82571.c 54.8 KB
Newer Older
1
2
3
/*******************************************************************************

  Intel PRO/1000 Linux driver
4
  Copyright(c) 1999 - 2011 Intel Corporation.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

/*
 * 82571EB Gigabit Ethernet Controller
31
 * 82571EB Gigabit Ethernet Controller (Copper)
32
 * 82571EB Gigabit Ethernet Controller (Fiber)
33
34
35
 * 82571EB Dual Port Gigabit Mezzanine Adapter
 * 82571EB Quad Port Gigabit Mezzanine Adapter
 * 82571PT Gigabit PT Quad Port Server ExpressModule
36
37
38
39
40
41
 * 82572EI Gigabit Ethernet Controller (Copper)
 * 82572EI Gigabit Ethernet Controller (Fiber)
 * 82572EI Gigabit Ethernet Controller
 * 82573V Gigabit Ethernet Controller (Copper)
 * 82573E Gigabit Ethernet Controller (Copper)
 * 82573L Gigabit Ethernet Controller
42
 * 82574L Gigabit Network Connection
43
 * 82583V Gigabit Network Connection
44
45
46
47
48
49
50
51
52
53
54
 */

#include "e1000.h"

#define ID_LED_RESERVED_F746 0xF746
#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
			      (ID_LED_OFF1_ON2  <<  8) | \
			      (ID_LED_DEF1_DEF2 <<  4) | \
			      (ID_LED_DEF1_DEF2))

#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
55
#define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */
56
57
58
59
#define E1000_BASE1000T_STATUS          10
#define E1000_IDLE_ERROR_COUNT_MASK     0xFF
#define E1000_RECEIVE_ERROR_COUNTER     21
#define E1000_RECEIVE_ERROR_MAX         0xFFFF
60

61
62
#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */

63
64
65
static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
66
static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
67
68
69
70
71
72
static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
				      u16 words, u16 *data);
static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
static s32 e1000_setup_link_82571(struct e1000_hw *hw);
static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73
static void e1000_clear_vfta_82571(struct e1000_hw *hw);
74
75
static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
static s32 e1000_led_on_82574(struct e1000_hw *hw);
76
static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77
static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
78
79
80
static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
81
82
static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
83
84
85
86
87
88
89
90
91
92

/**
 *  e1000_init_phy_params_82571 - Init PHY func ptrs.
 *  @hw: pointer to the HW structure
 **/
static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
{
	struct e1000_phy_info *phy = &hw->phy;
	s32 ret_val;

93
	if (hw->phy.media_type != e1000_media_type_copper) {
94
95
96
97
98
99
100
101
		phy->type = e1000_phy_none;
		return 0;
	}

	phy->addr			 = 1;
	phy->autoneg_mask		 = AUTONEG_ADVERTISE_SPEED_DEFAULT;
	phy->reset_delay_us		 = 100;

102
103
104
	phy->ops.power_up		 = e1000_power_up_phy_copper;
	phy->ops.power_down		 = e1000_power_down_phy_copper_82571;

105
106
107
108
109
110
111
112
	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
		phy->type		 = e1000_phy_igp_2;
		break;
	case e1000_82573:
		phy->type		 = e1000_phy_m88;
		break;
113
	case e1000_82574:
114
	case e1000_82583:
115
		phy->type		 = e1000_phy_bm;
116
117
		phy->ops.acquire = e1000_get_hw_semaphore_82574;
		phy->ops.release = e1000_put_hw_semaphore_82574;
118
119
		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
120
		break;
121
122
123
124
125
126
127
	default:
		return -E1000_ERR_PHY;
		break;
	}

	/* This can only be done after all function pointers are setup. */
	ret_val = e1000_get_phy_id_82571(hw);
128
129
130
131
	if (ret_val) {
		e_dbg("Error getting PHY ID\n");
		return ret_val;
	}
132
133
134
135
136
137

	/* Verify phy id */
	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
		if (phy->id != IGP01E1000_I_PHY_ID)
138
			ret_val = -E1000_ERR_PHY;
139
140
141
		break;
	case e1000_82573:
		if (phy->id != M88E1111_I_PHY_ID)
142
			ret_val = -E1000_ERR_PHY;
143
		break;
144
	case e1000_82574:
145
	case e1000_82583:
146
		if (phy->id != BME1000_E_PHY_ID_R2)
147
			ret_val = -E1000_ERR_PHY;
148
		break;
149
	default:
150
		ret_val = -E1000_ERR_PHY;
151
152
153
		break;
	}

154
155
156
157
	if (ret_val)
		e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);

	return ret_val;
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
}

/**
 *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 *  @hw: pointer to the HW structure
 **/
static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	u32 eecd = er32(EECD);
	u16 size;

	nvm->opcode_bits = 8;
	nvm->delay_usec = 1;
	switch (nvm->override) {
	case e1000_nvm_override_spi_large:
		nvm->page_size = 32;
		nvm->address_bits = 16;
		break;
	case e1000_nvm_override_spi_small:
		nvm->page_size = 8;
		nvm->address_bits = 8;
		break;
	default:
		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
		break;
	}

	switch (hw->mac.type) {
	case e1000_82573:
189
	case e1000_82574:
190
	case e1000_82583:
191
192
193
		if (((eecd >> 15) & 0x3) == 0x3) {
			nvm->type = e1000_nvm_flash_hw;
			nvm->word_size = 2048;
194
195
			/*
			 * Autonomous Flash update bit must be cleared due
196
197
198
199
200
201
202
203
			 * to Flash update issue.
			 */
			eecd &= ~E1000_EECD_AUPDEN;
			ew32(EECD, eecd);
			break;
		}
		/* Fall Through */
	default:
204
		nvm->type = e1000_nvm_eeprom_spi;
205
206
		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
				  E1000_EECD_SIZE_EX_SHIFT);
207
208
		/*
		 * Added to a constant, "size" becomes the left-shift value
209
210
211
		 * for setting word_size.
		 */
		size += NVM_WORD_SIZE_BASE_SHIFT;
212
213
214
215

		/* EEPROM access above 16k is unsupported */
		if (size > 14)
			size = 14;
216
217
218
219
		nvm->word_size	= 1 << size;
		break;
	}

220
221
222
223
224
225
226
227
228
229
230
	/* Function Pointers */
	switch (hw->mac.type) {
	case e1000_82574:
	case e1000_82583:
		nvm->ops.acquire = e1000_get_hw_semaphore_82574;
		nvm->ops.release = e1000_put_hw_semaphore_82574;
		break;
	default:
		break;
	}

231
232
233
234
235
236
237
238
239
240
241
242
	return 0;
}

/**
 *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 *  @hw: pointer to the HW structure
 **/
static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	struct e1000_mac_info *mac = &hw->mac;
	struct e1000_mac_operations *func = &mac->ops;
243
244
245
	u32 swsm = 0;
	u32 swsm2 = 0;
	bool force_clear_smbi = false;
246
247
248
249
250
251

	/* Set media type */
	switch (adapter->pdev->device) {
	case E1000_DEV_ID_82571EB_FIBER:
	case E1000_DEV_ID_82572EI_FIBER:
	case E1000_DEV_ID_82571EB_QUAD_FIBER:
252
		hw->phy.media_type = e1000_media_type_fiber;
253
254
255
		break;
	case E1000_DEV_ID_82571EB_SERDES:
	case E1000_DEV_ID_82572EI_SERDES:
256
257
	case E1000_DEV_ID_82571EB_SERDES_DUAL:
	case E1000_DEV_ID_82571EB_SERDES_QUAD:
258
		hw->phy.media_type = e1000_media_type_internal_serdes;
259
260
		break;
	default:
261
		hw->phy.media_type = e1000_media_type_copper;
262
263
264
265
266
267
268
		break;
	}

	/* Set mta register count */
	mac->mta_reg_count = 128;
	/* Set rar entry count */
	mac->rar_entry_count = E1000_RAR_ENTRIES;
269
270
	/* Adaptive IFS supported */
	mac->adaptive_ifs = true;
271
272

	/* check for link */
273
	switch (hw->phy.media_type) {
274
275
276
277
278
279
	case e1000_media_type_copper:
		func->setup_physical_interface = e1000_setup_copper_link_82571;
		func->check_for_link = e1000e_check_for_copper_link;
		func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
		break;
	case e1000_media_type_fiber:
280
281
		func->setup_physical_interface =
			e1000_setup_fiber_serdes_link_82571;
282
		func->check_for_link = e1000e_check_for_fiber_link;
283
284
		func->get_link_up_info =
			e1000e_get_speed_and_duplex_fiber_serdes;
285
286
		break;
	case e1000_media_type_internal_serdes:
287
288
		func->setup_physical_interface =
			e1000_setup_fiber_serdes_link_82571;
289
		func->check_for_link = e1000_check_for_serdes_link_82571;
290
291
		func->get_link_up_info =
			e1000e_get_speed_and_duplex_fiber_serdes;
292
293
294
295
296
297
		break;
	default:
		return -E1000_ERR_CONFIG;
		break;
	}

298
	switch (hw->mac.type) {
299
300
301
302
	case e1000_82573:
		func->set_lan_id = e1000_set_lan_id_single_port;
		func->check_mng_mode = e1000e_check_mng_mode_generic;
		func->led_on = e1000e_led_on_generic;
303
		func->blink_led = e1000e_blink_led_generic;
304
305
306
307
308
309
310
311
312
313

		/* FWSM register */
		mac->has_fwsm = true;
		/*
		 * ARC supported; valid only if manageability features are
		 * enabled.
		 */
		mac->arc_subsystem_valid =
			(er32(FWSM) & E1000_FWSM_MODE_MASK)
			? true : false;
314
		break;
315
	case e1000_82574:
316
	case e1000_82583:
317
		func->set_lan_id = e1000_set_lan_id_single_port;
318
319
320
321
322
323
		func->check_mng_mode = e1000_check_mng_mode_82574;
		func->led_on = e1000_led_on_82574;
		break;
	default:
		func->check_mng_mode = e1000e_check_mng_mode_generic;
		func->led_on = e1000e_led_on_generic;
324
		func->blink_led = e1000e_blink_led_generic;
325
326
327

		/* FWSM register */
		mac->has_fwsm = true;
328
329
330
		break;
	}

331
332
	/*
	 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
333
	 * first NVM or PHY access. This should be done for single-port
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
	 * devices, and for one port only on dual-port devices so that
	 * for those devices we can still use the SMBI lock to synchronize
	 * inter-port accesses to the PHY & NVM.
	 */
	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
		swsm2 = er32(SWSM2);

		if (!(swsm2 & E1000_SWSM2_LOCK)) {
			/* Only do this for the first interface on this card */
			ew32(SWSM2,
			    swsm2 | E1000_SWSM2_LOCK);
			force_clear_smbi = true;
		} else
			force_clear_smbi = false;
		break;
	default:
		force_clear_smbi = true;
		break;
	}

	if (force_clear_smbi) {
		/* Make sure SWSM.SMBI is clear */
		swsm = er32(SWSM);
		if (swsm & E1000_SWSM_SMBI) {
			/* This bit should not be set on a first interface, and
			 * indicates that the bootagent or EFI code has
			 * improperly left this bit enabled
			 */
364
			e_dbg("Please update your 82571 Bootagent\n");
365
366
367
368
369
		}
		ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
	}

	/*
Joe Perches's avatar
Joe Perches committed
370
	 * Initialize device specific counter of SMBI acquisition
371
372
373
374
	 * timeouts.
	 */
	 hw->dev_spec.e82571.smb_counter = 0;

375
376
377
	return 0;
}

Jeff Kirsher's avatar
Jeff Kirsher committed
378
static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
{
	struct e1000_hw *hw = &adapter->hw;
	static int global_quad_port_a; /* global port a indication */
	struct pci_dev *pdev = adapter->pdev;
	int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
	s32 rc;

	rc = e1000_init_mac_params_82571(adapter);
	if (rc)
		return rc;

	rc = e1000_init_nvm_params_82571(hw);
	if (rc)
		return rc;

	rc = e1000_init_phy_params_82571(hw);
	if (rc)
		return rc;

	/* tag quad port adapters first, it's used below */
	switch (pdev->device) {
	case E1000_DEV_ID_82571EB_QUAD_COPPER:
	case E1000_DEV_ID_82571EB_QUAD_FIBER:
	case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
403
	case E1000_DEV_ID_82571PT_QUAD_COPPER:
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
		adapter->flags |= FLAG_IS_QUAD_PORT;
		/* mark the first port */
		if (global_quad_port_a == 0)
			adapter->flags |= FLAG_IS_QUAD_PORT_A;
		/* Reset for multiple quad port adapters */
		global_quad_port_a++;
		if (global_quad_port_a == 4)
			global_quad_port_a = 0;
		break;
	default:
		break;
	}

	switch (adapter->hw.mac.type) {
	case e1000_82571:
		/* these dual ports don't have WoL on port B at all */
		if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
		     (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
		     (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
		    (is_port_b))
			adapter->flags &= ~FLAG_HAS_WOL;
		/* quad ports only support WoL on port A */
		if (adapter->flags & FLAG_IS_QUAD_PORT &&
Roel Kluin's avatar
Roel Kluin committed
427
		    (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
428
			adapter->flags &= ~FLAG_HAS_WOL;
429
430
431
		/* Does not support WoL on any port */
		if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
			adapter->flags &= ~FLAG_HAS_WOL;
432
433
434
		break;
	case e1000_82573:
		if (pdev->device == E1000_DEV_ID_82573L) {
435
436
			adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
			adapter->max_hw_frame_size = DEFAULT_JUMBO;
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
		}
		break;
	default:
		break;
	}

	return 0;
}

/**
 *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 *  @hw: pointer to the HW structure
 *
 *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 *  revision in the hardware structure.
 **/
static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
{
	struct e1000_phy_info *phy = &hw->phy;
456
457
	s32 ret_val;
	u16 phy_id = 0;
458
459
460
461

	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
462
463
		/*
		 * The 82571 firmware may still be configuring the PHY.
464
465
		 * In this case, we cannot access the PHY until the
		 * configuration is done.  So we explicitly set the
466
467
		 * PHY ID.
		 */
468
469
470
471
472
		phy->id = IGP01E1000_I_PHY_ID;
		break;
	case e1000_82573:
		return e1000e_get_phy_id(hw);
		break;
473
	case e1000_82574:
474
	case e1000_82583:
475
476
477
478
479
480
481
482
483
484
485
486
487
		ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
		if (ret_val)
			return ret_val;

		phy->id = (u32)(phy_id << 16);
		udelay(20);
		ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
		if (ret_val)
			return ret_val;

		phy->id |= (u32)(phy_id);
		phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
		break;
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
	default:
		return -E1000_ERR_PHY;
		break;
	}

	return 0;
}

/**
 *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Acquire the HW semaphore to access the PHY or NVM
 **/
static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
{
	u32 swsm;
505
506
	s32 sw_timeout = hw->nvm.word_size + 1;
	s32 fw_timeout = hw->nvm.word_size + 1;
507
508
	s32 i = 0;

509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
	/*
	 * If we have timedout 3 times on trying to acquire
	 * the inter-port SMBI semaphore, there is old code
	 * operating on the other port, and it is not
	 * releasing SMBI. Modify the number of times that
	 * we try for the semaphore to interwork with this
	 * older code.
	 */
	if (hw->dev_spec.e82571.smb_counter > 2)
		sw_timeout = 1;

	/* Get the SW semaphore */
	while (i < sw_timeout) {
		swsm = er32(SWSM);
		if (!(swsm & E1000_SWSM_SMBI))
			break;

		udelay(50);
		i++;
	}

	if (i == sw_timeout) {
531
		e_dbg("Driver can't access device - SMBI bit is set.\n");
532
533
		hw->dev_spec.e82571.smb_counter++;
	}
534
	/* Get the FW semaphore. */
535
	for (i = 0; i < fw_timeout; i++) {
536
537
538
539
540
541
542
543
544
545
		swsm = er32(SWSM);
		ew32(SWSM, swsm | E1000_SWSM_SWESMBI);

		/* Semaphore acquired if bit latched */
		if (er32(SWSM) & E1000_SWSM_SWESMBI)
			break;

		udelay(50);
	}

546
	if (i == fw_timeout) {
547
		/* Release semaphores */
548
		e1000_put_hw_semaphore_82571(hw);
549
		e_dbg("Driver can't access the NVM\n");
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
		return -E1000_ERR_NVM;
	}

	return 0;
}

/**
 *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Release hardware semaphore used to access the PHY or NVM
 **/
static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
{
	u32 swsm;

	swsm = er32(SWSM);
567
	swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
568
569
	ew32(SWSM, swsm);
}
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
/**
 *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Acquire the HW semaphore during reset.
 *
 **/
static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
{
	u32 extcnf_ctrl;
	s32 ret_val = 0;
	s32 i = 0;

	extcnf_ctrl = er32(EXTCNF_CTRL);
	extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
	do {
		ew32(EXTCNF_CTRL, extcnf_ctrl);
		extcnf_ctrl = er32(EXTCNF_CTRL);

		if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
			break;

		extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;

594
		usleep_range(2000, 4000);
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
		i++;
	} while (i < MDIO_OWNERSHIP_TIMEOUT);

	if (i == MDIO_OWNERSHIP_TIMEOUT) {
		/* Release semaphores */
		e1000_put_hw_semaphore_82573(hw);
		e_dbg("Driver can't access the PHY\n");
		ret_val = -E1000_ERR_PHY;
		goto out;
	}

out:
	return ret_val;
}

/**
 *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Release hardware semaphore used during reset.
 *
 **/
static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
{
	u32 extcnf_ctrl;

	extcnf_ctrl = er32(EXTCNF_CTRL);
	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
	ew32(EXTCNF_CTRL, extcnf_ctrl);
}

static DEFINE_MUTEX(swflag_mutex);

/**
 *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Acquire the HW semaphore to access the PHY or NVM.
 *
 **/
static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
{
	s32 ret_val;

	mutex_lock(&swflag_mutex);
	ret_val = e1000_get_hw_semaphore_82573(hw);
	if (ret_val)
		mutex_unlock(&swflag_mutex);
	return ret_val;
}

/**
 *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 *  @hw: pointer to the HW structure
 *
 *  Release hardware semaphore used to access the PHY or NVM
 *
 **/
static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
{
	e1000_put_hw_semaphore_82573(hw);
	mutex_unlock(&swflag_mutex);
}
658

659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
/**
 *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 *  @hw: pointer to the HW structure
 *  @active: true to enable LPLU, false to disable
 *
 *  Sets the LPLU D0 state according to the active flag.
 *  LPLU will not be activated unless the
 *  device autonegotiation advertisement meets standards of
 *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 *  This is a function pointer entry point only called by
 *  PHY setup routines.
 **/
static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
{
	u16 data = er32(POEMB);

	if (active)
		data |= E1000_PHY_CTRL_D0A_LPLU;
	else
		data &= ~E1000_PHY_CTRL_D0A_LPLU;

	ew32(POEMB, data);
	return 0;
}

/**
 *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 *  @hw: pointer to the HW structure
 *  @active: boolean used to enable/disable lplu
 *
 *  The low power link up (lplu) state is set to the power management level D3
 *  when active is true, else clear lplu for D3. LPLU
 *  is used during Dx states where the power conservation is most important.
 *  During driver activity, SmartSpeed should be enabled so performance is
 *  maintained.
 **/
static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
{
	u16 data = er32(POEMB);

	if (!active) {
		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
		data |= E1000_PHY_CTRL_NOND0A_LPLU;
	}

	ew32(POEMB, data);
	return 0;
}

711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
/**
 *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 *  @hw: pointer to the HW structure
 *
 *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 *  for EEPROM access grant bit.  If the access grant bit is not set, release
 *  hardware semaphore.
 **/
static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
{
	s32 ret_val;

	ret_val = e1000_get_hw_semaphore_82571(hw);
	if (ret_val)
		return ret_val;

728
729
730
731
	switch (hw->mac.type) {
	case e1000_82573:
		break;
	default:
732
		ret_val = e1000e_acquire_nvm(hw);
733
734
		break;
	}
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763

	if (ret_val)
		e1000_put_hw_semaphore_82571(hw);

	return ret_val;
}

/**
 *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 *  @hw: pointer to the HW structure
 *
 *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 **/
static void e1000_release_nvm_82571(struct e1000_hw *hw)
{
	e1000e_release_nvm(hw);
	e1000_put_hw_semaphore_82571(hw);
}

/**
 *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 *  @hw: pointer to the HW structure
 *  @offset: offset within the EEPROM to be written to
 *  @words: number of words to write
 *  @data: 16 bit word(s) to be written to the EEPROM
 *
 *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 *
 *  If e1000e_update_nvm_checksum is not called after this function, the
764
 *  EEPROM will most likely contain an invalid checksum.
765
766
767
768
769
770
771
772
 **/
static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
				 u16 *data)
{
	s32 ret_val;

	switch (hw->mac.type) {
	case e1000_82573:
773
	case e1000_82574:
774
	case e1000_82583:
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
		ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
		break;
	case e1000_82571:
	case e1000_82572:
		ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
		break;
	default:
		ret_val = -E1000_ERR_NVM;
		break;
	}

	return ret_val;
}

/**
 *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 *  @hw: pointer to the HW structure
 *
 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 *  value to the EEPROM.
 **/
static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
{
	u32 eecd;
	s32 ret_val;
	u16 i;

	ret_val = e1000e_update_nvm_checksum_generic(hw);
	if (ret_val)
		return ret_val;

807
808
809
810
	/*
	 * If our nvm is an EEPROM, then we're done
	 * otherwise, commit the checksum to the flash NVM.
	 */
811
812
813
814
815
	if (hw->nvm.type != e1000_nvm_flash_hw)
		return ret_val;

	/* Check for pending operations. */
	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
816
		usleep_range(1000, 2000);
817
818
819
820
821
822
823
824
825
		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
			break;
	}

	if (i == E1000_FLASH_UPDATES)
		return -E1000_ERR_NVM;

	/* Reset the firmware if using STM opcode. */
	if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
826
827
		/*
		 * The enabling of and the actual reset must be done
828
829
830
831
832
833
834
835
836
837
838
839
		 * in two write cycles.
		 */
		ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
		e1e_flush();
		ew32(HICR, E1000_HICR_FW_RESET);
	}

	/* Commit the write to flash */
	eecd = er32(EECD) | E1000_EECD_FLUPD;
	ew32(EECD, eecd);

	for (i = 0; i < E1000_FLASH_UPDATES; i++) {
840
		usleep_range(1000, 2000);
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
		if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
			break;
	}

	if (i == E1000_FLASH_UPDATES)
		return -E1000_ERR_NVM;

	return 0;
}

/**
 *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 *  @hw: pointer to the HW structure
 *
 *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 **/
static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
{
	if (hw->nvm.type == e1000_nvm_flash_hw)
		e1000_fix_nvm_checksum_82571(hw);

	return e1000e_validate_nvm_checksum_generic(hw);
}

/**
 *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 *  @hw: pointer to the HW structure
 *  @offset: offset within the EEPROM to be written to
 *  @words: number of words to write
 *  @data: 16 bit word(s) to be written to the EEPROM
 *
 *  After checking for invalid values, poll the EEPROM to ensure the previous
 *  command has completed before trying to write the next word.  After write
 *  poll for completion.
 *
 *  If e1000e_update_nvm_checksum is not called after this function, the
878
 *  EEPROM will most likely contain an invalid checksum.
879
880
881
882
883
 **/
static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
				      u16 words, u16 *data)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
884
	u32 i, eewr = 0;
885
886
	s32 ret_val = 0;

887
888
889
890
	/*
	 * A check for invalid values:  offset too large, too many words,
	 * and not enough words.
	 */
891
892
	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
	    (words == 0)) {
893
		e_dbg("nvm parameter(s) out of bounds\n");
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
		return -E1000_ERR_NVM;
	}

	for (i = 0; i < words; i++) {
		eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
		       ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
		       E1000_NVM_RW_REG_START;

		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
		if (ret_val)
			break;

		ew32(EEWR, eewr);

		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
		if (ret_val)
			break;
	}

	return ret_val;
}

/**
 *  e1000_get_cfg_done_82571 - Poll for configuration done
 *  @hw: pointer to the HW structure
 *
 *  Reads the management control register for the config done bit to be set.
 **/
static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
{
	s32 timeout = PHY_CFG_TIMEOUT;

	while (timeout) {
		if (er32(EEMNGCTL) &
		    E1000_NVM_CFG_DONE_PORT_0)
			break;
930
		usleep_range(1000, 2000);
931
932
933
		timeout--;
	}
	if (!timeout) {
934
		e_dbg("MNG configuration cycle has not completed.\n");
935
936
937
938
939
940
941
942
943
		return -E1000_ERR_RESET;
	}

	return 0;
}

/**
 *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 *  @hw: pointer to the HW structure
944
 *  @active: true to enable LPLU, false to disable
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
 *
 *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 *  this function also disables smart speed and vice versa.  LPLU will not be
 *  activated unless the device autonegotiation advertisement meets standards
 *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 *  pointer entry point only called by PHY setup routines.
 **/
static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
{
	struct e1000_phy_info *phy = &hw->phy;
	s32 ret_val;
	u16 data;

	ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
	if (ret_val)
		return ret_val;

	if (active) {
		data |= IGP02E1000_PM_D0_LPLU;
		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
		if (ret_val)
			return ret_val;

		/* When LPLU is enabled, we should disable SmartSpeed */
		ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
		ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
		if (ret_val)
			return ret_val;
	} else {
		data &= ~IGP02E1000_PM_D0_LPLU;
		ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
977
978
		/*
		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
979
980
		 * during Dx states where the power conservation is most
		 * important.  During driver activity we should enable
981
982
		 * SmartSpeed, so performance is maintained.
		 */
983
984
		if (phy->smart_speed == e1000_smart_speed_on) {
			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
985
					   &data);
986
987
988
989
990
			if (ret_val)
				return ret_val;

			data |= IGP01E1000_PSCFR_SMART_SPEED;
			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
991
					   data);
992
993
994
995
			if (ret_val)
				return ret_val;
		} else if (phy->smart_speed == e1000_smart_speed_off) {
			ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
996
					   &data);
997
998
999
1000
1001
			if (ret_val)
				return ret_val;

			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
			ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1002
					   data);
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
			if (ret_val)
				return ret_val;
		}
	}

	return 0;
}

/**
 *  e1000_reset_hw_82571 - Reset hardware
 *  @hw: pointer to the HW structure
 *
1015
 *  This resets the hardware into a known state.
1016
1017
1018
 **/
static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
{
1019
	u32 ctrl, ctrl_ext;
1020
1021
	s32 ret_val;

1022
1023
	/*
	 * Prevent the PCI-E bus from sticking if there is no TLP connection
1024
1025
1026
1027
	 * on the last TLP read/write transaction when MAC is reset.
	 */
	ret_val = e1000e_disable_pcie_master(hw);
	if (ret_val)
1028
		e_dbg("PCI-E Master disable polling has failed.\n");
1029

1030
	e_dbg("Masking off all interrupts\n");
1031
1032
1033
1034
1035
1036
	ew32(IMC, 0xffffffff);

	ew32(RCTL, 0);
	ew32(TCTL, E1000_TCTL_PSP);
	e1e_flush();

1037
	usleep_range(10000, 20000);
1038

1039
1040
1041
1042
	/*
	 * Must acquire the MDIO ownership before MAC reset.
	 * Ownership defaults to firmware after a reset.
	 */
1043
1044
	switch (hw->mac.type) {
	case e1000_82573:
1045
1046
		ret_val = e1000_get_hw_semaphore_82573(hw);
		break;
1047
1048
	case e1000_82574:
	case e1000_82583:
1049
		ret_val = e1000_get_hw_semaphore_82574(hw);
1050
1051
1052
		break;
	default:
		break;
1053
	}
1054
1055
	if (ret_val)
		e_dbg("Cannot acquire MDIO ownership\n");
1056
1057
1058

	ctrl = er32(CTRL);

1059
	e_dbg("Issuing a global reset to MAC\n");
1060
1061
	ew32(CTRL, ctrl | E1000_CTRL_RST);

1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
	/* Must release MDIO ownership and mutex after MAC reset. */
	switch (hw->mac.type) {
	case e1000_82574:
	case e1000_82583:
		e1000_put_hw_semaphore_82574(hw);
		break;
	default:
		break;
	}

1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
	if (hw->nvm.type == e1000_nvm_flash_hw) {
		udelay(10);
		ctrl_ext = er32(CTRL_EXT);
		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
		ew32(CTRL_EXT, ctrl_ext);
		e1e_flush();
	}

	ret_val = e1000e_get_auto_rd_done(hw);
	if (ret_val)
		/* We don't want to continue accessing MAC registers. */
		return ret_val;

1085
1086
	/*
	 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1087
1088
1089
	 * Need to wait for Phy configuration completion before accessing
	 * NVM and Phy.
	 */
1090
1091
1092
1093
1094

	switch (hw->mac.type) {
	case e1000_82573:
	case e1000_82574:
	case e1000_82583:
1095
		msleep(25);
1096
1097
1098
1099
		break;
	default:
		break;
	}
1100
1101
1102

	/* Clear any pending interrupt events. */
	ew32(IMC, 0xffffffff);
1103
	er32(ICR);
1104

1105
1106
1107
1108
1109
	if (hw->mac.type == e1000_82571) {
		/* Install any alternate MAC address into RAR0 */
		ret_val = e1000_check_alt_mac_addr_generic(hw);
		if (ret_val)
			return ret_val;
1110

1111
1112
		e1000e_set_laa_state_82571(hw, true);
	}
1113

1114
1115
1116
1117
	/* Reinitialize the 82571 serdes link state machine */
	if (hw->phy.media_type == e1000_media_type_internal_serdes)
		hw->mac.serdes_link_state = e1000_serdes_link_down;

1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
	return 0;
}

/**
 *  e1000_init_hw_82571 - Initialize hardware
 *  @hw: pointer to the HW structure
 *
 *  This inits the hardware readying it for operation.
 **/
static s32 e1000_init_hw_82571(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	u32 reg_data;
	s32 ret_val;
1132
	u16 i, rar_count = mac->rar_entry_count;
1133
1134
1135
1136
1137

	e1000_initialize_hw_bits_82571(hw);

	/* Initialize identification LED */
	ret_val = e1000e_id_led_init(hw);
1138
	if (ret_val)
1139
		e_dbg("Error initializing identification LED\n");
1140
		/* This is not fatal and we should not stop init due to this */
1141
1142

	/* Disabling VLAN filtering */
1143
	e_dbg("Initializing the IEEE VLAN\n");
1144
	mac->ops.clear_vfta(hw);
1145
1146

	/* Setup the receive address. */
1147
1148
	/*
	 * If, however, a locally administered address was assigned to the
1149
1150
1151
1152
1153
1154
1155
1156
	 * 82571, we must reserve a RAR for it to work around an issue where
	 * resetting one port will reload the MAC on the other port.
	 */
	if (e1000e_get_laa_state_82571(hw))
		rar_count--;
	e1000e_init_rx_addrs(hw, rar_count);

	/* Zero out the Multicast HASH table */
1157
	e_dbg("Zeroing the MTA\n");
1158
1159
1160
1161
1162
1163
1164
	for (i = 0; i < mac->mta_reg_count; i++)
		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

	/* Setup link and flow control */
	ret_val = e1000_setup_link_82571(hw);

	/* Set the transmit descriptor write-back policy */
1165
	reg_data = er32(TXDCTL(0));
1166
1167
1168
	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
		   E1000_TXDCTL_FULL_TX_DESC_WB |
		   E1000_TXDCTL_COUNT_DESC;
1169
	ew32(TXDCTL(0), reg_data);
1170
1171

	/* ...for both queues. */
1172
1173
	switch (mac->type) {
	case e1000_82573:
1174
1175
		e1000e_enable_tx_pkt_filtering(hw);
		/* fall through */
1176
1177
1178
1179
1180
1181
1182
	case e1000_82574:
	case e1000_82583:
		reg_data = er32(GCR);
		reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
		ew32(GCR, reg_data);
		break;
	default:
1183
		reg_data = er32(TXDCTL(1));
1184
1185
1186
		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
			   E1000_TXDCTL_FULL_TX_DESC_WB |
			   E1000_TXDCTL_COUNT_DESC;
1187
		ew32(TXDCTL(1), reg_data);
1188
		break;
1189
1190
	}

1191
1192
	/*
	 * Clear all of the statistics registers (clear on read).  It is
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
	 * important that we do this after we have tried to establish link
	 * because the symbol error count will increment wildly if there
	 * is no link.
	 */
	e1000_clear_hw_cntrs_82571(hw);

	return ret_val;
}

/**
 *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
 *  @hw: pointer to the HW structure
 *
 *  Initializes required hardware-dependent bits needed for normal operation.
 **/
static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
{
	u32 reg;

	/* Transmit Descriptor Control 0 */
1213
	reg = er32(TXDCTL(0));
1214
	reg |= (1 << 22);
1215
	ew32(TXDCTL(0), reg);
1216
1217

	/* Transmit Descriptor Control 1 */
1218
	reg = er32(TXDCTL(1));
1219
	reg |= (1 << 22);
1220
	ew32(TXDCTL(1), reg);
1221
1222

	/* Transmit Arbitration Control 0 */
1223
	reg = er32(TARC(0));
1224
1225
1226
1227
1228
1229
	reg &= ~(0xF << 27); /* 30:27 */
	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
		break;
1230
1231
1232
1233
	case e1000_82574:
	case e1000_82583:
		reg |= (1 << 26);
		break;
1234
1235
1236
	default:
		break;
	}
1237
	ew32(TARC(0), reg);
1238
1239

	/* Transmit Arbitration Control 1 */
1240
	reg = er32(TARC(1));
1241
1242
1243
1244
1245
1246
1247
1248
1249
	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
		reg &= ~((1 << 29) | (1 << 30));
		reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
		if (er32(TCTL) & E1000_TCTL_MULR)
			reg &= ~(1 << 28);
		else
			reg |= (1 << 28);
1250
		ew32(TARC(1), reg);
1251
1252
1253
1254
1255
1256
		break;
	default:
		break;
	}

	/* Device Control */
1257
1258
1259
1260
	switch (hw->mac.type) {
	case e1000_82573:
	case e1000_82574:
	case e1000_82583:
1261
1262
1263
		reg = er32(CTRL);
		reg &= ~(1 << 29);
		ew32(CTRL, reg);
1264
1265
1266
		break;
	default:
		break;
1267
1268
1269
	}

	/* Extended Device Control */
1270
1271
1272
1273
	switch (hw->mac.type) {
	case e1000_82573:
	case e1000_82574:
	case e1000_82583:
1274
1275
1276
1277
		reg = er32(CTRL_EXT);
		reg &= ~(1 << 23);
		reg |= (1 << 22);
		ew32(CTRL_EXT, reg);
1278
1279
1280
		break;
	default:
		break;
1281
	}
1282

1283
1284
1285
1286
1287
	if (hw->mac.type == e1000_82571) {
		reg = er32(PBA_ECC);
		reg |= E1000_PBA_ECC_CORR_EN;
		ew32(PBA_ECC, reg);
	}
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
	/*
	 * Workaround for hardware errata.
	 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
	 */

        if ((hw->mac.type == e1000_82571) ||
           (hw->mac.type == e1000_82572)) {
                reg = er32(CTRL_EXT);
                reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
                ew32(CTRL_EXT, reg);
        }

1300

1301
	/* PCI-Ex Control Registers */
1302
1303
1304
	switch (hw->mac.type) {
	case e1000_82574:
	case e1000_82583:
1305
1306
1307
		reg = er32(GCR);
		reg |= (1 << 22);
		ew32(GCR, reg);
1308

1309
1310
1311
1312
1313
		/*
		 * Workaround for hardware errata.
		 * apply workaround for hardware errata documented in errata
		 * docs Fixes issue where some error prone or unreliable PCIe
		 * completions are occurring, particularly with ASPM enabled.
1314
		 * Without fix, issue can cause Tx timeouts.
1315
		 */
1316
1317
1318
		reg = er32(GCR2);
		reg |= 1;
		ew32(GCR2, reg);
1319
1320
1321
		break;
	default:
		break;
1322
	}
1323
1324
1325
}

/**
1326
 *  e1000_clear_vfta_82571 - Clear VLAN filter table
1327
1328
1329
1330
1331
 *  @hw: pointer to the HW structure
 *
 *  Clears the register array which contains the VLAN filter table by
 *  setting all the values to 0.
 **/
1332
static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1333
1334
1335
1336
1337
1338
{
	u32 offset;
	u32 vfta_value = 0;
	u32 vfta_offset = 0;
	u32 vfta_bit_in_reg = 0;

1339
1340
1341
1342
	switch (hw->mac.type) {
	case e1000_82573:
	case e1000_82574:
	case e1000_82583:
1343
		if (hw->mng_cookie.vlan_id != 0) {
1344
1345
			/*
			 * The VFTA is a 4096b bit-field, each identifying
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
			 * a single VLAN ID.  The following operations
			 * determine which 32b entry (i.e. offset) into the
			 * array we want to set the VLAN ID (i.e. bit) of
			 * the manageability unit.
			 */
			vfta_offset = (hw->mng_cookie.vlan_id >>
				       E1000_VFTA_ENTRY_SHIFT) &
				      E1000_VFTA_ENTRY_MASK;
			vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
					       E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
		}
1357
1358
1359
		break;
	default:
		break;
1360
1361
	}
	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1362
1363
		/*
		 * If the offset we want to clear is the same offset of the
1364
1365
1366
1367
1368
1369
1370
1371
1372
		 * manageability VLAN ID, then clear all bits except that of
		 * the manageability unit.
		 */
		vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
		e1e_flush();
	}
}

1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
/**
 *  e1000_check_mng_mode_82574 - Check manageability is enabled
 *  @hw: pointer to the HW structure
 *
 *  Reads the NVM Initialization Control Word 2 and returns true
 *  (>0) if any manageability is enabled, else false (0).
 **/
static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
{
	u16 data;

	e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
	return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
}

/**
 *  e1000_led_on_82574 - Turn LED on
 *  @hw: pointer to the HW structure
 *
 *  Turn LED on.
 **/
static s32 e1000_led_on_82574(struct e1000_hw *hw)
{
	u32 ctrl;
	u32 i;

	ctrl = hw->mac.ledctl_mode2;
	if (!(E1000_STATUS_LU & er32(STATUS))) {
		/*
		 * If no link, then turn LED on by setting the invert bit
		 * for each LED that's "on" (0x0E) in ledctl_mode2.
		 */
		for (i = 0; i < 4; i++)
			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
			    E1000_LEDCTL_MODE_LED_ON)
				ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
	}
	ew32(LEDCTL, ctrl);

	return 0;
}

1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
/**
 *  e1000_check_phy_82574 - check 82574 phy hung state
 *  @hw: pointer to the HW structure
 *
 *  Returns whether phy is hung or not
 **/
bool e1000_check_phy_82574(struct e1000_hw *hw)
{
	u16 status_1kbt = 0;
	u16 receive_errors = 0;
	bool phy_hung = false;
	s32 ret_val = 0;

	/*
	 * Read PHY Receive Error counter first, if its is max - all F's then
	 * read the Base1000T status register If both are max then PHY is hung.
	 */
	ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);

	if (ret_val)
		goto out;
	if (receive_errors == E1000_RECEIVE_ERROR_MAX)  {
		ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
		if (ret_val)
			goto out;
		if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
		    E1000_IDLE_ERROR_COUNT_MASK)
			phy_hung = true;
	}
out:
	return phy_hung;
}

1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
/**
 *  e1000_setup_link_82571 - Setup flow control and link settings
 *  @hw: pointer to the HW structure
 *
 *  Determines which flow control settings to use, then configures flow
 *  control.  Calls the appropriate media-specific link configuration
 *  function.  Assuming the adapter has a valid link partner, a valid link
 *  should be established.  Assumes the hardware has previously been reset
 *  and the transmitter and receiver are not enabled.
 **/
static s32 e1000_setup_link_82571(struct e1000_hw *hw)
{
1460
1461
	/*
	 * 82573 does not have a word in the NVM to determine
1462
1463
1464
	 * the default flow control setting, so we explicitly
	 * set it to full.
	 */
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
	switch (hw->mac.type) {
	case e1000_82573:
	case e1000_82574:
	case e1000_82583:
		if (hw->fc.requested_mode == e1000_fc_default)
			hw->fc.requested_mode = e1000_fc_full;
		break;
	default:
		break;
	}
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498

	return e1000e_setup_link(hw);
}

/**
 *  e1000_setup_copper_link_82571 - Configure copper link settings
 *  @hw: pointer to the HW structure
 *
 *  Configures the link for auto-neg or forced speed and duplex.  Then we check
 *  for link, once link is established calls to configure collision distance
 *  and flow control are called.
 **/
static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
{
	u32 ctrl;
	s32 ret_val;

	ctrl = er32(CTRL);
	ctrl |= E1000_CTRL_SLU;
	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
	ew32(CTRL, ctrl);

	switch (hw->phy.type) {
	case e1000_phy_m88:
1499
	case e1000_phy_bm:
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
		ret_val = e1000e_copper_link_setup_m88(hw);
		break;
	case e1000_phy_igp_2:
		ret_val = e1000e_copper_link_setup_igp(hw);
		break;
	default:
		return -E1000_ERR_PHY;
		break;
	}

	if (ret_val)
		return ret_val;

	ret_val = e1000e_setup_copper_link(hw);

	return ret_val;
}

/**
 *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
 *  @hw: pointer to the HW structure
 *
 *  Configures collision distance and flow control for fiber and serdes links.
 *  Upon successful setup, poll for link.
 **/
static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
{
	switch (hw->mac.type) {
	case e1000_82571:
	case e1000_82572:
1530
1531
		/*
		 * If SerDes loopback mode is entered, there is no form
1532
1533
		 * of reset to take the adapter out of that mode.  So we
		 * have to explicitly take the adapter out of loopback
1534
		 * mode.  This prevents drivers from twiddling their thumbs
1535
1536
		 * if another tool failed to take it out of loopback mode.
		 */
1537
		ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1538
1539
1540
1541
1542
1543
1544
1545
		break;
	default:
		break;
	}

	return e1000e_setup_fiber_serdes_link(hw);
}

1546
1547
1548
1549
/**
 *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
 *  @hw: pointer to the HW structure
 *
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
 *  Reports the link state as up or down.
 *
 *  If autonegotiation is supported by the link partner, the link state is
 *  determined by the result of autonegotiation. This is the most likely case.
 *  If autonegotiation is not supported by the link partner, and the link
 *  has a valid signal, force the link up.
 *
 *  The link state is represented internally here by 4 states:
 *
 *  1) down
 *  2) autoneg_progress
1561
 *  3) autoneg_complete (the link successfully autonegotiated)
1562
1563
 *  4) forced_up (the link has been forced up, it did not autonegotiate)
 *
1564
 **/
1565
static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1566
1567
1568
1569
1570
{
	struct e1000_mac_info *mac = &hw->mac;
	u32 rxcw;
	u32 ctrl;
	u32 status;
1571
1572
	u32 txcw;
	u32 i;
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
	s32 ret_val = 0;

	ctrl = er32(CTRL);
	status = er32(STATUS);
	rxcw = er32(RXCW);

	if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {

		/* Receiver is synchronized with no invalid bits.  */
		switch (mac->serdes_link_state) {
		case e1000_serdes_link_autoneg_complete:
			if (!(status & E1000_STATUS_LU)) {
				/*
				 * We have lost link, retry autoneg before
				 * reporting link failure
				 */
				mac->serdes_link_state =
				    e1000_serdes_link_autoneg_progress;
1591
				mac->serdes_has_link = false;
1592
				e_dbg("AN_UP     -> AN_PROG\n");
1593
1594
			} else {
				mac->serdes_has_link = true;
1595
			}
1596
			break;
1597
1598
1599
1600