omap_hwmod_44xx_data.c 94 KB
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/*
 * Hardware modules present on the OMAP44xx chips
 *
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 * Copyright (C) 2009-2011 Texas Instruments, Inc.
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 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley
 * Benoit Cousson
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>

#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
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#include <plat/gpio.h>
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#include <plat/dma.h>
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#include "omap_hwmod_common_data.h"

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#include "cm1_44xx.h"
#include "cm2_44xx.h"
#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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#include "wd_timer.h"
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/* Base offset for all OMAP4 interrupts external to MPUSS */
#define OMAP44XX_IRQ_GIC_START	32

/* Base offset for all OMAP4 dma requests */
#define OMAP44XX_DMA_REQ_START  1

/* Backward references (IPs with Bus Master capability) */
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static struct omap_hwmod omap44xx_dma_system_hwmod;
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static struct omap_hwmod omap44xx_dmm_hwmod;
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static struct omap_hwmod omap44xx_dsp_hwmod;
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static struct omap_hwmod omap44xx_dss_hwmod;
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static struct omap_hwmod omap44xx_emif_fw_hwmod;
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static struct omap_hwmod omap44xx_iva_hwmod;
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static struct omap_hwmod omap44xx_l3_instr_hwmod;
static struct omap_hwmod omap44xx_l3_main_1_hwmod;
static struct omap_hwmod omap44xx_l3_main_2_hwmod;
static struct omap_hwmod omap44xx_l3_main_3_hwmod;
static struct omap_hwmod omap44xx_l4_abe_hwmod;
static struct omap_hwmod omap44xx_l4_cfg_hwmod;
static struct omap_hwmod omap44xx_l4_per_hwmod;
static struct omap_hwmod omap44xx_l4_wkup_hwmod;
static struct omap_hwmod omap44xx_mpu_hwmod;
static struct omap_hwmod omap44xx_mpu_private_hwmod;

/*
 * Interconnects omap_hwmod structures
 * hwmods that compose the global OMAP interconnect
 */

/*
 * 'dmm' class
 * instance(s): dmm
 */
static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
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	.name	= "dmm",
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};

/* dmm interface data */
/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_dmm_hwmod,
	.clk		= "l3_div_ck",
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	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
	{
		.pa_start	= 0x4e000000,
		.pa_end		= 0x4e0007ff,
		.flags		= ADDR_TYPE_RT
	},
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};

/* mpu -> dmm */
static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_dmm_hwmod,
	.clk		= "l3_div_ck",
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	.addr		= omap44xx_dmm_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dmm_addrs),
	.user		= OCP_USER_MPU,
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};

/* dmm slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
	&omap44xx_l3_main_1__dmm,
	&omap44xx_mpu__dmm,
};

static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
	{ .irq = 113 + OMAP44XX_IRQ_GIC_START },
};

static struct omap_hwmod omap44xx_dmm_hwmod = {
	.name		= "dmm",
	.class		= &omap44xx_dmm_hwmod_class,
	.slaves		= omap44xx_dmm_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dmm_slaves),
	.mpu_irqs	= omap44xx_dmm_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dmm_irqs),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'emif_fw' class
 * instance(s): emif_fw
 */
static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
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	.name	= "emif_fw",
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};

/* emif_fw interface data */
/* dmm -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
	.master		= &omap44xx_dmm_hwmod,
	.slave		= &omap44xx_emif_fw_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
	{
		.pa_start	= 0x4a20c000,
		.pa_end		= 0x4a20c0ff,
		.flags		= ADDR_TYPE_RT
	},
};

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/* l4_cfg -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_emif_fw_hwmod,
	.clk		= "l4_div_ck",
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	.addr		= omap44xx_emif_fw_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_emif_fw_addrs),
	.user		= OCP_USER_MPU,
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};

/* emif_fw slave ports */
static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
	&omap44xx_dmm__emif_fw,
	&omap44xx_l4_cfg__emif_fw,
};

static struct omap_hwmod omap44xx_emif_fw_hwmod = {
	.name		= "emif_fw",
	.class		= &omap44xx_emif_fw_hwmod_class,
	.slaves		= omap44xx_emif_fw_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_emif_fw_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'l3' class
 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 */
static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
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	.name	= "l3",
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};

/* l3_instr interface data */
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/* iva -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
	.master		= &omap44xx_iva_hwmod,
	.slave		= &omap44xx_l3_instr_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_3 -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
	.master		= &omap44xx_l3_main_3_hwmod,
	.slave		= &omap44xx_l3_instr_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_instr slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
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	&omap44xx_iva__l3_instr,
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	&omap44xx_l3_main_3__l3_instr,
};

static struct omap_hwmod omap44xx_l3_instr_hwmod = {
	.name		= "l3_instr",
	.class		= &omap44xx_l3_hwmod_class,
	.slaves		= omap44xx_l3_instr_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_instr_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/* l3_main_1 interface data */
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/* dsp -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* dss -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
	.master		= &omap44xx_dss_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_2 -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_l3_main_1_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
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	&omap44xx_dsp__l3_main_1,
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	&omap44xx_dss__l3_main_1,
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	&omap44xx_l3_main_2__l3_main_1,
	&omap44xx_l4_cfg__l3_main_1,
	&omap44xx_mpu__l3_main_1,
};

static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
	.name		= "l3_main_1",
	.class		= &omap44xx_l3_hwmod_class,
	.slaves		= omap44xx_l3_main_1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* l3_main_2 interface data */
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/* dma_system -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
	.master		= &omap44xx_dma_system_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* iva -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
	.master		= &omap44xx_iva_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_1 -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_2_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
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	&omap44xx_dma_system__l3_main_2,
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	&omap44xx_iva__l3_main_2,
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	&omap44xx_l3_main_1__l3_main_2,
	&omap44xx_l4_cfg__l3_main_2,
};

static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
	.name		= "l3_main_2",
	.class		= &omap44xx_l3_hwmod_class,
	.slaves		= omap44xx_l3_main_2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* l3_main_3 interface data */
/* l3_main_1 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_2 -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg -> l3_main_3 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l3_main_3_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l3_main_3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
	&omap44xx_l3_main_1__l3_main_3,
	&omap44xx_l3_main_2__l3_main_3,
	&omap44xx_l4_cfg__l3_main_3,
};

static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
	.name		= "l3_main_3",
	.class		= &omap44xx_l3_hwmod_class,
	.slaves		= omap44xx_l3_main_3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l3_main_3_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'l4' class
 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 */
static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
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	.name	= "l4",
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};

/* l4_abe interface data */
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/* dsp -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

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/* l3_main_1 -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_l4_abe_hwmod,
	.clk		= "ocp_abe_iclk",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_abe slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
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	&omap44xx_dsp__l4_abe,
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	&omap44xx_l3_main_1__l4_abe,
	&omap44xx_mpu__l4_abe,
};

static struct omap_hwmod omap44xx_l4_abe_hwmod = {
	.name		= "l4_abe",
	.class		= &omap44xx_l4_hwmod_class,
	.slaves		= omap44xx_l4_abe_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_abe_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* l4_cfg interface data */
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
	.master		= &omap44xx_l3_main_1_hwmod,
	.slave		= &omap44xx_l4_cfg_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_cfg slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
	&omap44xx_l3_main_1__l4_cfg,
};

static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
	.name		= "l4_cfg",
	.class		= &omap44xx_l4_hwmod_class,
	.slaves		= omap44xx_l4_cfg_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_cfg_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* l4_per interface data */
/* l3_main_2 -> l4_per */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_l4_per_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_per slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
	&omap44xx_l3_main_2__l4_per,
};

static struct omap_hwmod omap44xx_l4_per_hwmod = {
	.name		= "l4_per",
	.class		= &omap44xx_l4_hwmod_class,
	.slaves		= omap44xx_l4_per_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_per_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* l4_wkup interface data */
/* l4_cfg -> l4_wkup */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_l4_wkup_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* l4_wkup slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
	&omap44xx_l4_cfg__l4_wkup,
};

static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
	.name		= "l4_wkup",
	.class		= &omap44xx_l4_hwmod_class,
	.slaves		= omap44xx_l4_wkup_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_l4_wkup_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
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 * 'mpu_bus' class
 * instance(s): mpu_private
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 */
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static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
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	.name	= "mpu_bus",
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};
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/* mpu_private interface data */
/* mpu -> mpu_private */
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
	.master		= &omap44xx_mpu_hwmod,
	.slave		= &omap44xx_mpu_private_hwmod,
	.clk		= "l3_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* mpu_private slave ports */
static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
	&omap44xx_mpu__mpu_private,
};

static struct omap_hwmod omap44xx_mpu_private_hwmod = {
	.name		= "mpu_private",
	.class		= &omap44xx_mpu_bus_hwmod_class,
	.slaves		= omap44xx_mpu_private_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_mpu_private_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * Modules omap_hwmod structures
 *
 * The following IPs are excluded for the moment because:
 * - They do not need an explicit SW control using omap_hwmod API.
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
 *  aess
 *  bandgap
 *  c2c
 *  c2c_target_fw
 *  cm_core
 *  cm_core_aon
 *  counter_32k
 *  ctrl_module_core
 *  ctrl_module_pad_core
 *  ctrl_module_pad_wkup
 *  ctrl_module_wkup
 *  debugss
 *  dmic
 *  efuse_ctrl_cust
 *  efuse_ctrl_std
 *  elm
 *  emif1
 *  emif2
 *  fdif
 *  gpmc
 *  gpu
 *  hdq1w
 *  hsi
 *  ipu
 *  iss
 *  kbd
 *  mailbox
 *  mcasp
 *  mcbsp1
 *  mcbsp2
 *  mcbsp3
 *  mcbsp4
 *  mcpdm
 *  mmc1
 *  mmc2
 *  mmc3
 *  mmc4
 *  mmc5
 *  mpu_c0
 *  mpu_c1
 *  ocmc_ram
 *  ocp2scp_usb_phy
 *  ocp_wp_noc
 *  prcm
 *  prcm_mpu
 *  prm
 *  scrm
 *  sl2if
 *  slimbus1
 *  slimbus2
 *  usb_host_fs
 *  usb_host_hs
 *  usb_otg_hs
 *  usb_phy_cm
 *  usb_tll_hs
 *  usim
 */

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/*
 * 'dma' class
 * dma controller for data exchange between memory to memory (i.e. internal or
 * external memory) and gp peripherals to memory or memory to gp peripherals
 */

static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x002c,
	.syss_offs	= 0x0028,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
	.name	= "dma",
	.sysc	= &omap44xx_dma_sysc,
};

/* dma dev_attr */
static struct omap_dma_dev_attr dma_dev_attr = {
	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
	.lch_count	= 32,
};

/* dma_system */
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
	{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
	{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
	{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
	{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
};

/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
	&omap44xx_dma_system__l3_main_2,
};

static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
	{
		.pa_start	= 0x4a056000,
		.pa_end		= 0x4a0560ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_dma_system_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dma_system_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dma_system_addrs),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
	&omap44xx_l4_cfg__dma_system,
};

static struct omap_hwmod omap44xx_dma_system_hwmod = {
	.name		= "dma_system",
	.class		= &omap44xx_dma_hwmod_class,
	.mpu_irqs	= omap44xx_dma_system_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dma_system_irqs),
	.main_clk	= "l3_div_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
		},
	},
	.dev_attr	= &dma_dev_attr,
	.slaves		= omap44xx_dma_system_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dma_system_slaves),
	.masters	= omap44xx_dma_system_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dma_system_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dsp' class
 * dsp sub-system
 */

static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
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	.name	= "dsp",
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};

/* dsp */
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
	{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
};

static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
	{ .name = "mmu_cache", .rst_shift = 1 },
};

static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
	{ .name = "dsp", .rst_shift = 0 },
};

/* dsp -> iva */
static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
	.master		= &omap44xx_dsp_hwmod,
	.slave		= &omap44xx_iva_hwmod,
	.clk		= "dpll_iva_m5x2_ck",
};

/* dsp master ports */
static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
	&omap44xx_dsp__l3_main_1,
	&omap44xx_dsp__l4_abe,
	&omap44xx_dsp__iva,
};

/* l4_cfg -> dsp */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
	.master		= &omap44xx_l4_cfg_hwmod,
	.slave		= &omap44xx_dsp_hwmod,
	.clk		= "l4_div_ck",
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

/* dsp slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
	&omap44xx_l4_cfg__dsp,
};

/* Pseudo hwmod for reset control purpose only */
static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
	.name		= "dsp_c0",
	.class		= &omap44xx_dsp_hwmod_class,
	.flags		= HWMOD_INIT_NO_RESET,
	.rst_lines	= omap44xx_dsp_c0_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_c0_resets),
	.prcm = {
		.omap4 = {
			.rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
		},
	},
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

static struct omap_hwmod omap44xx_dsp_hwmod = {
	.name		= "dsp",
	.class		= &omap44xx_dsp_hwmod_class,
	.mpu_irqs	= omap44xx_dsp_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dsp_irqs),
	.rst_lines	= omap44xx_dsp_resets,
	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
	.main_clk	= "dsp_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
			.rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
		},
	},
	.slaves		= omap44xx_dsp_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dsp_slaves),
	.masters	= omap44xx_dsp_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dsp_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

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/*
 * 'dss' class
 * display sub-system
 */

static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
	.rev_offs	= 0x0000,
	.syss_offs	= 0x0014,
	.sysc_flags	= SYSS_HAS_RESET_STATUS,
};

static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
	.name	= "dss",
	.sysc	= &omap44xx_dss_sysc,
};

/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
	&omap44xx_dss__l3_main_1,
};

static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
	{
		.pa_start	= 0x58000000,
		.pa_end		= 0x5800007f,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
	{
		.pa_start	= 0x48040000,
		.pa_end		= 0x4804007f,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_addrs),
	.user		= OCP_USER_MPU,
};

/* dss slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
	&omap44xx_l3_main_2__dss,
	&omap44xx_l4_per__dss,
};

static struct omap_hwmod_opt_clk dss_opt_clks[] = {
	{ .role = "sys_clk", .clk = "dss_sys_clk" },
	{ .role = "tv_clk", .clk = "dss_tv_clk" },
	{ .role = "dss_clk", .clk = "dss_dss_clk" },
	{ .role = "video_clk", .clk = "dss_48mhz_clk" },
};

static struct omap_hwmod omap44xx_dss_hwmod = {
	.name		= "dss_core",
	.class		= &omap44xx_dss_hwmod_class,
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.opt_clks	= dss_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
	.slaves		= omap44xx_dss_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_slaves),
	.masters	= omap44xx_dss_masters,
	.masters_cnt	= ARRAY_SIZE(omap44xx_dss_masters),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'dispc' class
 * display controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
	.name	= "dispc",
	.sysc	= &omap44xx_dispc_sysc,
};

/* dss_dispc */
static struct omap_hwmod omap44xx_dss_dispc_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
	{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
};

static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
	{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
};

static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
	{
		.pa_start	= 0x58001000,
		.pa_end		= 0x58001fff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dispc_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_dispc_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
	{
		.pa_start	= 0x48041000,
		.pa_end		= 0x48041fff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dispc_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dispc_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_addrs),
	.user		= OCP_USER_MPU,
};

/* dss_dispc slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
	&omap44xx_l3_main_2__dss_dispc,
	&omap44xx_l4_per__dss_dispc,
};

static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
	.name		= "dss_dispc",
	.class		= &omap44xx_dispc_hwmod_class,
	.mpu_irqs	= omap44xx_dss_dispc_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_irqs),
	.sdma_reqs	= omap44xx_dss_dispc_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.slaves		= omap44xx_dss_dispc_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dispc_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'dsi' class
 * display serial interface controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
	.name	= "dsi",
	.sysc	= &omap44xx_dsi_sysc,
};

/* dss_dsi1 */
static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
	{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
};

static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
	{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
	{
		.pa_start	= 0x58004000,
		.pa_end		= 0x580041ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dsi1_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_dsi1_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
	{
		.pa_start	= 0x48044000,
		.pa_end		= 0x480441ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dsi1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dsi1_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
	.user		= OCP_USER_MPU,
};

/* dss_dsi1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
	&omap44xx_l3_main_2__dss_dsi1,
	&omap44xx_l4_per__dss_dsi1,
};

static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
	.name		= "dss_dsi1",
	.class		= &omap44xx_dsi_hwmod_class,
	.mpu_irqs	= omap44xx_dss_dsi1_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
	.sdma_reqs	= omap44xx_dss_dsi1_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.slaves		= omap44xx_dss_dsi1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/* dss_dsi2 */
static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
	{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
};

static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
	{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
	{
		.pa_start	= 0x58005000,
		.pa_end		= 0x580051ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_dsi2_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_dsi2_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
	{
		.pa_start	= 0x48045000,
		.pa_end		= 0x480451ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_dsi2_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_dsi2_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
	.user		= OCP_USER_MPU,
};

/* dss_dsi2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
	&omap44xx_l3_main_2__dss_dsi2,
	&omap44xx_l4_per__dss_dsi2,
};

static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
	.name		= "dss_dsi2",
	.class		= &omap44xx_dsi_hwmod_class,
	.mpu_irqs	= omap44xx_dss_dsi2_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
	.sdma_reqs	= omap44xx_dss_dsi2_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.slaves		= omap44xx_dss_dsi2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'hdmi' class
 * hdmi controller
 */

static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
	.name	= "hdmi",
	.sysc	= &omap44xx_hdmi_sysc,
};

/* dss_hdmi */
static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
	{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
};

static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
	{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
};

static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
	{
		.pa_start	= 0x58006000,
		.pa_end		= 0x58006fff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_hdmi_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_hdmi_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
	{
		.pa_start	= 0x48046000,
		.pa_end		= 0x48046fff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_hdmi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_hdmi_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
	.user		= OCP_USER_MPU,
};

/* dss_hdmi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
	&omap44xx_l3_main_2__dss_hdmi,
	&omap44xx_l4_per__dss_hdmi,
};

static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
	.name		= "dss_hdmi",
	.class		= &omap44xx_hdmi_hwmod_class,
	.mpu_irqs	= omap44xx_dss_hdmi_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
	.sdma_reqs	= omap44xx_dss_hdmi_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.slaves		= omap44xx_dss_hdmi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'rfbi' class
 * remote frame buffer interface
 */

static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
	.name	= "rfbi",
	.sysc	= &omap44xx_rfbi_sysc,
};

/* dss_rfbi */
static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
	{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
};

static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
	{
		.pa_start	= 0x58002000,
		.pa_end		= 0x580020ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_rfbi_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_rfbi_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
	{
		.pa_start	= 0x48042000,
		.pa_end		= 0x480420ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_rfbi_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_rfbi_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
	.user		= OCP_USER_MPU,
};

/* dss_rfbi slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
	&omap44xx_l3_main_2__dss_rfbi,
	&omap44xx_l4_per__dss_rfbi,
};

static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
	.name		= "dss_rfbi",
	.class		= &omap44xx_rfbi_hwmod_class,
	.sdma_reqs	= omap44xx_dss_rfbi_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.slaves		= omap44xx_dss_rfbi_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

/*
 * 'venc' class
 * video encoder
 */

static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
	.name	= "venc",
};

/* dss_venc */
static struct omap_hwmod omap44xx_dss_venc_hwmod;
static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
	{
		.pa_start	= 0x58003000,
		.pa_end		= 0x580030ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l3_main_2 -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
	.master		= &omap44xx_l3_main_2_hwmod,
	.slave		= &omap44xx_dss_venc_hwmod,
	.clk		= "l3_div_ck",
	.addr		= omap44xx_dss_venc_dma_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
	.user		= OCP_USER_SDMA,
};

static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
	{
		.pa_start	= 0x48043000,
		.pa_end		= 0x480430ff,
		.flags		= ADDR_TYPE_RT
	},
};

/* l4_per -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_dss_venc_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_dss_venc_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_dss_venc_addrs),
	.user		= OCP_USER_MPU,
};

/* dss_venc slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
	&omap44xx_l3_main_2__dss_venc,
	&omap44xx_l4_per__dss_venc,
};

static struct omap_hwmod omap44xx_dss_venc_hwmod = {
	.name		= "dss_venc",
	.class		= &omap44xx_venc_hwmod_class,
	.main_clk	= "dss_fck",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
		},
	},
	.slaves		= omap44xx_dss_venc_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_dss_venc_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1320
1321
1322
1323
1324
1325
1326
/*
 * 'gpio' class
 * general purpose io module
 */

static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
	.rev_offs	= 0x0000,
1327
	.sysc_offs	= 0x0010,
1328
	.syss_offs	= 0x0114,
1329
1330
1331
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
			   SYSS_HAS_RESET_STATUS),
1332
1333
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
1334
1335
1336
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

1337
static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1338
1339
1340
	.name	= "gpio",
	.sysc	= &omap44xx_gpio_sysc,
	.rev	= 2,
1341
1342
};

1343
1344
/* gpio dev_attr */
static struct omap_gpio_dev_attr gpio_dev_attr = {
1345
1346
	.bank_width	= 32,
	.dbck_flag	= true,
1347
1348
};

1349
1350
1351
1352
/* gpio1 */
static struct omap_hwmod omap44xx_gpio1_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
	{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
1353
1354
};

1355
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1356
	{
1357
1358
		.pa_start	= 0x4a310000,
		.pa_end		= 0x4a3101ff,
1359
1360
1361
1362
		.flags		= ADDR_TYPE_RT
	},
};

1363
1364
1365
1366
/* l4_wkup -> gpio1 */
static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
	.master		= &omap44xx_l4_wkup_hwmod,
	.slave		= &omap44xx_gpio1_hwmod,
1367
	.clk		= "l4_wkup_clk_mux_ck",
1368
1369
	.addr		= omap44xx_gpio1_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_gpio1_addrs),
1370
1371
1372
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1373
1374
1375
/* gpio1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
	&omap44xx_l4_wkup__gpio1,
1376
1377
};

1378
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1379
	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1380
1381
1382
1383
1384
1385
1386
1387
};

static struct omap_hwmod omap44xx_gpio1_hwmod = {
	.name		= "gpio1",
	.class		= &omap44xx_gpio_hwmod_class,
	.mpu_irqs	= omap44xx_gpio1_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio1_irqs),
	.main_clk	= "gpio1_ick",
1388
1389
	.prcm = {
		.omap4 = {
1390
			.clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1391
1392
		},
	},
1393
1394
1395
1396
1397
	.opt_clks	= gpio1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio1_slaves),
1398
1399
1400
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1401
1402
1403
1404
/* gpio2 */
static struct omap_hwmod omap44xx_gpio2_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
	{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
1405
1406
};

1407
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1408
	{
1409
1410
		.pa_start	= 0x48055000,
		.pa_end		= 0x480551ff,
1411
1412
1413
1414
		.flags		= ADDR_TYPE_RT
	},
};

1415
1416
/* l4_per -> gpio2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1417
	.master		= &omap44xx_l4_per_hwmod,
1418
	.slave		= &omap44xx_gpio2_hwmod,
1419
	.clk		= "l4_div_ck",
1420
1421
	.addr		= omap44xx_gpio2_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_gpio2_addrs),
1422
1423
1424
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1425
1426
1427
/* gpio2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
	&omap44xx_l4_per__gpio2,
1428
1429
};

1430
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1431
	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1432
1433
1434
1435
1436
};

static struct omap_hwmod omap44xx_gpio2_hwmod = {
	.name		= "gpio2",
	.class		= &omap44xx_gpio_hwmod_class,
1437
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1438
1439
1440
	.mpu_irqs	= omap44xx_gpio2_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio2_irqs),
	.main_clk	= "gpio2_ick",
1441
1442
	.prcm = {
		.omap4 = {
1443
			.clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1444
1445
		},
	},
1446
1447
1448
1449
1450
	.opt_clks	= gpio2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio2_slaves),
1451
1452
1453
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1454
1455
1456
1457
/* gpio3 */
static struct omap_hwmod omap44xx_gpio3_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
	{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
1458
1459
};

1460
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1461
	{
1462
1463
		.pa_start	= 0x48057000,
		.pa_end		= 0x480571ff,
1464
1465
1466
1467
		.flags		= ADDR_TYPE_RT
	},
};

1468
1469
/* l4_per -> gpio3 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1470
	.master		= &omap44xx_l4_per_hwmod,
1471
	.slave		= &omap44xx_gpio3_hwmod,
1472
	.clk		= "l4_div_ck",
1473
1474
	.addr		= omap44xx_gpio3_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_gpio3_addrs),
1475
1476
1477
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1478
1479
1480
/* gpio3 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
	&omap44xx_l4_per__gpio3,
1481
1482
};

1483
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1484
	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1485
1486
1487
1488
1489
};

static struct omap_hwmod omap44xx_gpio3_hwmod = {
	.name		= "gpio3",
	.class		= &omap44xx_gpio_hwmod_class,
1490
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1491
1492
1493
	.mpu_irqs	= omap44xx_gpio3_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio3_irqs),
	.main_clk	= "gpio3_ick",
1494
1495
	.prcm = {
		.omap4 = {
1496
			.clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1497
1498
		},
	},
1499
1500
1501
1502
1503
	.opt_clks	= gpio3_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio3_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio3_slaves),
1504
1505
1506
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1507
1508
1509
1510
/* gpio4 */
static struct omap_hwmod omap44xx_gpio4_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
	{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
1511
1512
};

1513
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1514
	{
1515
1516
		.pa_start	= 0x48059000,
		.pa_end		= 0x480591ff,
1517
1518
1519
1520
		.flags		= ADDR_TYPE_RT
	},
};

1521
1522
/* l4_per -> gpio4 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1523
	.master		= &omap44xx_l4_per_hwmod,
1524
	.slave		= &omap44xx_gpio4_hwmod,
1525
	.clk		= "l4_div_ck",
1526
1527
	.addr		= omap44xx_gpio4_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_gpio4_addrs),
1528
1529
1530
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1531
1532
1533
/* gpio4 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
	&omap44xx_l4_per__gpio4,
1534
1535
};

1536
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1537
	{ .role = "dbclk", .clk = "gpio4_dbclk" },
1538
1539
1540
1541
1542
};

static struct omap_hwmod omap44xx_gpio4_hwmod = {
	.name		= "gpio4",
	.class		= &omap44xx_gpio_hwmod_class,
1543
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1544
1545
1546
	.mpu_irqs	= omap44xx_gpio4_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio4_irqs),
	.main_clk	= "gpio4_ick",
1547
1548
	.prcm = {
		.omap4 = {
1549
			.clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1550
1551
		},
	},
1552
1553
1554
1555
1556
	.opt_clks	= gpio4_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio4_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio4_slaves),
1557
1558
1559
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1560
1561
1562
1563
/* gpio5 */
static struct omap_hwmod omap44xx_gpio5_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
	{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
1564
1565
};

1566
1567
1568
1569
1570
1571
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
	{
		.pa_start	= 0x4805b000,
		.pa_end		= 0x4805b1ff,
		.flags		= ADDR_TYPE_RT
	},
1572
1573
};

1574
1575
1576
1577
/* l4_per -> gpio5 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_gpio5_hwmod,
1578
	.clk		= "l4_div_ck",
1579
1580
1581
	.addr		= omap44xx_gpio5_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_gpio5_addrs),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1582
1583
};

1584
1585
1586
/* gpio5 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
	&omap44xx_l4_per__gpio5,
1587
1588
};

1589
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1590
	{ .role = "dbclk", .clk = "gpio5_dbclk" },
1591
1592
};

1593
1594
1595
static struct omap_hwmod omap44xx_gpio5_hwmod = {
	.name		= "gpio5",
	.class		= &omap44xx_gpio_hwmod_class,
1596
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1597
1598
1599
	.mpu_irqs	= omap44xx_gpio5_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio5_irqs),
	.main_clk	= "gpio5_ick",
1600
1601
	.prcm = {
		.omap4 = {
1602
			.clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1603
1604
		},
	},
1605
1606
1607
1608
1609
	.opt_clks	= gpio5_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio5_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio5_slaves),
1610
1611
1612
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1613
1614
1615
1616
/* gpio6 */
static struct omap_hwmod omap44xx_gpio6_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
	{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
1617
1618
};

1619
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1620
	{
1621
1622
		.pa_start	= 0x4805d000,
		.pa_end		= 0x4805d1ff,
1623
1624
1625
1626
		.flags		= ADDR_TYPE_RT
	},
};

1627
1628
1629
1630
/* l4_per -> gpio6 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_gpio6_hwmod,
1631
	.clk		= "l4_div_ck",
1632
1633
1634
	.addr		= omap44xx_gpio6_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_gpio6_addrs),
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1635
1636
};

1637
1638
1639
/* gpio6 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
	&omap44xx_l4_per__gpio6,
1640
1641
};

1642
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1643
	{ .role = "dbclk", .clk = "gpio6_dbclk" },
1644
1645
};

1646
1647
1648
static struct omap_hwmod omap44xx_gpio6_hwmod = {
	.name		= "gpio6",
	.class		= &omap44xx_gpio_hwmod_class,
1649
	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1650
1651
1652
1653
1654
1655
1656
	.mpu_irqs	= omap44xx_gpio6_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_gpio6_irqs),
	.main_clk	= "gpio6_ick",
	.prcm = {
		.omap4 = {
			.clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
		},
1657
	},
1658
1659
1660
1661
1662
1663
	.opt_clks	= gpio6_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
	.dev_attr	= &gpio_dev_attr,
	.slaves		= omap44xx_gpio6_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_gpio6_slaves),
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1664
1665
};

1666
1667
1668
1669
/*
 * 'i2c' class
 * multimaster high-speed i2c controller
 */
1670

1671
1672
1673
1674
1675
static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0090,
	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1676
			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1677
1678
	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
			   SIDLE_SMART_WKUP),
1679
	.sysc_fields	= &omap_hwmod_sysc_type1,
1680
1681
};

1682
static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1683
1684
	.name	= "i2c",
	.sysc	= &omap44xx_i2c_sysc,
1685
1686
};

1687
1688
1689
1690
/* i2c1 */
static struct omap_hwmod omap44xx_i2c1_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
1691
1692
};

1693
1694
1695
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1696
1697
};

1698
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1699
	{
1700
1701
		.pa_start	= 0x48070000,
		.pa_end		= 0x480700ff,
1702
1703
1704
1705
		.flags		= ADDR_TYPE_RT
	},
};

1706
1707
1708
1709
1710
1711
1712
/* l4_per -> i2c1 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
	.master		= &omap44xx_l4_per_hwmod,
	.slave		= &omap44xx_i2c1_hwmod,
	.clk		= "l4_div_ck",
	.addr		= omap44xx_i2c1_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c1_addrs),
1713
1714
1715
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1716
1717
1718
/* i2c1 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
	&omap44xx_l4_per__i2c1,
1719
1720
};

1721
1722
1723
1724
1725
1726
1727
1728
1729
static struct omap_hwmod omap44xx_i2c1_hwmod = {
	.name		= "i2c1",
	.class		= &omap44xx_i2c_hwmod_class,
	.flags		= HWMOD_INIT_NO_RESET,
	.mpu_irqs	= omap44xx_i2c1_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_irqs),
	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
	.main_clk	= "i2c1_fck",
1730
1731
	.prcm = {
		.omap4 = {
1732
			.clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1733
1734
		},
	},
1735
1736
	.slaves		= omap44xx_i2c1_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),
1737
1738
1739
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1740
1741
1742
1743
/* i2c2 */
static struct omap_hwmod omap44xx_i2c2_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
1744
1745
};

1746
1747
1748
1749
1750
1751
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
};

static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1752
	{
1753
1754
		.pa_start	= 0x48072000,
		.pa_end		= 0x480720ff,
1755
1756
1757
1758
		.flags		= ADDR_TYPE_RT
	},
};

1759
1760
/* l4_per -> i2c2 */
static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1761
	.master		= &omap44xx_l4_per_hwmod,
1762
	.slave		= &omap44xx_i2c2_hwmod,
1763
	.clk		= "l4_div_ck",
1764
1765
	.addr		= omap44xx_i2c2_addrs,
	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c2_addrs),
1766
1767
1768
	.user		= OCP_USER_MPU | OCP_USER_SDMA,
};

1769
1770
1771
/* i2c2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
	&omap44xx_l4_per__i2c2,
1772
1773
};

1774
1775
1776
1777
1778
1779
1780
1781
1782
static struct omap_hwmod omap44xx_i2c2_hwmod = {
	.name		= "i2c2",
	.class		= &omap44xx_i2c_hwmod_class,
	.flags		= HWMOD_INIT_NO_RESET,
	.mpu_irqs	= omap44xx_i2c2_irqs,
	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_irqs),
	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,
	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
	.main_clk	= "i2c2_fck",
1783
1784
	.prcm = {
		.omap4 = {
1785
			.clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1786
1787
		},
	},
1788
1789
	.slaves		= omap44xx_i2c2_slaves,
	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),
1790
1791
1792
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};

1793
1794
1795
1796
/* i2c3 */
static struct omap_hwmod omap44xx_i2c3_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
1797
1798
};

1799
1800
1801
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1802
1803
};

1804
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1805
	{
1806
1807
		.pa_start	= 0x48060000,
		.pa_end		= 0x480600ff,