clock.c 23.5 KB
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/*
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 * linux/arch/arm/mach-at91/clock.c
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 *
 * Copyright (C) 2005 David Brownell
 * Copyright (C) 2005 Ivan Kokshaysky
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/clk/at91_pmc.h>
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#include <mach/hardware.h>
#include <mach/cpu.h>
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#include <asm/proc-fns.h>

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#include "clock.h"
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#include "generic.h"
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void __iomem *at91_pmc_base;
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EXPORT_SYMBOL_GPL(at91_pmc_base);
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/*
 * There's a lot more which can be done with clocks, including cpufreq
 * integration, slow clock mode support (for system suspend), letting
 * PLLB be used at other rates (on boards that don't need USB), etc.
 */

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#define clk_is_primary(x)	((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_programmable(x)	((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_peripheral(x)	((x)->type & CLK_TYPE_PERIPHERAL)
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#define clk_is_sys(x)		((x)->type & CLK_TYPE_SYSTEM)
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/*
 * Chips have some kind of clocks : group them by functionality
 */
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#define cpu_has_utmi()		(  cpu_is_at91sam9rl() \
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				|| cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
				|| cpu_is_sama5d3())

#define cpu_has_1056M_plla()	(cpu_is_sama5d3())
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#define cpu_has_800M_plla()	(  cpu_is_at91sam9g20() \
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				|| cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
				|| cpu_is_at91sam9n12())
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#define cpu_has_300M_plla()	(cpu_is_at91sam9g10())
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#define cpu_has_240M_plla()	(cpu_is_at91sam9261() \
				|| cpu_is_at91sam9263() \
				|| cpu_is_at91sam9rl())

#define cpu_has_210M_plla()	(cpu_is_at91sam9260())

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#define cpu_has_pllb()		(!(cpu_is_at91sam9rl() \
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				|| cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
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				|| cpu_is_sama5d3()))
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#define cpu_has_upll()		(cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
				|| cpu_is_sama5d3())
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/* USB host HS & FS */
#define cpu_has_uhp()		(!cpu_is_at91sam9rl())

/* USB device FS only */
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#define cpu_has_udpfs()		(!(cpu_is_at91sam9rl() \
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				|| cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
				|| cpu_is_sama5d3()))
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#define cpu_has_plladiv2()	(cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
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				|| cpu_is_at91sam9n12() \
				|| cpu_is_sama5d3())
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#define cpu_has_mdiv3()		(cpu_is_at91sam9g45() \
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				|| cpu_is_at91sam9x5() \
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				|| cpu_is_at91sam9n12() \
				|| cpu_is_sama5d3())
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#define cpu_has_alt_prescaler()	(cpu_is_at91sam9x5() \
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				|| cpu_is_at91sam9n12() \
				|| cpu_is_sama5d3())
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static LIST_HEAD(clocks);
static DEFINE_SPINLOCK(clk_lock);
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static u32 at91_pllb_usb_init;
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/*
 * Four primary clock sources:  two crystal oscillators (32K, main), and
 * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
 * 48 MHz (unless no USB function clocks are needed).  The main clock and
 * both PLLs are turned off to run in "slow clock mode" (system suspend).
 */
static struct clk clk32k = {
	.name		= "clk32k",
	.rate_hz	= AT91_SLOW_CLOCK,
	.users		= 1,		/* always on */
	.id		= 0,
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	.type		= CLK_TYPE_PRIMARY,
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};
static struct clk main_clk = {
	.name		= "main",
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	.pmc_mask	= AT91_PMC_MOSCS,	/* in PMC_SR */
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	.id		= 1,
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	.type		= CLK_TYPE_PRIMARY,
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};
static struct clk plla = {
	.name		= "plla",
	.parent		= &main_clk,
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	.pmc_mask	= AT91_PMC_LOCKA,	/* in PMC_SR */
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	.id		= 2,
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	.type		= CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
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};

static void pllb_mode(struct clk *clk, int is_on)
{
	u32	value;

	if (is_on) {
		is_on = AT91_PMC_LOCKB;
		value = at91_pllb_usb_init;
	} else
		value = 0;

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	// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
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	at91_pmc_write(AT91_CKGR_PLLBR, value);
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	do {
		cpu_relax();
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	} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
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}

static struct clk pllb = {
	.name		= "pllb",
	.parent		= &main_clk,
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	.pmc_mask	= AT91_PMC_LOCKB,	/* in PMC_SR */
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	.mode		= pllb_mode,
	.id		= 3,
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	.type		= CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
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};

static void pmc_sys_mode(struct clk *clk, int is_on)
{
	if (is_on)
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		at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
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	else
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		at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
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}

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static void pmc_uckr_mode(struct clk *clk, int is_on)
{
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	unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
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	if (is_on) {
		is_on = AT91_PMC_LOCKU;
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		at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
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	} else
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		at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
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	do {
		cpu_relax();
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	} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
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}

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/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
	.name		= "udpck",
	.parent		= &pllb,
	.mode		= pmc_sys_mode,
};
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struct clk utmi_clk = {
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	.name		= "utmi_clk",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_UPLLEN,	/* in CKGR_UCKR */
	.mode		= pmc_uckr_mode,
	.type		= CLK_TYPE_PLL,
};
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static struct clk uhpck = {
	.name		= "uhpck",
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	/*.parent		= ... we choose parent at runtime */
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	.mode		= pmc_sys_mode,
};


/*
 * The master clock is divided from the CPU clock (by 1-4).  It's used for
 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 */
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struct clk mck = {
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	.name		= "mck",
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	.pmc_mask	= AT91_PMC_MCKRDY,	/* in PMC_SR */
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};

static void pmc_periph_mode(struct clk *clk, int is_on)
{
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	u32 regval = 0;

	/*
	 * With sama5d3 devices, we are managing clock division so we have to
	 * use the Peripheral Control Register introduced from at91sam9x5
	 * devices.
	 */
	if (cpu_is_sama5d3()) {
		regval |= AT91_PMC_PCR_CMD; /* write command */
		regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
		regval |= AT91_PMC_PCR_DIV(clk->div);
		if (is_on)
			regval |= AT91_PMC_PCR_EN; /* enable clock */
		at91_pmc_write(AT91_PMC_PCR, regval);
	} else {
		if (is_on)
			at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
		else
			at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
	}
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}

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static struct clk __init *at91_css_to_clk(unsigned long css)
{
	switch (css) {
		case AT91_PMC_CSS_SLOW:
			return &clk32k;
		case AT91_PMC_CSS_MAIN:
			return &main_clk;
		case AT91_PMC_CSS_PLLA:
			return &plla;
		case AT91_PMC_CSS_PLLB:
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			if (cpu_has_upll())
				/* CSS_PLLB == CSS_UPLL */
				return &utmi_clk;
			else if (cpu_has_pllb())
				return &pllb;
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			break;
		/* alternate PMC: can use master clock */
		case AT91_PMC_CSS_MASTER:
			return &mck;
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	}
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	return NULL;
}
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static int pmc_prescaler_divider(u32 reg)
{
	if (cpu_has_alt_prescaler()) {
		return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
	} else {
		return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
	}
}

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static void __clk_enable(struct clk *clk)
{
	if (clk->parent)
		__clk_enable(clk->parent);
	if (clk->users++ == 0 && clk->mode)
		clk->mode(clk, 1);
}

int clk_enable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	BUG_ON(clk->users == 0);
	if (--clk->users == 0 && clk->mode)
		clk->mode(clk, 0);
	if (clk->parent)
		__clk_disable(clk->parent);
}

void clk_disable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	unsigned long	flags;
	unsigned long	rate;

	spin_lock_irqsave(&clk_lock, flags);
	for (;;) {
		rate = clk->rate_hz;
		if (rate || !clk->parent)
			break;
		clk = clk->parent;
	}
	spin_unlock_irqrestore(&clk_lock, flags);
	return rate;
}
EXPORT_SYMBOL(clk_get_rate);

/*------------------------------------------------------------------------*/

/*
 * For now, only the programmable clocks support reparenting (MCK could
 * do this too, with care) or rate changing (the PLLs could do this too,
 * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 * a better rate match; we don't.
 */

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;
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	unsigned long	prev = ULONG_MAX;
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	if (!clk_is_programmable(clk))
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		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
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		if (actual > rate)
			prev = actual;

		if (actual && actual <= rate) {
			if ((prev - rate) < (rate - actual)) {
				actual = prev;
				prescale--;
			}
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			break;
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		}
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		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
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	unsigned long	prescale_offset, css_mask;
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	unsigned long	actual;

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	if (!clk_is_programmable(clk))
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		return -EINVAL;
	if (clk->users)
		return -EBUSY;
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	if (cpu_has_alt_prescaler()) {
		prescale_offset = PMC_ALT_PRES_OFFSET;
		css_mask = AT91_PMC_ALT_PCKR_CSS;
	} else {
		prescale_offset = PMC_PRES_OFFSET;
		css_mask = AT91_PMC_CSS;
	}

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	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate) {
			u32	pckr;

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			pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
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			pckr &= css_mask;	/* keep clock selection */
			pckr |= prescale << prescale_offset;
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			at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
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			clk->rate_hz = actual;
			break;
		}
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	unsigned long	flags;

	if (clk->users)
		return -EBUSY;
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	if (!clk_is_primary(parent) || !clk_is_programmable(clk))
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		return -EINVAL;
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	if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
		return -EINVAL;

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	spin_lock_irqsave(&clk_lock, flags);

	clk->rate_hz = parent->rate_hz;
	clk->parent = parent;
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	at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
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	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

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/* establish PCK0..PCKN parentage and rate */
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static void __init init_programmable_clock(struct clk *clk)
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{
	struct clk	*parent;
	u32		pckr;
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	unsigned int	css_mask;

	if (cpu_has_alt_prescaler())
		css_mask = AT91_PMC_ALT_PCKR_CSS;
	else
		css_mask = AT91_PMC_CSS;
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	pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
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	parent = at91_css_to_clk(pckr & css_mask);
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	clk->parent = parent;
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	clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
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}

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/*------------------------------------------------------------------------*/

#ifdef CONFIG_DEBUG_FS

static int at91_clk_show(struct seq_file *s, void *unused)
{
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	u32		scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
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	struct clk	*clk;
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	scsr = at91_pmc_read(AT91_PMC_SCSR);
	pcsr = at91_pmc_read(AT91_PMC_PCSR);
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	if (cpu_is_sama5d3())
		pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
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	sr = at91_pmc_read(AT91_PMC_SR);
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	seq_printf(s, "SCSR = %8x\n", scsr);
	seq_printf(s, "PCSR = %8x\n", pcsr);
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	if (cpu_is_sama5d3())
		seq_printf(s, "PCSR1 = %8x\n", pcsr1);
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	seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
	seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
	seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
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	if (cpu_has_pllb())
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		seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
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	if (cpu_has_utmi()) {
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		uckr = at91_pmc_read(AT91_CKGR_UCKR);
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		seq_printf(s, "UCKR = %8x\n", uckr);
	}
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	seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
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	if (cpu_has_upll() || cpu_is_at91sam9n12())
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		seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
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	seq_printf(s, "SR   = %8x\n", sr);
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	seq_printf(s, "\n");

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	list_for_each_entry(clk, &clocks, node) {
		char	*state;
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		if (clk->mode == pmc_sys_mode) {
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			state = (scsr & clk->pmc_mask) ? "on" : "off";
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		} else if (clk->mode == pmc_periph_mode) {
			if (cpu_is_sama5d3()) {
				u32 pmc_mask = 1 << (clk->pid % 32);

				if (clk->pid > 31)
					state = (pcsr1 & pmc_mask) ? "on" : "off";
				else
					state = (pcsr & pmc_mask) ? "on" : "off";
			} else {
				state = (pcsr & clk->pmc_mask) ? "on" : "off";
			}
		} else if (clk->mode == pmc_uckr_mode) {
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			state = (uckr & clk->pmc_mask) ? "on" : "off";
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		} else if (clk->pmc_mask) {
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			state = (sr & clk->pmc_mask) ? "on" : "off";
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		} else if (clk == &clk32k || clk == &main_clk) {
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			state = "on";
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		} else {
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			state = "";
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		}
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		seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
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			clk->name, clk->users, state, clk_get_rate(clk),
			clk->parent ? clk->parent->name : "");
	}
	return 0;
}

static int at91_clk_open(struct inode *inode, struct file *file)
{
	return single_open(file, at91_clk_show, NULL);
}

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static const struct file_operations at91_clk_operations = {
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	.open		= at91_clk_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init at91_clk_debugfs_init(void)
{
	/* /sys/kernel/debug/at91_clk */
	(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);

	return 0;
}
postcore_initcall(at91_clk_debugfs_init);

#endif

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/*------------------------------------------------------------------------*/

/* Register a new clock */
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static void __init at91_clk_add(struct clk *clk)
{
	list_add_tail(&clk->node, &clocks);

	clk->cl.con_id = clk->name;
	clk->cl.clk = clk;
	clkdev_add(&clk->cl);
}

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int __init clk_register(struct clk *clk)
{
	if (clk_is_peripheral(clk)) {
565
566
		if (!clk->parent)
			clk->parent = &mck;
567
568
569
		if (cpu_is_sama5d3())
			clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
						    1 << clk->div);
570
571
		clk->mode = pmc_periph_mode;
	}
572
573
574
575
	else if (clk_is_sys(clk)) {
		clk->parent = &mck;
		clk->mode = pmc_sys_mode;
	}
576
577
578
579
580
	else if (clk_is_programmable(clk)) {
		clk->mode = pmc_sys_mode;
		init_programmable_clock(clk);
	}

581
582
	at91_clk_add(clk);

583
584
585
	return 0;
}

586
587
588
589
590
591
592
/*------------------------------------------------------------------------*/

static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
	unsigned mul, div;

	div = reg & 0xff;
593
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595
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597
	if (cpu_is_sama5d3())
		mul = AT91_PMC3_MUL_GET(reg);
	else
		mul = AT91_PMC_MUL_GET(reg);

598
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601
602
	if (div && mul) {
		freq /= div;
		freq *= mul + 1;
	} else
		freq = 0;
603

604
605
606
	return freq;
}

607
608
609
610
static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
	if (pll == &pllb && (reg & AT91_PMC_USB96M))
		return freq / 2;
611
612
	else if (pll == &utmi_clk || cpu_is_at91sam9n12())
		return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
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616
	else
		return freq;
}

617
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628
629
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631
632
static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;

	/* PLL output max 240 MHz (or 180 MHz per errata) */
	if (out_freq > 240000000)
		goto fail;

	for (i = 1; i < 256; i++) {
		int diff1;
		unsigned input, mul1;

		/*
		 * PLL input between 1MHz and 32MHz per spec, but lower
		 * frequences seem necessary in some cases so allow 100K.
633
		 * Warning: some newer products need 2MHz min.
634
635
		 */
		input = main_freq / i;
636
637
		if (cpu_is_at91sam9g20() && input < 2000000)
			continue;
638
639
640
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642
643
		if (input < 100000)
			continue;
		if (input > 32000000)
			continue;

		mul1 = out_freq / input;
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645
		if (cpu_is_at91sam9g20() && mul > 63)
			continue;
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668
		if (mul1 > 2048)
			continue;
		if (mul1 < 2)
			goto fail;

		diff1 = out_freq - input * mul1;
		if (diff1 < 0)
			diff1 = -diff1;
		if (diff > diff1) {
			diff = diff1;
			div = i;
			mul = mul1;
			if (diff == 0)
				break;
		}
	}
	if (i == 256 && diff > (out_freq >> 5))
		goto fail;
	return ret | ((mul - 1) << 16) | div;
fail:
	return 0;
}

669
static struct clk *const standard_pmc_clocks[] __initconst = {
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678
	/* four primary clocks */
	&clk32k,
	&main_clk,
	&plla,

	/* MCK */
	&mck
};

679
680
681
/* PLLB generated USB full speed clock init */
static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
{
682
683
	unsigned int reg;

684
685
686
687
688
689
690
691
	/*
	 * USB clock init:  choose 48 MHz PLLB value,
	 * disable 48MHz clock during usb peripheral suspend.
	 *
	 * REVISIT:  assumes MCK doesn't derive from PLLB!
	 */
	uhpck.parent = &pllb;

692
	reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
693
694
	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
	if (cpu_is_at91rm9200()) {
695
		reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
696
697
		uhpck.pmc_mask = AT91RM9200_PMC_UHP;
		udpck.pmc_mask = AT91RM9200_PMC_UDP;
698
		at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
699
700
	} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
		   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
701
		   cpu_is_at91sam9g10()) {
702
703
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708
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710
711
712
713
		reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
		uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
		udpck.pmc_mask = AT91SAM926x_PMC_UDP;
	} else if (cpu_is_at91sam9n12()) {
		/* Divider for USB clock is in USB clock register for 9n12 */
		reg = AT91_PMC_USBS_PLLB;

		/* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
		reg |= AT91_PMC_OHCIUSBDIV_2;
		at91_pmc_write(AT91_PMC_USB, reg);

		/* Still setup masks */
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716
		uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
		udpck.pmc_mask = AT91SAM926x_PMC_UDP;
	}
717
	at91_pmc_write(AT91_CKGR_PLLBR, 0);
718

719
720
	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
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732
733
}

/* UPLL generated USB full speed clock init */
static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
{
	/*
	 * USB clock init: choose 480 MHz from UPLL,
	 */
	unsigned int usbr = AT91_PMC_USBS_UPLL;

	/* Setup divider by 10 to reach 48 MHz */
	usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;

734
	at91_pmc_write(AT91_PMC_USB, usbr);
735
736
737
738

	/* Now set uhpck values */
	uhpck.parent = &utmi_clk;
	uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
739
	uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
740
741
}

742
static int __init at91_pmc_init(unsigned long main_clock)
743
744
{
	unsigned tmp, freq, mckr;
745
	int i;
746
	int pll_overclock = false;
747
748
749
750
751
752
753
754
755

	/*
	 * When the bootloader initialized the main oscillator correctly,
	 * there's no problem using the cycle counter.  But if it didn't,
	 * or when using oscillator bypass mode, we must be told the speed
	 * of the main clock.
	 */
	if (!main_clock) {
		do {
756
			tmp = at91_pmc_read(AT91_CKGR_MCFR);
757
758
		} while (!(tmp & AT91_PMC_MAINRDY));
		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
759
760
761
762
	}
	main_clk.rate_hz = main_clock;

	/* report if PLLA is more than mildly overclocked */
763
	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
764
765
	if (cpu_has_1056M_plla()) {
		if (plla.rate_hz > 1056000000)
766
767
768
769
			pll_overclock = true;
	} else if (cpu_has_800M_plla()) {
		if (plla.rate_hz > 800000000)
			pll_overclock = true;
770
771
772
	} else if (cpu_has_300M_plla()) {
		if (plla.rate_hz > 300000000)
			pll_overclock = true;
773
774
775
776
777
778
	} else if (cpu_has_240M_plla()) {
		if (plla.rate_hz > 240000000)
			pll_overclock = true;
	} else if (cpu_has_210M_plla()) {
		if (plla.rate_hz > 210000000)
			pll_overclock = true;
779
780
781
782
783
	} else {
		if (plla.rate_hz > 209000000)
			pll_overclock = true;
	}
	if (pll_overclock)
784
785
		pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);

786
	if (cpu_has_plladiv2()) {
787
		mckr = at91_pmc_read(AT91_PMC_MCKR);
788
789
		plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));	/* plla divisor by 2 */
	}
790

791
	if (!cpu_has_pllb() && cpu_has_upll()) {
792
793
794
795
		/* setup UTMI clock as the fourth primary clock
		 * (instead of pllb) */
		utmi_clk.type |= CLK_TYPE_PRIMARY;
		utmi_clk.id = 3;
796
	}
797

798

799
800
801
	/*
	 * USB HS clock init
	 */
802
	if (cpu_has_utmi()) {
803
804
805
806
807
		/*
		 * multiplier is hard-wired to 40
		 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
		 */
		utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
808
809
810
811

		/* UTMI bias and PLL are managed at the same time */
		if (cpu_has_upll())
			utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
812
	}
813
814
815
816
817
818
819
820
821

	/*
	 * USB FS clock init
	 */
	if (cpu_has_pllb())
		at91_pllb_usbfs_clock_init(main_clock);
	if (cpu_has_upll())
		/* assumes that we choose UPLL for USB and not PLLA */
		at91_upll_usbfs_clock_init(main_clock);
822

823
824
825
826
	/*
	 * MCK and CPU derive from one of those primary clocks.
	 * For now, assume this parentage won't change.
	 */
827
	mckr = at91_pmc_read(AT91_PMC_MCKR);
828
	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
829
	freq = mck.parent->rate_hz;
830
	freq /= pmc_prescaler_divider(mckr);					/* prescale */
831
	if (cpu_is_at91rm9200()) {
832
		mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
833
	} else if (cpu_is_at91sam9g20()) {
834
835
836
837
		mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
			freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
		if (mckr & AT91_PMC_PDIV)
			freq /= 2;		/* processor clock division */
838
	} else if (cpu_has_mdiv3()) {
839
840
		mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
			freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
841
	} else {
842
		mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));		/* mdiv */
843
	}
844

845
846
847
848
849
850
	if (cpu_has_alt_prescaler()) {
		/* Programmable clocks can use MCK */
		mck.type |= CLK_TYPE_PRIMARY;
		mck.id = 4;
	}

851
852
	/* Register the PMC's standard clocks */
	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
853
		at91_clk_add(standard_pmc_clocks[i]);
854

855
	if (cpu_has_pllb())
856
		at91_clk_add(&pllb);
857
858

	if (cpu_has_uhp())
859
		at91_clk_add(&uhpck);
860
861

	if (cpu_has_udpfs())
862
		at91_clk_add(&udpck);
863
864

	if (cpu_has_utmi())
865
		at91_clk_add(&utmi_clk);
866

867
868
869
	/* MCK and CPU clock are "always on" */
	clk_enable(&mck);

870
871
872
873
874
	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
		(unsigned) main_clock / 1000000,
		((unsigned) main_clock % 1000000) / 1000);

875
876
877
	return 0;
}

878
879
880
#if defined(CONFIG_OF)
static struct of_device_id pmc_ids[] = {
	{ .compatible = "atmel,at91rm9200-pmc" },
881
882
883
884
885
	{ .compatible = "atmel,at91sam9260-pmc" },
	{ .compatible = "atmel,at91sam9g45-pmc" },
	{ .compatible = "atmel,at91sam9n12-pmc" },
	{ .compatible = "atmel,at91sam9x5-pmc" },
	{ .compatible = "atmel,sama5d3-pmc" },
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
	{ /*sentinel*/ }
};

static struct of_device_id osc_ids[] = {
	{ .compatible = "atmel,osc" },
	{ /*sentinel*/ }
};

int __init at91_dt_clock_init(void)
{
	struct device_node *np;
	u32 main_clock = 0;

	np = of_find_matching_node(NULL, pmc_ids);
	if (!np)
		panic("unable to find compatible pmc node in dtb\n");

	at91_pmc_base = of_iomap(np, 0);
	if (!at91_pmc_base)
		panic("unable to map pmc cpu registers\n");

	of_node_put(np);

	/* retrieve the freqency of fixed clocks from device tree */
	np = of_find_matching_node(NULL, osc_ids);
	if (np) {
		u32 rate;
		if (!of_property_read_u32(np, "clock-frequency", &rate))
			main_clock = rate;
	}

	of_node_put(np);

	return at91_pmc_init(main_clock);
}
#endif

int __init at91_clock_init(unsigned long main_clock)
{
	at91_pmc_base = ioremap(AT91_PMC, 256);
	if (!at91_pmc_base)
		panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);

	return at91_pmc_init(main_clock);
}

932
933
934
935
936
937
/*
 * Several unused clocks may be active.  Turn them off.
 */
static int __init at91_clock_reset(void)
{
	unsigned long pcdr = 0;
938
	unsigned long pcdr1 = 0;
939
940
941
942
943
944
945
	unsigned long scdr = 0;
	struct clk *clk;

	list_for_each_entry(clk, &clocks, node) {
		if (clk->users > 0)
			continue;

946
947
948
949
950
951
952
953
954
955
956
		if (clk->mode == pmc_periph_mode) {
			if (cpu_is_sama5d3()) {
				u32 pmc_mask = 1 << (clk->pid % 32);

				if (clk->pid > 31)
					pcdr1 |= pmc_mask;
				else
					pcdr |= pmc_mask;
			} else
				pcdr |= clk->pmc_mask;
		}
957
958
959
960
961
962

		if (clk->mode == pmc_sys_mode)
			scdr |= clk->pmc_mask;

		pr_debug("Clocks: disable unused %s\n", clk->name);
	}
963

964
	at91_pmc_write(AT91_PMC_SCDR, scdr);
965
	at91_pmc_write(AT91_PMC_PCDR, pcdr);
966
967
	if (cpu_is_sama5d3())
		at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
968
969
970

	return 0;
}
971
late_initcall(at91_clock_reset);
972
973
974

void at91sam9_idle(void)
{
975
	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
976
977
	cpu_do_idle();
}