ich8lan.c 123 KB
Newer Older
1
2
3
/*******************************************************************************

  Intel PRO/1000 Linux driver
Bruce Allan's avatar
Bruce Allan committed
4
  Copyright(c) 1999 - 2013 Intel Corporation.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

29
/* 82562G 10/100 Network Connection
30
31
32
33
34
35
36
37
38
39
40
 * 82562G-2 10/100 Network Connection
 * 82562GT 10/100 Network Connection
 * 82562GT-2 10/100 Network Connection
 * 82562V 10/100 Network Connection
 * 82562V-2 10/100 Network Connection
 * 82566DC-2 Gigabit Network Connection
 * 82566DC Gigabit Network Connection
 * 82566DM-2 Gigabit Network Connection
 * 82566DM Gigabit Network Connection
 * 82566MC Gigabit Network Connection
 * 82566MM Gigabit Network Connection
41
42
 * 82567LM Gigabit Network Connection
 * 82567LF Gigabit Network Connection
43
 * 82567V Gigabit Network Connection
44
45
46
 * 82567LM-2 Gigabit Network Connection
 * 82567LF-2 Gigabit Network Connection
 * 82567V-2 Gigabit Network Connection
47
48
 * 82567LF-3 Gigabit Network Connection
 * 82567LM-3 Gigabit Network Connection
49
 * 82567LM-4 Gigabit Network Connection
50
51
52
53
 * 82577LM Gigabit Network Connection
 * 82577LC Gigabit Network Connection
 * 82578DM Gigabit Network Connection
 * 82578DC Gigabit Network Connection
54
55
 * 82579LM Gigabit Network Connection
 * 82579V Gigabit Network Connection
56
57
58
59
60
61
62
63
 */

#include "e1000.h"

/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
union ich8_hws_flash_status {
	struct ich8_hsfsts {
64
65
66
67
68
69
70
71
72
		u16 flcdone:1;	/* bit 0 Flash Cycle Done */
		u16 flcerr:1;	/* bit 1 Flash Cycle Error */
		u16 dael:1;	/* bit 2 Direct Access error Log */
		u16 berasesz:2;	/* bit 4:3 Sector Erase Size */
		u16 flcinprog:1;	/* bit 5 flash cycle in Progress */
		u16 reserved1:2;	/* bit 13:6 Reserved */
		u16 reserved2:6;	/* bit 13:6 Reserved */
		u16 fldesvalid:1;	/* bit 14 Flash Descriptor Valid */
		u16 flockdn:1;	/* bit 15 Flash Config Lock-Down */
73
74
75
76
77
78
79
80
	} hsf_status;
	u16 regval;
};

/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
/* Offset 06h FLCTL */
union ich8_hws_flash_ctrl {
	struct ich8_hsflctl {
81
82
83
84
85
		u16 flcgo:1;	/* 0 Flash Cycle Go */
		u16 flcycle:2;	/* 2:1 Flash Cycle */
		u16 reserved:5;	/* 7:3 Reserved  */
		u16 fldbcount:2;	/* 9:8 Flash Data Byte Count */
		u16 flockdn:6;	/* 15:10 Reserved */
86
87
88
89
90
91
92
	} hsf_ctrl;
	u16 regval;
};

/* ICH Flash Region Access Permissions */
union ich8_hws_flash_regacc {
	struct ich8_flracc {
93
94
95
96
		u32 grra:8;	/* 0:7 GbE region Read Access */
		u32 grwa:8;	/* 8:15 GbE region Write Access */
		u32 gmrag:8;	/* 23:16 GbE Master Read Access Grant */
		u32 gmwag:8;	/* 31:24 GbE Master Write Access Grant */
97
98
99
100
	} hsf_flregacc;
	u16 regval;
};

101
102
103
104
105
106
107
108
109
110
111
112
113
/* ICH Flash Protected Region */
union ich8_flash_protected_range {
	struct ich8_pr {
		u32 base:13;     /* 0:12 Protected Range Base */
		u32 reserved1:2; /* 13:14 Reserved */
		u32 rpe:1;       /* 15 Read Protection Enable */
		u32 limit:13;    /* 16:28 Protected Range Limit */
		u32 reserved2:2; /* 29:30 Reserved */
		u32 wpe:1;       /* 31 Write Protection Enable */
	} range;
	u32 regval;
};

114
115
116
117
118
static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
						u32 offset, u8 byte);
119
120
static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
					 u8 *data);
121
122
123
124
125
static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
					 u16 *data);
static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
					 u8 size, u16 *data);
static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
126
127
128
129
130
131
132
133
static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
134
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
135
static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
136
static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
137
static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
138
static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
139
140
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
141
static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
Bruce Allan's avatar
Bruce Allan committed
142
static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
143
static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
144
static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167

static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
{
	return readw(hw->flash_address + reg);
}

static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
{
	return readl(hw->flash_address + reg);
}

static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
{
	writew(val, hw->flash_address + reg);
}

static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
{
	writel(val, hw->flash_address + reg);
}

#define er16flash(reg)		__er16flash(hw, (reg))
#define er32flash(reg)		__er32flash(hw, (reg))
168
169
#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
170

171
172
173
174
175
176
177
178
179
180
181
/**
 *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 *  @hw: pointer to the HW structure
 *
 *  Test access to the PHY registers by reading the PHY ID registers.  If
 *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 *  otherwise assume the read PHY ID is correct if it is valid.
 *
 *  Assumes the sw/fw/hw semaphore is already acquired.
 **/
static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
182
{
183
184
185
186
187
188
	u16 phy_reg = 0;
	u32 phy_id = 0;
	s32 ret_val;
	u16 retry_count;

	for (retry_count = 0; retry_count < 2; retry_count++) {
189
		ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
190
191
192
193
		if (ret_val || (phy_reg == 0xFFFF))
			continue;
		phy_id = (u32)(phy_reg << 16);

194
		ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
195
196
197
198
199
200
201
		if (ret_val || (phy_reg == 0xFFFF)) {
			phy_id = 0;
			continue;
		}
		phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
		break;
	}
202
203
204
205

	if (hw->phy.id) {
		if (hw->phy.id == phy_id)
			return true;
206
207
208
	} else if (phy_id) {
		hw->phy.id = phy_id;
		hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
209
210
211
		return true;
	}

212
	/* In case the PHY needs to be in mdio slow mode,
213
214
215
216
217
218
219
220
221
	 * set slow mode and try to get the PHY id again.
	 */
	hw->phy.ops.release(hw);
	ret_val = e1000_set_mdio_slow_mode_hv(hw);
	if (!ret_val)
		ret_val = e1000e_get_phy_id(hw);
	hw->phy.ops.acquire(hw);

	return !ret_val;
222
223
224
225
226
227
228
229
230
231
232
233
234
}

/**
 *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 *  @hw: pointer to the HW structure
 *
 *  Workarounds/flow necessary for PHY initialization during driver load
 *  and resume paths.
 **/
static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
{
	u32 mac_reg, fwsm = er32(FWSM);
	s32 ret_val;
Bruce Allan's avatar
Bruce Allan committed
235
	u16 phy_reg;
236

237
238
239
240
241
	/* Gate automatic PHY configuration by hardware on managed and
	 * non-managed 82579 and newer adapters.
	 */
	e1000_gate_hw_phy_config_ich8lan(hw, true);

242
243
244
	ret_val = hw->phy.ops.acquire(hw);
	if (ret_val) {
		e_dbg("Failed to initialize PHY flow\n");
245
		goto out;
246
247
	}

248
	/* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
249
250
251
252
	 * inaccessible and resetting the PHY is not blocked, toggle the
	 * LANPHYPC Value bit to force the interconnect to PCIe mode.
	 */
	switch (hw->mac.type) {
Bruce Allan's avatar
Bruce Allan committed
253
254
255
256
	case e1000_pch_lpt:
		if (e1000_phy_is_accessible_pchlan(hw))
			break;

257
		/* Before toggling LANPHYPC, see if PHY is accessible by
Bruce Allan's avatar
Bruce Allan committed
258
259
260
261
262
263
264
		 * forcing MAC to SMBus mode first.
		 */
		mac_reg = er32(CTRL_EXT);
		mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
		ew32(CTRL_EXT, mac_reg);

		/* fall-through */
265
	case e1000_pch2lan:
Bruce Allan's avatar
Bruce Allan committed
266
267
268
269
270
271
272
273
274
275
276
277
		if (e1000_phy_is_accessible_pchlan(hw)) {
			if (hw->mac.type == e1000_pch_lpt) {
				/* Unforce SMBus mode in PHY */
				e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
				phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
				e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);

				/* Unforce SMBus mode in MAC */
				mac_reg = er32(CTRL_EXT);
				mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
				ew32(CTRL_EXT, mac_reg);
			}
278
			break;
Bruce Allan's avatar
Bruce Allan committed
279
		}
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299

		/* fall-through */
	case e1000_pchlan:
		if ((hw->mac.type == e1000_pchlan) &&
		    (fwsm & E1000_ICH_FWSM_FW_VALID))
			break;

		if (hw->phy.ops.check_reset_block(hw)) {
			e_dbg("Required LANPHYPC toggle blocked by ME\n");
			break;
		}

		e_dbg("Toggling LANPHYPC\n");

		/* Set Phy Config Counter to 50msec */
		mac_reg = er32(FEXTNVM3);
		mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
		mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
		ew32(FEXTNVM3, mac_reg);

300
301
302
303
304
305
306
307
308
		if (hw->mac.type == e1000_pch_lpt) {
			/* Toggling LANPHYPC brings the PHY out of SMBus mode
			 * So ensure that the MAC is also out of SMBus mode
			 */
			mac_reg = er32(CTRL_EXT);
			mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
			ew32(CTRL_EXT, mac_reg);
		}

309
310
311
312
313
314
		/* Toggle LANPHYPC Value bit */
		mac_reg = er32(CTRL);
		mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
		mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
		ew32(CTRL, mac_reg);
		e1e_flush();
315
		usleep_range(10, 20);
316
317
318
		mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
		ew32(CTRL, mac_reg);
		e1e_flush();
Bruce Allan's avatar
Bruce Allan committed
319
320
321
322
323
324
325
326
327
		if (hw->mac.type < e1000_pch_lpt) {
			msleep(50);
		} else {
			u16 count = 20;
			do {
				usleep_range(5000, 10000);
			} while (!(er32(CTRL_EXT) &
				   E1000_CTRL_EXT_LPCD) && count--);
		}
328
329
330
331
332
333
334
		break;
	default:
		break;
	}

	hw->phy.ops.release(hw);

335
	/* Reset the PHY before any access to it.  Doing so, ensures
336
337
338
339
340
341
	 * that the PHY is in a known good state before we read/write
	 * PHY registers.  The generic reset is sufficient here,
	 * because we haven't determined the PHY type yet.
	 */
	ret_val = e1000e_phy_hw_reset_generic(hw);

342
out:
343
344
345
346
347
348
349
350
	/* Ungate automatic PHY configuration on non-managed 82579 */
	if ((hw->mac.type == e1000_pch2lan) &&
	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
		usleep_range(10000, 20000);
		e1000_gate_hw_phy_config_ich8lan(hw, false);
	}

	return ret_val;
351
352
}

353
354
355
356
357
358
359
360
361
/**
 *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific PHY parameters and function pointers.
 **/
static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
{
	struct e1000_phy_info *phy = &hw->phy;
362
	s32 ret_val;
363
364
365
366

	phy->addr                     = 1;
	phy->reset_delay_us           = 100;

367
	phy->ops.set_page             = e1000_set_page_igp;
368
369
	phy->ops.read_reg             = e1000_read_phy_reg_hv;
	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
370
	phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
371
372
	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
373
374
	phy->ops.write_reg            = e1000_write_phy_reg_hv;
	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
375
	phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
376
377
	phy->ops.power_up             = e1000_power_up_phy_copper;
	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
378
379
	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;

380
	phy->id = e1000_phy_unknown;
381

382
383
384
	ret_val = e1000_init_phy_workarounds_pchlan(hw);
	if (ret_val)
		return ret_val;
385

386
387
388
389
390
391
392
393
394
395
	if (phy->id == e1000_phy_unknown)
		switch (hw->mac.type) {
		default:
			ret_val = e1000e_get_phy_id(hw);
			if (ret_val)
				return ret_val;
			if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
				break;
			/* fall-through */
		case e1000_pch2lan:
Bruce Allan's avatar
Bruce Allan committed
396
		case e1000_pch_lpt:
397
			/* In case the PHY needs to be in mdio slow mode,
398
399
400
401
402
403
404
405
			 * set slow mode and try to get the PHY id again.
			 */
			ret_val = e1000_set_mdio_slow_mode_hv(hw);
			if (ret_val)
				return ret_val;
			ret_val = e1000e_get_phy_id(hw);
			if (ret_val)
				return ret_val;
406
			break;
407
		}
408
409
	phy->type = e1000e_get_phy_type_from_id(phy->id);

410
411
	switch (phy->type) {
	case e1000_phy_82577:
412
	case e1000_phy_82579:
Bruce Allan's avatar
Bruce Allan committed
413
	case e1000_phy_i217:
414
415
		phy->ops.check_polarity = e1000_check_polarity_82577;
		phy->ops.force_speed_duplex =
416
		    e1000_phy_force_speed_duplex_82577;
417
		phy->ops.get_cable_length = e1000_get_cable_length_82577;
418
419
		phy->ops.get_info = e1000_get_phy_info_82577;
		phy->ops.commit = e1000e_phy_sw_reset;
420
		break;
421
422
423
424
425
426
427
428
429
	case e1000_phy_82578:
		phy->ops.check_polarity = e1000_check_polarity_m88;
		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
		phy->ops.get_cable_length = e1000e_get_cable_length_m88;
		phy->ops.get_info = e1000e_get_phy_info_m88;
		break;
	default:
		ret_val = -E1000_ERR_PHY;
		break;
430
431
432
433
434
	}

	return ret_val;
}

435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
/**
 *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific PHY parameters and function pointers.
 **/
static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
{
	struct e1000_phy_info *phy = &hw->phy;
	s32 ret_val;
	u16 i = 0;

	phy->addr			= 1;
	phy->reset_delay_us		= 100;

450
451
452
	phy->ops.power_up               = e1000_power_up_phy_copper;
	phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;

453
	/* We may need to do this twice - once for IGP and if that fails,
454
455
456
457
	 * we'll set BM func pointers and try again
	 */
	ret_val = e1000e_determine_phy_address(hw);
	if (ret_val) {
458
459
		phy->ops.write_reg = e1000e_write_phy_reg_bm;
		phy->ops.read_reg  = e1000e_read_phy_reg_bm;
460
		ret_val = e1000e_determine_phy_address(hw);
Bruce Allan's avatar
Bruce Allan committed
461
462
		if (ret_val) {
			e_dbg("Cannot determine PHY addr. Erroring out\n");
463
			return ret_val;
Bruce Allan's avatar
Bruce Allan committed
464
		}
465
466
	}

467
468
469
	phy->id = 0;
	while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
	       (i++ < 100)) {
470
		usleep_range(1000, 2000);
471
472
473
474
475
476
477
478
479
480
		ret_val = e1000e_get_phy_id(hw);
		if (ret_val)
			return ret_val;
	}

	/* Verify phy id */
	switch (phy->id) {
	case IGP03E1000_E_PHY_ID:
		phy->type = e1000_phy_igp_3;
		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
481
482
		phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
		phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
483
484
485
		phy->ops.get_info = e1000e_get_phy_info_igp;
		phy->ops.check_polarity = e1000_check_polarity_igp;
		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
486
487
488
489
490
491
		break;
	case IFE_E_PHY_ID:
	case IFE_PLUS_E_PHY_ID:
	case IFE_C_E_PHY_ID:
		phy->type = e1000_phy_ife;
		phy->autoneg_mask = E1000_ALL_NOT_GIG;
492
493
494
		phy->ops.get_info = e1000_get_phy_info_ife;
		phy->ops.check_polarity = e1000_check_polarity_ife;
		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
495
		break;
496
497
498
	case BME1000_E_PHY_ID:
		phy->type = e1000_phy_bm;
		phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
499
500
501
		phy->ops.read_reg = e1000e_read_phy_reg_bm;
		phy->ops.write_reg = e1000e_write_phy_reg_bm;
		phy->ops.commit = e1000e_phy_sw_reset;
502
503
504
		phy->ops.get_info = e1000e_get_phy_info_m88;
		phy->ops.check_polarity = e1000_check_polarity_m88;
		phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
505
		break;
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
	default:
		return -E1000_ERR_PHY;
		break;
	}

	return 0;
}

/**
 *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific NVM parameters and function
 *  pointers.
 **/
static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
{
	struct e1000_nvm_info *nvm = &hw->nvm;
	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
525
	u32 gfpreg, sector_base_addr, sector_end_addr;
526
527
	u16 i;

528
	/* Can't read flash registers if the register set isn't mapped. */
529
	if (!hw->flash_address) {
530
		e_dbg("ERROR: Flash registers not mapped\n");
531
532
533
534
535
536
537
		return -E1000_ERR_CONFIG;
	}

	nvm->type = e1000_nvm_flash_sw;

	gfpreg = er32flash(ICH_FLASH_GFPREG);

538
	/* sector_X_addr is a "sector"-aligned address (4096 bytes)
539
	 * Add 1 to sector_end_addr since this sector is included in
540
541
	 * the overall size.
	 */
542
543
544
545
546
547
	sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
	sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;

	/* flash_base_addr is byte-aligned */
	nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;

548
	/* find total size of the NVM, then cut in half since the total
549
550
	 * size represents two separate NVM banks.
	 */
551
552
	nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
				<< FLASH_SECTOR_ADDR_SHIFT);
553
554
555
556
557
558
559
560
	nvm->flash_bank_size /= 2;
	/* Adjust to word count */
	nvm->flash_bank_size /= sizeof(u16);

	nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;

	/* Clear shadow ram */
	for (i = 0; i < nvm->word_size; i++) {
561
		dev_spec->shadow_ram[i].modified = false;
562
563
564
565
566
567
568
569
570
571
572
573
574
		dev_spec->shadow_ram[i].value    = 0xFFFF;
	}

	return 0;
}

/**
 *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 *  @hw: pointer to the HW structure
 *
 *  Initialize family-specific MAC parameters and function
 *  pointers.
 **/
575
static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
576
577
578
579
{
	struct e1000_mac_info *mac = &hw->mac;

	/* Set media type function pointer */
580
	hw->phy.media_type = e1000_media_type_copper;
581
582
583
584
585
586
587

	/* Set mta register count */
	mac->mta_reg_count = 32;
	/* Set rar entry count */
	mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
	if (mac->type == e1000_ich8lan)
		mac->rar_entry_count--;
588
589
590
591
	/* FWSM register */
	mac->has_fwsm = true;
	/* ARC subsystem not supported */
	mac->arc_subsystem_valid = false;
592
593
	/* Adaptive IFS supported */
	mac->adaptive_ifs = true;
594

Bruce Allan's avatar
Bruce Allan committed
595
	/* LED and other operations */
596
597
598
599
	switch (mac->type) {
	case e1000_ich8lan:
	case e1000_ich9lan:
	case e1000_ich10lan:
600
601
		/* check management mode */
		mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
602
		/* ID LED init */
603
		mac->ops.id_led_init = e1000e_id_led_init_generic;
604
605
		/* blink LED */
		mac->ops.blink_led = e1000e_blink_led_generic;
606
607
608
609
610
611
612
613
		/* setup LED */
		mac->ops.setup_led = e1000e_setup_led_generic;
		/* cleanup LED */
		mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
		/* turn on/off LED */
		mac->ops.led_on = e1000_led_on_ich8lan;
		mac->ops.led_off = e1000_led_off_ich8lan;
		break;
614
	case e1000_pch2lan:
615
616
617
		mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
		mac->ops.rar_set = e1000_rar_set_pch2lan;
		/* fall-through */
Bruce Allan's avatar
Bruce Allan committed
618
	case e1000_pch_lpt:
619
	case e1000_pchlan:
620
621
		/* check management mode */
		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
622
623
624
625
626
627
628
629
630
631
632
633
634
635
		/* ID LED init */
		mac->ops.id_led_init = e1000_id_led_init_pchlan;
		/* setup LED */
		mac->ops.setup_led = e1000_setup_led_pchlan;
		/* cleanup LED */
		mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
		/* turn on/off LED */
		mac->ops.led_on = e1000_led_on_pchlan;
		mac->ops.led_off = e1000_led_off_pchlan;
		break;
	default:
		break;
	}

Bruce Allan's avatar
Bruce Allan committed
636
637
638
639
640
	if (mac->type == e1000_pch_lpt) {
		mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
		mac->ops.rar_set = e1000_rar_set_pch_lpt;
	}

641
642
	/* Enable PCS Lock-loss workaround for ICH8 */
	if (mac->type == e1000_ich8lan)
643
		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
644
645
646
647

	return 0;
}

648
649
650
651
652
653
654
655
656
657
658
659
/**
 *  __e1000_access_emi_reg_locked - Read/write EMI register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: pointer to value to read/write from/to the EMI address
 *  @read: boolean flag to indicate read or write
 *
 *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 **/
static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
					 u16 *data, bool read)
{
660
	s32 ret_val;
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681

	ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
	if (ret_val)
		return ret_val;

	if (read)
		ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
	else
		ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);

	return ret_val;
}

/**
 *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: value to be read from the EMI address
 *
 *  Assumes the SW/FW/HW Semaphore is already acquired.
 **/
682
s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
{
	return __e1000_access_emi_reg_locked(hw, addr, data, true);
}

/**
 *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 *  @hw: pointer to the HW structure
 *  @addr: EMI address to program
 *  @data: value to be written to the EMI address
 *
 *  Assumes the SW/FW/HW Semaphore is already acquired.
 **/
static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
{
	return __e1000_access_emi_reg_locked(hw, addr, &data, false);
}

700
701
702
703
/**
 *  e1000_set_eee_pchlan - Enable/disable EEE support
 *  @hw: pointer to the HW structure
 *
704
705
706
 *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 *  the link and the EEE capabilities of the link partner.  The LPI Control
 *  register bits will remain set only if/when link is up.
707
708
709
 **/
static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
{
Bruce Allan's avatar
Bruce Allan committed
710
	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
711
712
	s32 ret_val;
	u16 lpi_ctrl;
713

Bruce Allan's avatar
Bruce Allan committed
714
715
	if ((hw->phy.type != e1000_phy_82579) &&
	    (hw->phy.type != e1000_phy_i217))
716
		return 0;
717

718
	ret_val = hw->phy.ops.acquire(hw);
719
	if (ret_val)
720
		return ret_val;
721

722
	ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
Bruce Allan's avatar
Bruce Allan committed
723
	if (ret_val)
724
725
726
727
728
729
730
731
		goto release;

	/* Clear bits that enable EEE in various speeds */
	lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;

	/* Enable EEE if not disabled by user */
	if (!dev_spec->eee_disable) {
		u16 lpa, pcs_status, data;
Bruce Allan's avatar
Bruce Allan committed
732
733

		/* Save off link partner's EEE ability */
734
735
736
737
738
739
740
741
742
743
744
745
746
747
		switch (hw->phy.type) {
		case e1000_phy_82579:
			lpa = I82579_EEE_LP_ABILITY;
			pcs_status = I82579_EEE_PCS_STATUS;
			break;
		case e1000_phy_i217:
			lpa = I217_EEE_LP_ABILITY;
			pcs_status = I217_EEE_PCS_STATUS;
			break;
		default:
			ret_val = -E1000_ERR_PHY;
			goto release;
		}
		ret_val = e1000_read_emi_reg_locked(hw, lpa,
748
						    &dev_spec->eee_lp_ability);
Bruce Allan's avatar
Bruce Allan committed
749
750
751
		if (ret_val)
			goto release;

752
753
		/* Enable EEE only for speeds in which the link partner is
		 * EEE capable.
Bruce Allan's avatar
Bruce Allan committed
754
		 */
755
756
757
758
		if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
			lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;

		if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
759
760
			e1e_rphy_locked(hw, MII_LPA, &data);
			if (data & LPA_100FULL)
761
762
763
764
765
766
767
768
769
770
771
772
773
774
				lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
			else
				/* EEE is not supported in 100Half, so ignore
				 * partner's EEE in 100 ability if full-duplex
				 * is not advertised.
				 */
				dev_spec->eee_lp_ability &=
				    ~I82579_EEE_100_SUPPORTED;
		}

		/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
		ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
		if (ret_val)
			goto release;
Bruce Allan's avatar
Bruce Allan committed
775
776
	}

777
778
779
780
781
	ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
release:
	hw->phy.ops.release(hw);

	return ret_val;
782
783
}

784
785
786
787
788
789
790
791
792
793
794
795
796
/**
 *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 *  @hw: pointer to the HW structure
 *
 *  Checks to see of the link status of the hardware has changed.  If a
 *  change in link status has been detected, then we read the PHY registers
 *  to get the current speed/duplex if link exists.
 **/
static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
{
	struct e1000_mac_info *mac = &hw->mac;
	s32 ret_val;
	bool link;
797
	u16 phy_reg;
798

799
	/* We only want to go out to the PHY registers to see if Auto-Neg
800
801
802
803
	 * has completed and/or if our link status has changed.  The
	 * get_link_status flag is set upon receiving a Link Status
	 * Change or Rx Sequence Error interrupt.
	 */
804
805
	if (!mac->get_link_status)
		return 0;
806

807
	/* First we want to see if the MII Status Register reports
808
809
810
811
812
	 * link.  If so, then we want to get the current speed/duplex
	 * of the PHY.
	 */
	ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
	if (ret_val)
813
		return ret_val;
814

815
816
817
	if (hw->mac.type == e1000_pchlan) {
		ret_val = e1000_k1_gig_workaround_hv(hw, link);
		if (ret_val)
818
			return ret_val;
819
820
	}

Bruce Allan's avatar
Bruce Allan committed
821
822
823
	/* Clear link partner's EEE ability */
	hw->dev_spec.ich8lan.eee_lp_ability = 0;

824
	if (!link)
825
		return 0; /* No link detected */
826
827
828

	mac->get_link_status = false;

829
830
	switch (hw->mac.type) {
	case e1000_pch2lan:
831
832
		ret_val = e1000_k1_workaround_lv(hw);
		if (ret_val)
833
			return ret_val;
834
835
836
837
838
		/* fall-thru */
	case e1000_pchlan:
		if (hw->phy.type == e1000_phy_82578) {
			ret_val = e1000_link_stall_workaround_hv(hw);
			if (ret_val)
839
				return ret_val;
840
841
		}

842
		/* Workaround for PCHx parts in half-duplex:
843
844
845
846
847
848
849
850
851
852
853
854
855
856
		 * Set the number of preambles removed from the packet
		 * when it is passed from the PHY to the MAC to prevent
		 * the MAC from misinterpreting the packet type.
		 */
		e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;

		if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);

		e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
		break;
	default:
		break;
857
858
	}

859
	/* Check if there was DownShift, must be checked
860
861
862
863
	 * immediately after link-up
	 */
	e1000e_check_downshift(hw);

864
865
866
	/* Enable/Disable EEE after link up */
	ret_val = e1000_set_eee_pchlan(hw);
	if (ret_val)
867
		return ret_val;
868

869
	/* If we are forcing speed/duplex, then we simply return since
870
871
	 * we have already determined whether we have link or not.
	 */
872
873
	if (!mac->autoneg)
		return -E1000_ERR_CONFIG;
874

875
	/* Auto-Neg is enabled.  Auto Speed Detection takes care
876
877
878
	 * of MAC speed/duplex configuration.  So we only need to
	 * configure Collision Distance in the MAC.
	 */
879
	mac->ops.config_collision_dist(hw);
880

881
	/* Configure Flow Control now that Auto-Neg has completed.
882
883
884
885
886
887
	 * First, we need to restore the desired flow control
	 * settings because we may have had to re-autoneg with a
	 * different link partner.
	 */
	ret_val = e1000e_config_fc_after_link_up(hw);
	if (ret_val)
888
		e_dbg("Error configuring flow control\n");
889
890
891
892

	return ret_val;
}

Jeff Kirsher's avatar
Jeff Kirsher committed
893
static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
894
895
896
897
{
	struct e1000_hw *hw = &adapter->hw;
	s32 rc;

898
	rc = e1000_init_mac_params_ich8lan(hw);
899
900
901
902
903
904
905
	if (rc)
		return rc;

	rc = e1000_init_nvm_params_ich8lan(hw);
	if (rc)
		return rc;

906
907
908
909
	switch (hw->mac.type) {
	case e1000_ich8lan:
	case e1000_ich9lan:
	case e1000_ich10lan:
910
		rc = e1000_init_phy_params_ich8lan(hw);
911
912
913
		break;
	case e1000_pchlan:
	case e1000_pch2lan:
Bruce Allan's avatar
Bruce Allan committed
914
	case e1000_pch_lpt:
915
916
917
918
919
		rc = e1000_init_phy_params_pchlan(hw);
		break;
	default:
		break;
	}
920
921
922
	if (rc)
		return rc;

923
	/* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
924
925
926
927
928
	 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
	 */
	if ((adapter->hw.phy.type == e1000_phy_ife) ||
	    ((adapter->hw.mac.type >= e1000_pch2lan) &&
	     (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
929
930
		adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
		adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
931
932

		hw->mac.ops.blink_led = NULL;
933
934
	}

935
	if ((adapter->hw.mac.type == e1000_ich8lan) &&
936
	    (adapter->hw.phy.type != e1000_phy_ife))
937
938
		adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;

939
940
941
942
943
	/* Enable workaround for 82579 w/ ME enabled */
	if ((adapter->hw.mac.type == e1000_pch2lan) &&
	    (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
		adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;

944
945
946
947
	/* Disable EEE by default until IEEE802.3az spec is finalized */
	if (adapter->flags2 & FLAG2_HAS_EEE)
		adapter->hw.dev_spec.ich8lan.eee_disable = true;

948
949
950
	return 0;
}

951
952
static DEFINE_MUTEX(nvm_mutex);

953
954
955
956
957
958
/**
 *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 *  @hw: pointer to the HW structure
 *
 *  Acquires the mutex for performing NVM operations.
 **/
959
static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
960
961
962
963
964
965
966
967
968
969
970
971
{
	mutex_lock(&nvm_mutex);

	return 0;
}

/**
 *  e1000_release_nvm_ich8lan - Release NVM mutex
 *  @hw: pointer to the HW structure
 *
 *  Releases the mutex used while performing NVM operations.
 **/
972
static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
973
974
975
976
{
	mutex_unlock(&nvm_mutex);
}

977
978
979
980
/**
 *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 *  @hw: pointer to the HW structure
 *
981
982
 *  Acquires the software control flag for performing PHY and select
 *  MAC CSR accesses.
983
984
985
 **/
static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
{
986
987
	u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
	s32 ret_val = 0;
988

989
990
	if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
			     &hw->adapter->state)) {
991
		e_dbg("contention for Phy access\n");
992
993
		return -E1000_ERR_PHY;
	}
994

995
996
	while (timeout) {
		extcnf_ctrl = er32(EXTCNF_CTRL);
997
998
		if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
			break;
999

1000
1001
1002
1003
1004
		mdelay(1);
		timeout--;
	}

	if (!timeout) {
1005
		e_dbg("SW has already locked the resource.\n");
1006
1007
1008
1009
		ret_val = -E1000_ERR_CONFIG;
		goto out;
	}

1010
	timeout = SW_FLAG_TIMEOUT;
1011
1012
1013
1014
1015
1016
1017
1018

	extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
	ew32(EXTCNF_CTRL, extcnf_ctrl);

	while (timeout) {
		extcnf_ctrl = er32(EXTCNF_CTRL);
		if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
			break;
1019

1020
1021
1022
1023
1024
		mdelay(1);
		timeout--;
	}

	if (!timeout) {
1025
		e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1026
		      er32(FWSM), extcnf_ctrl);
1027
1028
		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
		ew32(EXTCNF_CTRL, extcnf_ctrl);
1029
1030
		ret_val = -E1000_ERR_CONFIG;
		goto out;
1031
1032
	}

1033
1034
out:
	if (ret_val)
1035
		clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1036
1037

	return ret_val;
1038
1039
1040
1041
1042
1043
}

/**
 *  e1000_release_swflag_ich8lan - Release software control flag
 *  @hw: pointer to the HW structure
 *
1044
1045
 *  Releases the software control flag for performing PHY and select
 *  MAC CSR accesses.
1046
1047
1048
1049
1050
1051
 **/
static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
{
	u32 extcnf_ctrl;

	extcnf_ctrl = er32(EXTCNF_CTRL);
1052
1053
1054
1055
1056
1057
1058

	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
		ew32(EXTCNF_CTRL, extcnf_ctrl);
	} else {
		e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
	}
1059

1060
	clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1061
1062
}

1063
1064
1065
1066
/**
 *  e1000_check_mng_mode_ich8lan - Checks management mode
 *  @hw: pointer to the HW structure
 *
1067
 *  This checks if the adapter has any manageability enabled.
1068
1069
1070
1071
1072
 *  This is a function pointer entry point only called by read/write
 *  routines for the PHY and NVM parts.
 **/
static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
{
1073
1074
1075
	u32 fwsm;

	fwsm = er32(FWSM);
1076
1077
1078
	return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
		((fwsm & E1000_FWSM_MODE_MASK) ==
		 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1079
}
1080

1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
/**
 *  e1000_check_mng_mode_pchlan - Checks management mode
 *  @hw: pointer to the HW structure
 *
 *  This checks if the adapter has iAMT enabled.
 *  This is a function pointer entry point only called by read/write
 *  routines for the PHY and NVM parts.
 **/
static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
{
	u32 fwsm;

	fwsm = er32(FWSM);
	return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1095
	    (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1096
1097
}

1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
/**
 *  e1000_rar_set_pch2lan - Set receive address register
 *  @hw: pointer to the HW structure
 *  @addr: pointer to the receive address
 *  @index: receive address array register
 *
 *  Sets the receive address array register at index to the address passed
 *  in by addr.  For 82579, RAR[0] is the base address register that is to
 *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
 *  Use SHRA[0-3] in place of those reserved for ME.
 **/
static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
{
	u32 rar_low, rar_high;

1113
	/* HW expects these in little endian so we reverse the byte order
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
	 * from network order (big endian) to little endian
	 */
	rar_low = ((u32)addr[0] |
		   ((u32)addr[1] << 8) |
		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));

	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));

	/* If MAC address zero, no need to set the AV bit */
	if (rar_low || rar_high)
		rar_high |= E1000_RAH_AV;

	if (index == 0) {
		ew32(RAL(index), rar_low);
		e1e_flush();
		ew32(RAH(index), rar_high);
		e1e_flush();
		return;
	}

	if (index < hw->mac.rar_entry_count) {
		s32 ret_val;

		ret_val = e1000_acquire_swflag_ich8lan(hw);
		if (ret_val)
			goto out;

		ew32(SHRAL(index - 1), rar_low);
		e1e_flush();
		ew32(SHRAH(index - 1), rar_high);
		e1e_flush();

		e1000_release_swflag_ich8lan(hw);

		/* verify the register updates */
		if ((er32(SHRAL(index - 1)) == rar_low) &&
		    (er32(SHRAH(index - 1)) == rar_high))
			return;

		e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
		      (index - 1), er32(FWSM));
	}

out:
	e_dbg("Failed to write receive address at index %d\n", index);
}

Bruce Allan's avatar
Bruce Allan committed
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
/**
 *  e1000_rar_set_pch_lpt - Set receive address registers
 *  @hw: pointer to the HW structure
 *  @addr: pointer to the receive address
 *  @index: receive address array register
 *
 *  Sets the receive address register array at index to the address passed
 *  in by addr. For LPT, RAR[0] is the base address register that is to
 *  contain the MAC address. SHRA[0-10] are the shared receive address
 *  registers that are shared between the Host and manageability engine (ME).
 **/
static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
{
	u32 rar_low, rar_high;
	u32 wlock_mac;

1177
	/* HW expects these in little endian so we reverse the byte order
Bruce Allan's avatar
Bruce Allan committed
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
	 * from network order (big endian) to little endian
	 */
	rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
		   ((u32)addr[2] << 16) | ((u32)addr[3] << 24));

	rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));

	/* If MAC address zero, no need to set the AV bit */
	if (rar_low || rar_high)
		rar_high |= E1000_RAH_AV;

	if (index == 0) {
		ew32(RAL(index), rar_low);
		e1e_flush();
		ew32(RAH(index), rar_high);
		e1e_flush();
		return;
	}

1197
	/* The manageability engine (ME) can lock certain SHRAR registers that
Bruce Allan's avatar
Bruce Allan committed
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
	 * it is using - those registers are unavailable for use.
	 */
	if (index < hw->mac.rar_entry_count) {
		wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
		wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;

		/* Check if all SHRAR registers are locked */
		if (wlock_mac == 1)
			goto out;

		if ((wlock_mac == 0) || (index <= wlock_mac)) {
			s32 ret_val;

			ret_val = e1000_acquire_swflag_ich8lan(hw);

			if (ret_val)
				goto out;

			ew32(SHRAL_PCH_LPT(index - 1), rar_low);
			e1e_flush();
			ew32(SHRAH_PCH_LPT(index - 1), rar_high);
			e1e_flush();

			e1000_release_swflag_ich8lan(hw);

			/* verify the register updates */
			if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
			    (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
				return;
		}
	}

out:
	e_dbg("Failed to write receive address at index %d\n", index);
}

1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
/**
 *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 *  @hw: pointer to the HW structure
 *
 *  Checks if firmware is blocking the reset of the PHY.
 *  This is a function pointer entry point only called by
 *  reset routines.
 **/
static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
{
	u32 fwsm;

	fwsm = er32(FWSM);

	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
}

1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
/**
 *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 *  @hw: pointer to the HW structure
 *
 *  Assumes semaphore already acquired.
 *
 **/
static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
{
	u16 phy_data;
	u32 strap = er32(STRAP);
Bruce Allan's avatar
Bruce Allan committed
1262
1263
	u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
	    E1000_STRAP_SMT_FREQ_SHIFT;
1264
	s32 ret_val;
1265
1266
1267
1268
1269

	strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;

	ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
	if (ret_val)
1270
		return ret_val;
1271
1272
1273
1274
1275

	phy_data &= ~HV_SMB_ADDR_MASK;
	phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
	phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;

Bruce Allan's avatar
Bruce Allan committed
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
	if (hw->phy.type == e1000_phy_i217) {
		/* Restore SMBus frequency */
		if (freq--) {
			phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
			phy_data |= (freq & (1 << 0)) <<
			    HV_SMB_ADDR_FREQ_LOW_SHIFT;
			phy_data |= (freq & (1 << 1)) <<
			    (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
		} else {
			e_dbg("Unsupported SMB frequency in PHY\n");
		}
	}

1289
	return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1290
1291
}

1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
/**
 *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 *  @hw:   pointer to the HW structure
 *
 *  SW should configure the LCD from the NVM extended configuration region
 *  as a workaround for certain parts.
 **/
static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
{
	struct e1000_phy_info *phy = &hw->phy;
	u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1303
	s32 ret_val = 0;
1304
1305
	u16 word_addr, reg_data, reg_addr, phy_page = 0;

1306
	/* Initialize the PHY from the NVM on ICH platforms.  This
1307
1308
1309
1310
1311
	 * is needed due to an issue where the NVM configuration is
	 * not properly autoloaded after power transitions.
	 * Therefore, after each PHY reset, we will load the
	 * configuration data out of the NVM manually.
	 */
1312
1313
1314
1315
1316
	switch (hw->mac.type) {
	case e1000_ich8lan:
		if (phy->type != e1000_phy_igp_3)
			return ret_val;

1317
1318
		if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
		    (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1319
1320
1321
1322
1323
			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
			break;
		}
		/* Fall-thru */
	case e1000_pchlan:
1324
	case e1000_pch2lan:
Bruce Allan's avatar
Bruce Allan committed
1325
	case e1000_pch_lpt:
1326
		sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1327
1328
1329
1330
1331
1332
1333
1334
		break;
	default:
		return ret_val;
	}

	ret_val = hw->phy.ops.acquire(hw);
	if (ret_val)
		return ret_val;
1335
1336
1337

	data = er32(FEXTNVM);
	if (!(data & sw_cfg_mask))
1338
		goto release;
1339

1340
	/* Make sure HW does not configure LCD from PHY
1341
1342
1343
	 * extended configuration before SW configuration
	 */
	data = er32(EXTCNF_CTRL);
Bruce Allan's avatar
Bruce Allan committed
1344
1345
1346
	if ((hw->mac.type < e1000_pch2lan) &&
	    (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
		goto release;
1347
1348
1349
1350
1351

	cnf_size = er32(EXTCNF_SIZE);
	cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
	cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
	if (!cnf_size)
1352
		goto release;
1353
1354
1355
1356

	cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
	cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;

Bruce Allan's avatar
Bruce Allan committed
1357
1358
1359
	if (((hw->mac.type == e1000_pchlan) &&
	     !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
	    (hw->mac.type > e1000_pchlan)) {
1360
		/* HW configures the SMBus address and LEDs when the
1361
1362
1363
		 * OEM and LCD Write Enable bits are set in the NVM.
		 * When both NVM bits are cleared, SW will configure
		 * them instead.
1364
		 */
1365
		ret_val = e1000_write_smbus_addr(hw);
1366
		if (ret_val)
Bruce Allan's avatar