i7core_edac.c 61.2 KB
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/* Intel i7 core/Nehalem Memory Controller kernel module
 *
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 * This driver supports the memory controllers found on the Intel
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 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
 * and Westmere-EP.
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 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
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 * Copyright (c) 2009-2010 by:
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 *	 Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Forked and adapted from the i5400_edac driver
 *
 * Based on the following public Intel datasheets:
 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
 * Datasheet, Volume 2:
 *	http://download.intel.com/design/processor/datashts/320835.pdf
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/edac.h>
#include <linux/mmzone.h>
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#include <linux/smp.h>
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#include <asm/mce.h>
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#include <asm/processor.h>
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#include <asm/div64.h>
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#include "edac_core.h"

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/* Static vars */
static LIST_HEAD(i7core_edac_list);
static DEFINE_MUTEX(i7core_edac_lock);
static int probed;

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static int use_pci_fixup;
module_param(use_pci_fixup, int, 0444);
MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
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/*
 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
 * registers start at bus 255, and are not reported by BIOS.
 * We currently find devices with only 2 sockets. In order to support more QPI
 * Quick Path Interconnect, just increment this number.
 */
#define MAX_SOCKET_BUSES	2


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/*
 * Alter this version for the module when modifications are made
 */
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#define I7CORE_REVISION    " Ver: 1.0.0"
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#define EDAC_MOD_STR      "i7core_edac"

/*
 * Debug macros
 */
#define i7core_printk(level, fmt, arg...)			\
	edac_printk(level, "i7core", fmt, ##arg)

#define i7core_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

/*
 * i7core Memory Controller Registers
 */

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	/* OFFSETS for Device 0 Function 0 */

#define MC_CFG_CONTROL	0x90
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  #define MC_CFG_UNLOCK		0x02
  #define MC_CFG_LOCK		0x00
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	/* OFFSETS for Device 3 Function 0 */

#define MC_CONTROL	0x48
#define MC_STATUS	0x4c
#define MC_MAX_DOD	0x64

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/*
 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#define MC_TEST_ERR_RCV1	0x60
  #define DIMM2_COR_ERR(r)			((r) & 0x7fff)

#define MC_TEST_ERR_RCV0	0x64
  #define DIMM1_COR_ERR(r)			(((r) >> 16) & 0x7fff)
  #define DIMM0_COR_ERR(r)			((r) & 0x7fff)

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/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
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#define MC_SSRCONTROL		0x48
  #define SSR_MODE_DISABLE	0x00
  #define SSR_MODE_ENABLE	0x01
  #define SSR_MODE_MASK		0x03

#define MC_SCRUB_CONTROL	0x4c
  #define STARTSCRUB		(1 << 24)
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  #define SCRUBINTERVAL_MASK    0xffffff
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#define MC_COR_ECC_CNT_0	0x80
#define MC_COR_ECC_CNT_1	0x84
#define MC_COR_ECC_CNT_2	0x88
#define MC_COR_ECC_CNT_3	0x8c
#define MC_COR_ECC_CNT_4	0x90
#define MC_COR_ECC_CNT_5	0x94

#define DIMM_TOP_COR_ERR(r)			(((r) >> 16) & 0x7fff)
#define DIMM_BOT_COR_ERR(r)			((r) & 0x7fff)


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	/* OFFSETS for Devices 4,5 and 6 Function 0 */

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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  #define THREE_DIMMS_PRESENT		(1 << 24)
  #define SINGLE_QUAD_RANK_PRESENT	(1 << 23)
  #define QUAD_RANK_PRESENT		(1 << 22)
  #define REGISTERED_DIMM		(1 << 15)

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#define MC_CHANNEL_MAPPER	0x60
  #define RDLCH(r, ch)		((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  #define WRLCH(r, ch)		((((r) >> (ch * 6)) & 0x07) - 1)

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#define MC_CHANNEL_RANK_PRESENT 0x7c
  #define RANK_PRESENT_MASK		0xffff

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#define MC_CHANNEL_ADDR_MATCH	0xf0
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#define MC_CHANNEL_ERROR_MASK	0xf8
#define MC_CHANNEL_ERROR_INJECT	0xfc
  #define INJECT_ADDR_PARITY	0x10
  #define INJECT_ECC		0x08
  #define MASK_CACHELINE	0x06
  #define MASK_FULL_CACHELINE	0x06
  #define MASK_MSB32_CACHELINE	0x04
  #define MASK_LSB32_CACHELINE	0x02
  #define NO_MASK_CACHELINE	0x00
  #define REPEAT_EN		0x01
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	/* OFFSETS for Devices 4,5 and 6 Function 1 */
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#define MC_DOD_CH_DIMM0		0x48
#define MC_DOD_CH_DIMM1		0x4c
#define MC_DOD_CH_DIMM2		0x50
  #define RANKOFFSET_MASK	((1 << 12) | (1 << 11) | (1 << 10))
  #define RANKOFFSET(x)		((x & RANKOFFSET_MASK) >> 10)
  #define DIMM_PRESENT_MASK	(1 << 9)
  #define DIMM_PRESENT(x)	(((x) & DIMM_PRESENT_MASK) >> 9)
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  #define MC_DOD_NUMBANK_MASK		((1 << 8) | (1 << 7))
  #define MC_DOD_NUMBANK(x)		(((x) & MC_DOD_NUMBANK_MASK) >> 7)
  #define MC_DOD_NUMRANK_MASK		((1 << 6) | (1 << 5))
  #define MC_DOD_NUMRANK(x)		(((x) & MC_DOD_NUMRANK_MASK) >> 5)
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  #define MC_DOD_NUMROW_MASK		((1 << 4) | (1 << 3) | (1 << 2))
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  #define MC_DOD_NUMROW(x)		(((x) & MC_DOD_NUMROW_MASK) >> 2)
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  #define MC_DOD_NUMCOL_MASK		3
  #define MC_DOD_NUMCOL(x)		((x) & MC_DOD_NUMCOL_MASK)
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#define MC_RANK_PRESENT		0x7c

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#define MC_SAG_CH_0	0x80
#define MC_SAG_CH_1	0x84
#define MC_SAG_CH_2	0x88
#define MC_SAG_CH_3	0x8c
#define MC_SAG_CH_4	0x90
#define MC_SAG_CH_5	0x94
#define MC_SAG_CH_6	0x98
#define MC_SAG_CH_7	0x9c

#define MC_RIR_LIMIT_CH_0	0x40
#define MC_RIR_LIMIT_CH_1	0x44
#define MC_RIR_LIMIT_CH_2	0x48
#define MC_RIR_LIMIT_CH_3	0x4C
#define MC_RIR_LIMIT_CH_4	0x50
#define MC_RIR_LIMIT_CH_5	0x54
#define MC_RIR_LIMIT_CH_6	0x58
#define MC_RIR_LIMIT_CH_7	0x5C
#define MC_RIR_LIMIT_MASK	((1 << 10) - 1)

#define MC_RIR_WAY_CH		0x80
  #define MC_RIR_WAY_OFFSET_MASK	(((1 << 14) - 1) & ~0x7)
  #define MC_RIR_WAY_RANK_MASK		0x7

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/*
 * i7core structs
 */

#define NUM_CHANS 3
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#define MAX_DIMMS 3		/* Max DIMMS per channel */
#define MAX_MCR_FUNC  4
#define MAX_CHAN_FUNC 3
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struct i7core_info {
	u32	mc_control;
	u32	mc_status;
	u32	max_dod;
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	u32	ch_map;
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};

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struct i7core_inject {
	int	enable;

	u32	section;
	u32	type;
	u32	eccmask;

	/* Error address mask */
	int channel, dimm, rank, bank, page, col;
};

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struct i7core_channel {
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	bool		is_3dimms_present;
	bool		is_single_4rank;
	bool		has_4rank;
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	u32		dimms;
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};

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struct pci_id_descr {
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	int			dev;
	int			func;
	int 			dev_id;
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	int			optional;
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};

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struct pci_id_table {
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	const struct pci_id_descr	*descr;
	int				n_devs;
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};

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struct i7core_dev {
	struct list_head	list;
	u8			socket;
	struct pci_dev		**pdev;
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	int			n_devs;
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	struct mem_ctl_info	*mci;
};

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struct i7core_pvt {
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	struct pci_dev	*pci_noncore;
	struct pci_dev	*pci_mcr[MAX_MCR_FUNC + 1];
	struct pci_dev	*pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];

	struct i7core_dev *i7core_dev;
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	struct i7core_info	info;
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	struct i7core_inject	inject;
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	struct i7core_channel	channel[NUM_CHANS];
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	int		ce_count_available;
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			/* ECC corrected errors counts per udimm */
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	unsigned long	udimm_ce_count[MAX_DIMMS];
	int		udimm_last_ce_count[MAX_DIMMS];
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			/* ECC corrected errors counts per rdimm */
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	unsigned long	rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
	int		rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
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	bool		is_registered, enable_scrub;
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	/* Fifo double buffers */
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	struct mce		mce_entry[MCE_LOG_LEN];
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	struct mce		mce_outentry[MCE_LOG_LEN];

	/* Fifo in/out counters */
	unsigned		mce_in, mce_out;

	/* Count indicator to show errors not got */
	unsigned		mce_overrun;
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	/* DCLK Frequency used for computing scrub rate */
	int			dclk_freq;

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	/* Struct to control EDAC polling */
	struct edac_pci_ctl_info *i7core_pci;
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};

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#define PCI_DESCR(device, function, device_id)	\
	.dev = (device),			\
	.func = (function),			\
	.dev_id = (device_id)

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static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
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		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
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			/* Exists only for RDIMM */
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	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1  },
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	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
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		/* Generic Non-core registers */
	/*
	 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
	 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
	 * the probing code needs to test for the other address in case of
	 * failure of this one
	 */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE)  },

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};
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static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
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	{ PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR)         },
	{ PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD)      },
	{ PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST)     },

	{ PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
	{ PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
	{ PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
	{ PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC)   },

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	{ PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
	{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
	{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
	{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC)   },
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	/*
	 * This is the PCI device has an alternate address on some
	 * processors like Core i7 860
	 */
	{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE)     },
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};

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static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
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		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2)  },
			/* Exists only for RDIMM */
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1  },
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2)   },
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		/* Generic Non-core registers */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2)  },

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};

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#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
static const struct pci_id_table pci_dev_table[] = {
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	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
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	{0,}			/* 0 terminated list. */
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};

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/*
 *	pci_device_id	table for which devices we are looking for
 */
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static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
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	{0,}			/* 0 terminated list. */
};

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/****************************************************************************
			Anciliary status routines
 ****************************************************************************/

	/* MC_CONTROL bits */
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#define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
#define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
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	/* MC_STATUS bits */
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#define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 4))
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#define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
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	/* MC_MAX_DOD read functions */
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static inline int numdimms(u32 dimms)
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{
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	return (dimms & 0x3) + 1;
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}

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static inline int numrank(u32 rank)
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{
	static int ranks[4] = { 1, 2, 4, -EINVAL };

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	return ranks[rank & 0x3];
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}

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static inline int numbank(u32 bank)
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{
	static int banks[4] = { 4, 8, 16, -EINVAL };

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	return banks[bank & 0x3];
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}

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static inline int numrow(u32 row)
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{
	static int rows[8] = {
		1 << 12, 1 << 13, 1 << 14, 1 << 15,
		1 << 16, -EINVAL, -EINVAL, -EINVAL,
	};

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	return rows[row & 0x7];
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}

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static inline int numcol(u32 col)
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{
	static int cols[8] = {
		1 << 10, 1 << 11, 1 << 12, -EINVAL,
	};
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	return cols[col & 0x3];
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}

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static struct i7core_dev *get_i7core_dev(u8 socket)
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{
	struct i7core_dev *i7core_dev;

	list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
		if (i7core_dev->socket == socket)
			return i7core_dev;
	}

	return NULL;
}

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static struct i7core_dev *alloc_i7core_dev(u8 socket,
					   const struct pci_id_table *table)
{
	struct i7core_dev *i7core_dev;

	i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
	if (!i7core_dev)
		return NULL;

	i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
				   GFP_KERNEL);
	if (!i7core_dev->pdev) {
		kfree(i7core_dev);
		return NULL;
	}

	i7core_dev->socket = socket;
	i7core_dev->n_devs = table->n_devs;
	list_add_tail(&i7core_dev->list, &i7core_edac_list);

	return i7core_dev;
}

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static void free_i7core_dev(struct i7core_dev *i7core_dev)
{
	list_del(&i7core_dev->list);
	kfree(i7core_dev->pdev);
	kfree(i7core_dev);
}

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/****************************************************************************
			Memory check routines
 ****************************************************************************/
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static int get_dimm_config(struct mem_ctl_info *mci)
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{
	struct i7core_pvt *pvt = mci->pvt_info;
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	struct pci_dev *pdev;
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	int i, j;
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	enum edac_type mode;
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	enum mem_type mtype;
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	struct dimm_info *dimm;
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	/* Get data from the MC register, function 0 */
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	pdev = pvt->pci_mcr[0];
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	if (!pdev)
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		return -ENODEV;

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	/* Device 3 function 0 reads */
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	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
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	debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
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		pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
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		pvt->info.max_dod, pvt->info.ch_map);
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	if (ECC_ENABLED(pvt)) {
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		debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
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		if (ECCx8(pvt))
			mode = EDAC_S8ECD8ED;
		else
			mode = EDAC_S4ECD4ED;
	} else {
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		debugf0("ECC disabled\n");
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		mode = EDAC_NONE;
	}
531 532

	/* FIXME: need to handle the error codes */
533 534
	debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
		"x%x x 0x%x\n",
535 536
		numdimms(pvt->info.max_dod),
		numrank(pvt->info.max_dod >> 2),
537
		numbank(pvt->info.max_dod >> 4),
538 539
		numrow(pvt->info.max_dod >> 6),
		numcol(pvt->info.max_dod >> 9));
540

541
	for (i = 0; i < NUM_CHANS; i++) {
542
		u32 data, dimm_dod[3], value[8];
543

544 545 546
		if (!pvt->pci_ch[i][0])
			continue;

547 548 549 550 551 552 553 554 555
		if (!CH_ACTIVE(pvt, i)) {
			debugf0("Channel %i is not active\n", i);
			continue;
		}
		if (CH_DISABLED(pvt, i)) {
			debugf0("Channel %i is disabled\n", i);
			continue;
		}

556
		/* Devices 4-6 function 0 */
557
		pci_read_config_dword(pvt->pci_ch[i][0],
558 559
				MC_CHANNEL_DIMM_INIT_PARAMS, &data);

560 561 562 563 564 565 566 567 568

		if (data & THREE_DIMMS_PRESENT)
			pvt->channel[i].is_3dimms_present = true;

		if (data & SINGLE_QUAD_RANK_PRESENT)
			pvt->channel[i].is_single_4rank = true;

		if (data & QUAD_RANK_PRESENT)
			pvt->channel[i].has_4rank = true;
569

570 571
		if (data & REGISTERED_DIMM)
			mtype = MEM_RDDR3;
572
		else
573 574 575
			mtype = MEM_DDR3;

		/* Devices 4-6 function 1 */
576
		pci_read_config_dword(pvt->pci_ch[i][1],
577
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
578
		pci_read_config_dword(pvt->pci_ch[i][1],
579
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
580
		pci_read_config_dword(pvt->pci_ch[i][1],
581
				MC_DOD_CH_DIMM2, &dimm_dod[2]);
582

583
		debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
584
			"%s%s%s%cDIMMs\n",
585 586 587
			i,
			RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
			data,
588 589 590
			pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
			pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
			pvt->channel[i].has_4rank ? "HAS_4R " : "",
591
			(data & REGISTERED_DIMM) ? 'R' : 'U');
592 593 594

		for (j = 0; j < 3; j++) {
			u32 banks, ranks, rows, cols;
595
			u32 size, npages;
596 597 598 599

			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;

600 601
			dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
				       i, j, 0);
602 603 604 605 606
			banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
			ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
			rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
			cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));

607 608 609
			/* DDR3 has 8 I/O banks */
			size = (rows * cols * banks * ranks) >> (20 - 3);

610 611 612
			debugf0("\tdimm %d %d Mb offset: %x, "
				"bank: %d, rank: %d, row: %#x, col: %#x\n",
				j, size,
613 614 615
				RANKOFFSET(dimm_dod[j]),
				banks, ranks, rows, cols);

616
			npages = MiB_TO_PAGES(size);
617

618 619
			dimm->nr_pages = npages;

620 621
			switch (banks) {
			case 4:
622
				dimm->dtype = DEV_X4;
623 624
				break;
			case 8:
625
				dimm->dtype = DEV_X8;
626 627
				break;
			case 16:
628
				dimm->dtype = DEV_X16;
629 630
				break;
			default:
631
				dimm->dtype = DEV_UNKNOWN;
632 633
			}

634 635 636 637 638 639
			snprintf(dimm->label, sizeof(dimm->label),
				 "CPU#%uChannel#%u_DIMM#%u",
				 pvt->i7core_dev->socket, i, j);
			dimm->grain = 8;
			dimm->edac_mode = mode;
			dimm->mtype = mtype;
640
		}
641

642 643 644 645 646 647 648 649
		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
		pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
		pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
		pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
		pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
650
		debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
651
		for (j = 0; j < 8; j++)
652
			debugf1("\t\t%#x\t%#x\t%#x\n",
653 654
				(value[j] >> 27) & 0x1,
				(value[j] >> 24) & 0x7,
655
				(value[j] & ((1 << 24) - 1)));
656 657
	}

658 659 660
	return 0;
}

661 662 663 664 665 666 667 668 669 670 671
/****************************************************************************
			Error insertion routines
 ****************************************************************************/

/* The i7core has independent error injection features per channel.
   However, to have a simpler code, we don't allow enabling error injection
   on more than one channel.
   Also, since a change at an inject parameter will be applied only at enable,
   we're disabling error injection on all write calls to the sysfs nodes that
   controls the error code injection.
 */
672
static int disable_inject(const struct mem_ctl_info *mci)
673 674 675 676 677
{
	struct i7core_pvt *pvt = mci->pvt_info;

	pvt->inject.enable = 0;

678
	if (!pvt->pci_ch[pvt->inject.channel][0])
679 680
		return -ENODEV;

681
	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
682
				MC_CHANNEL_ERROR_INJECT, 0);
683 684

	return 0;
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701
}

/*
 * i7core inject inject.section
 *
 *	accept and store error injection inject.section value
 *	bit 0 - refers to the lower 32-byte half cacheline
 *	bit 1 - refers to the upper 32-byte half cacheline
 */
static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
					   const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
702
		disable_inject(mci);
703 704 705

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 3))
706
		return -EIO;
707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734

	pvt->inject.section = (u32) value;
	return count;
}

static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.section);
}

/*
 * i7core inject.type
 *
 *	accept and store error injection inject.section value
 *	bit 0 - repeat enable - Enable error repetition
 *	bit 1 - inject ECC error
 *	bit 2 - inject parity error
 */
static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
735
		disable_inject(mci);
736 737 738

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 7))
739
		return -EIO;
740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769

	pvt->inject.type = (u32) value;
	return count;
}

static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.type);
}

/*
 * i7core_inject_inject.eccmask_store
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
770
		disable_inject(mci);
771 772 773

	rc = strict_strtoul(data, 10, &value);
	if (rc < 0)
774
		return -EIO;
775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797

	pvt->inject.eccmask = (u32) value;
	return count;
}

static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
}

/*
 * i7core_addrmatch
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */

798 799 800 801 802
#define DECLARE_ADDR_MATCH(param, limit)			\
static ssize_t i7core_inject_store_##param(			\
		struct mem_ctl_info *mci,			\
		const char *data, size_t count)			\
{								\
803
	struct i7core_pvt *pvt;					\
804 805 806
	long value;						\
	int rc;							\
								\
807 808 809
	debugf1("%s()\n", __func__);				\
	pvt = mci->pvt_info;					\
								\
810 811 812
	if (pvt->inject.enable)					\
		disable_inject(mci);				\
								\
813
	if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829
		value = -1;					\
	else {							\
		rc = strict_strtoul(data, 10, &value);		\
		if ((rc < 0) || (value >= limit))		\
			return -EIO;				\
	}							\
								\
	pvt->inject.param = value;				\
								\
	return count;						\
}								\
								\
static ssize_t i7core_inject_show_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
830 831 832 833
	struct i7core_pvt *pvt;					\
								\
	pvt = mci->pvt_info;					\
	debugf1("%s() pvt=%p\n", __func__, pvt);		\
834 835 836 837
	if (pvt->inject.param < 0)				\
		return sprintf(data, "any\n");			\
	else							\
		return sprintf(data, "%d\n", pvt->inject.param);\
838 839
}

840 841 842 843 844 845 846 847 848
#define ATTR_ADDR_MATCH(param)					\
	{							\
		.attr = {					\
			.name = #param,				\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_inject_show_##param,		\
		.store = i7core_inject_store_##param,		\
	}
849

850 851 852 853 854 855
DECLARE_ADDR_MATCH(channel, 3);
DECLARE_ADDR_MATCH(dimm, 3);
DECLARE_ADDR_MATCH(rank, 4);
DECLARE_ADDR_MATCH(bank, 32);
DECLARE_ADDR_MATCH(page, 0x10000);
DECLARE_ADDR_MATCH(col, 0x4000);
856

857
static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
858 859 860 861
{
	u32 read;
	int count;

862 863 864 865
	debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val);

866 867
	for (count = 0; count < 10; count++) {
		if (count)
868
			msleep(100);
869 870 871 872 873 874 875
		pci_write_config_dword(dev, where, val);
		pci_read_config_dword(dev, where, &read);

		if (read == val)
			return 0;
	}

876 877 878 879
	i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
		"write=%08x. Read=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val, read);
880 881 882 883

	return -EINVAL;
}

884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
/*
 * This routine prepares the Memory Controller for error injection.
 * The error will be injected when some process tries to write to the
 * memory that matches the given criteria.
 * The criteria can be set in terms of a mask where dimm, rank, bank, page
 * and col can be specified.
 * A -1 value for any of the mask items will make the MCU to ignore
 * that matching criteria for error injection.
 *
 * It should be noticed that the error will only happen after a write operation
 * on a memory that matches the condition. if REPEAT_EN is not enabled at
 * inject mask, then it will produce just one error. Otherwise, it will repeat
 * until the injectmask would be cleaned.
 *
 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 *    is reliable enough to check if the MC is using the
 *    three channels. However, this is not clear at the datasheet.
 */
static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
				       const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 injectmask;
	u64 mask = 0;
	int  rc;
	long enable;

911
	if (!pvt->pci_ch[pvt->inject.channel][0])
912 913
		return 0;

914 915 916 917 918 919 920 921 922 923 924 925 926
	rc = strict_strtoul(data, 10, &enable);
	if ((rc < 0))
		return 0;

	if (enable) {
		pvt->inject.enable = 1;
	} else {
		disable_inject(mci);
		return count;
	}

	/* Sets pvt->inject.dimm mask */
	if (pvt->inject.dimm < 0)
927
		mask |= 1LL << 41;
928
	else {
929
		if (pvt->channel[pvt->inject.channel].dimms > 2)
930
			mask |= (pvt->inject.dimm & 0x3LL) << 35;
931
		else
932
			mask |= (pvt->inject.dimm & 0x1LL) << 36;
933 934 935 936
	}

	/* Sets pvt->inject.rank mask */
	if (pvt->inject.rank < 0)
937
		mask |= 1LL << 40;
938
	else {
939
		if (pvt->channel[pvt->inject.channel].dimms > 2)
940
			mask |= (pvt->inject.rank & 0x1LL) << 34;
941
		else
942
			mask |= (pvt->inject.rank & 0x3LL) << 34;
943 944 945 946
	}

	/* Sets pvt->inject.bank mask */
	if (pvt->inject.bank < 0)
947
		mask |= 1LL << 39;
948
	else
949
		mask |= (pvt->inject.bank & 0x15LL) << 30;
950 951 952

	/* Sets pvt->inject.page mask */
	if (pvt->inject.page < 0)
953
		mask |= 1LL << 38;
954
	else
955
		mask |= (pvt->inject.page & 0xffff) << 14;
956 957 958

	/* Sets pvt->inject.column mask */
	if (pvt->inject.col < 0)
959
		mask |= 1LL << 37;
960
	else
961
		mask |= (pvt->inject.col & 0x3fff);
962

963 964 965 966 967 968 969 970 971 972 973 974
	/*
	 * bit    0: REPEAT_EN
	 * bits 1-2: MASK_HALF_CACHELINE
	 * bit    3: INJECT_ECC
	 * bit    4: INJECT_ADDR_PARITY
	 */

	injectmask = (pvt->inject.type & 1) |
		     (pvt->inject.section & 0x3) << 1 |
		     (pvt->inject.type & 0x6) << (3 - 1);

	/* Unlock writes to registers - this register is write only */
975
	pci_write_config_dword(pvt->pci_noncore,
976
			       MC_CFG_CONTROL, 0x2);
977

978
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
979
			       MC_CHANNEL_ADDR_MATCH, mask);
980
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
981 982
			       MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);

983
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
984 985
			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);

986
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
987
			       MC_CHANNEL_ERROR_INJECT, injectmask);
988

989
	/*
990 991 992
	 * This is something undocumented, based on my tests
	 * Without writing 8 to this register, errors aren't injected. Not sure
	 * why.
993
	 */
994
	pci_write_config_dword(pvt->pci_noncore,
995
			       MC_CFG_CONTROL, 8);
996

997 998
	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
		" inject 0x%08x\n",
999 1000
		mask, pvt->inject.eccmask, injectmask);

1001

1002 1003 1004 1005 1006 1007 1008
	return count;
}

static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
					char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
1009 1010
	u32 injectmask;

1011 1012 1013
	if (!pvt->pci_ch[pvt->inject.channel][0])
		return 0;

1014
	pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1015
			       MC_CHANNEL_ERROR_INJECT, &injectmask);
1016 1017 1018 1019 1020 1021

	debugf0("Inject error read: 0x%018x\n", injectmask);

	if (injectmask & 0x0c)
		pvt->inject.enable = 1;

1022 1023 1024
	return sprintf(data, "%d\n", pvt->inject.enable);
}

1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037
#define DECLARE_COUNTER(param)					\
static ssize_t i7core_show_counter_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
	struct i7core_pvt *pvt = mci->pvt_info;			\
								\
	debugf1("%s() \n", __func__);				\
	if (!pvt->ce_count_available || (pvt->is_registered))	\
		return sprintf(data, "data unavailable\n");	\
	return sprintf(data, "%lu\n",				\
			pvt->udimm_ce_count[param]);		\
}
1038

1039 1040 1041 1042 1043 1044 1045
#define ATTR_COUNTER(param)					\
	{							\
		.attr = {					\
			.name = __stringify(udimm##param),	\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_show_counter_##param		\
1046
	}
1047

1048 1049 1050
DECLARE_COUNTER(0);
DECLARE_COUNTER(1);
DECLARE_COUNTER(2);
1051

1052 1053 1054
/*
 * Sysfs struct
 */
1055

1056
static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1057 1058 1059 1060 1061 1062
	ATTR_ADDR_MATCH(channel),
	ATTR_ADDR_MATCH(dimm),
	ATTR_ADDR_MATCH(rank),
	ATTR_ADDR_MATCH(bank),
	ATTR_ADDR_MATCH(page),
	ATTR_ADDR_MATCH(col),
1063
	{ } /* End of list */
1064 1065
};

1066
static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1067 1068 1069 1070
	.name  = "inject_addrmatch",
	.mcidev_attr = i7core_addrmatch_attrs,
};

1071
static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1072 1073 1074
	ATTR_COUNTER(0),
	ATTR_COUNTER(1),
	ATTR_COUNTER(2),
1075
	{ .attr = { .name = NULL } }
1076 1077
};

1078
static const struct mcidev_sysfs_group i7core_udimm_counters = {
1079 1080 1081 1082
	.name  = "all_channel_counts",
	.mcidev_attr = i7core_udimm_counters_attrs,
};

1083
static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
1106
		.grp = &i7core_inject_addrmatch,
1107 1108 1109 1110 1111 1112 1113 1114
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	},
1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
	{ }	/* End of list */
};

static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
		.grp = &i7core_inject_addrmatch,
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	}, {
		.grp = &i7core_udimm_counters,
	},
	{ }	/* End of list */
1153 1154
};

1155 1156 1157 1158 1159
/****************************************************************************
	Device initialization routines: put/get, init/exit
 ****************************************************************************/

/*
1160
 *	i7core_put_all_devices	'put' all the devices that we have
1161 1162
 *				reserved via 'get'
 */
1163
static void i7core_put_devices(struct i7core_dev *i7core_dev)
1164
{
1165
	int i;
1166

1167
	debugf0(__FILE__ ": %s()\n", __func__);
1168
	for (i = 0; i < i7core_dev->n_devs; i++) {
1169 1170 1171 1172 1173 1174 1175 1176
		struct pci_dev *pdev = i7core_dev->pdev[i];
		if (!pdev)
			continue;
		debugf0("Removing dev %02x:%02x.%d\n",
			pdev->bus->number,
			PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
		pci_dev_put(pdev);
	}
1177
}
1178

1179 1180
static void i7core_put_all_devices(void)
{
1181
	struct i7core_dev *i7core_dev, *tmp;
1182

1183
	list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1184
		i7core_put_devices(i7core_dev);
1185
		free_i7core_dev(i7core_dev);
1186
	}
1187 1188
}

1189
static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1190 1191 1192
{
	struct pci_dev *pdev = NULL;
	int i;
1193

1194
	/*
1195
	 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
1196 1197 1198
	 * aren't announced by acpi. So, we need to use a legacy scan probing
	 * to detect them
	 */
1199 1200 1201 1202 1203 1204
	while (table && table->descr) {
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
		if (unlikely(!pdev)) {
			for (i = 0; i < MAX_SOCKET_BUSES; i++)
				pcibios_scan_specific_bus(255-i);
		}
1205
		pci_dev_put(pdev);
1206
		table++;
1207 1208 1209
	}
}

1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226
static unsigned i7core_pci_lastbus(void)
{
	int last_bus = 0, bus;
	struct pci_bus *b = NULL;

	while ((b = pci_find_next_bus(b)) != NULL) {
		bus = b->number;
		debugf0("Found bus %d\n", bus);
		if (bus > last_bus)
			last_bus = bus;
	}

	debugf0("Last bus %d\n", last_bus);

	return last_bus;
}

1227
/*
1228
 *	i7core_get_all_devices	Find and perform 'get' operation on the MCH's
1229 1230 1231 1232
 *			device/functions we want to reference for this driver
 *
 *			Need to 'get' device 16 func 1 and func 2
 */
1233 1234 1235 1236
static int i7core_get_onedevice(struct pci_dev **prev,
				const struct pci_id_table *table,
				const unsigned devno,
				const unsigned last_bus)
1237
{
1238
	struct i7core_dev *i7core_dev;
1239
	const struct pci_id_descr *dev_descr = &table->descr[devno];
1240

1241
	struct pci_dev *pdev = NULL;
1242 1243
	u8 bus = 0;
	u8 socket = 0;
1244

1245
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1246
			      dev_descr->dev_id, *prev);
1247

1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261
	/*
	 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
	 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
	 * to probe for the alternate address in case of failure
	 */
	if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				      PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);

	if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				      PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
				      *prev);

1262 1263 1264 1265
	if (!pdev) {
		if (*prev) {
			*prev = pdev;
			return 0;
1266 1267
		}

1268
		if (dev_descr->optional)
1269
			return 0;
1270