qcom-timer.c 6.41 KB
Newer Older
1
/*
2 3
 *
 * Copyright (C) 2007 Google, Inc.
4
 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
5 6 7 8 9 10 11 12 13 14 15 16
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

17 18
#include <linux/clocksource.h>
#include <linux/clockchips.h>
19
#include <linux/cpu.h>
20 21 22
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
23
#include <linux/io.h>
24 25 26
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
27
#include <linux/sched_clock.h>
28

29 30
#include <asm/delay.h>

31 32 33 34 35 36 37 38 39
#define TIMER_MATCH_VAL			0x0000
#define TIMER_COUNT_VAL			0x0004
#define TIMER_ENABLE			0x0008
#define TIMER_ENABLE_CLR_ON_MATCH_EN	BIT(1)
#define TIMER_ENABLE_EN			BIT(0)
#define TIMER_CLEAR			0x000C
#define DGT_CLK_CTL			0x10
#define DGT_CLK_CTL_DIV_4		0x3
#define TIMER_STS_GPT0_CLR_PEND		BIT(10)
40 41

#define GPT_HZ 32768
42

43
static void __iomem *event_base;
44
static void __iomem *sts_base;
45

46 47
static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
48
	struct clock_event_device *evt = dev_id;
49
	/* Stop the timer tick */
50
	if (clockevent_state_oneshot(evt)) {
51
		u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
52
		ctrl &= ~TIMER_ENABLE_EN;
53
		writel_relaxed(ctrl, event_base + TIMER_ENABLE);
54
	}
55 56 57 58 59 60 61
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static int msm_timer_set_next_event(unsigned long cycles,
				    struct clock_event_device *evt)
{
62
	u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
63

64 65 66 67
	ctrl &= ~TIMER_ENABLE_EN;
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);

	writel_relaxed(ctrl, event_base + TIMER_CLEAR);
68
	writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
69 70 71 72 73

	if (sts_base)
		while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
			cpu_relax();

74
	writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
75 76 77
	return 0;
}

78
static int msm_timer_shutdown(struct clock_event_device *evt)
79
{
80 81
	u32 ctrl;

82
	ctrl = readl_relaxed(event_base + TIMER_ENABLE);
83
	ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
84
	writel_relaxed(ctrl, event_base + TIMER_ENABLE);
85
	return 0;
86 87
}

88
static struct clock_event_device __percpu *msm_evt;
89 90 91

static void __iomem *source_base;

92
static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
93 94 95 96
{
	return readl_relaxed(source_base + TIMER_COUNT_VAL);
}

97 98 99 100
static struct clocksource msm_clocksource = {
	.name	= "dg_timer",
	.rating	= 300,
	.read	= msm_read_timer_count,
101
	.mask	= CLOCKSOURCE_MASK(32),
102
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
103 104
};

105 106 107
static int msm_timer_irq;
static int msm_timer_has_ppi;

108
static int msm_local_timer_starting_cpu(unsigned int cpu)
109
{
110
	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
111 112 113 114 115 116
	int err;

	evt->irq = msm_timer_irq;
	evt->name = "msm_timer";
	evt->features = CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 200;
117 118 119
	evt->set_state_shutdown = msm_timer_shutdown;
	evt->set_state_oneshot = msm_timer_shutdown;
	evt->tick_resume = msm_timer_shutdown;
120
	evt->set_next_event = msm_timer_set_next_event;
121 122 123 124 125 126 127 128 129 130 131 132 133
	evt->cpumask = cpumask_of(cpu);

	clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);

	if (msm_timer_has_ppi) {
		enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
	} else {
		err = request_irq(evt->irq, msm_timer_interrupt,
				IRQF_TIMER | IRQF_NOBALANCING |
				IRQF_TRIGGER_RISING, "gp_timer", evt);
		if (err)
			pr_err("request_irq failed\n");
	}
134 135 136 137

	return 0;
}

138
static int msm_local_timer_dying_cpu(unsigned int cpu)
139
{
140 141
	struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);

142
	evt->set_state_shutdown(evt);
143
	disable_percpu_irq(evt->irq);
144
	return 0;
145 146
}

147
static u64 notrace msm_sched_clock_read(void)
148 149 150 151
{
	return msm_clocksource.read(&msm_clocksource);
}

152 153 154 155 156 157 158 159 160
static unsigned long msm_read_current_timer(void)
{
	return msm_clocksource.read(&msm_clocksource);
}

static struct delay_timer msm_delay_timer = {
	.read_current_timer = msm_read_current_timer,
};

161
static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
162
				  bool percpu)
163
{
164
	struct clocksource *cs = &msm_clocksource;
165 166 167 168 169 170 171 172 173 174
	int res = 0;

	msm_timer_irq = irq;
	msm_timer_has_ppi = percpu;

	msm_evt = alloc_percpu(struct clock_event_device);
	if (!msm_evt) {
		pr_err("memory allocation failed for clockevents\n");
		goto err;
	}
175

176 177 178
	if (percpu)
		res = request_percpu_irq(irq, msm_timer_interrupt,
					 "gp_timer", msm_evt);
179

180 181 182
	if (res) {
		pr_err("request_percpu_irq failed\n");
	} else {
183 184 185 186 187
		/* Install and invoke hotplug callbacks */
		res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
					"AP_QCOM_TIMER_STARTING",
					msm_local_timer_starting_cpu,
					msm_local_timer_dying_cpu);
188 189
		if (res) {
			free_percpu_irq(irq, msm_evt);
190
			goto err;
191
		}
192
	}
193 194

err:
195
	writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
196
	res = clocksource_register_hz(cs, dgt_hz);
197
	if (res)
198
		pr_err("clocksource_register failed\n");
199
	sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
200 201
	msm_delay_timer.freq = dgt_hz;
	register_current_timer_delay(&msm_delay_timer);
202 203

	return res;
204 205
}

206
static int __init msm_dt_timer_init(struct device_node *np)
207 208
{
	u32 freq;
209
	int irq, ret;
210 211
	struct resource res;
	u32 percpu_offset;
212 213
	void __iomem *base;
	void __iomem *cpu0_base;
214

215 216
	base = of_iomap(np, 0);
	if (!base) {
217
		pr_err("Failed to map event base\n");
218
		return -ENXIO;
219 220
	}

221 222
	/* We use GPT0 for the clockevent */
	irq = irq_of_parse_and_map(np, 1);
223 224
	if (irq <= 0) {
		pr_err("Can't get irq\n");
225
		return -EINVAL;
226 227
	}

228
	/* We use CPU0's DGT for the clocksource */
229 230 231
	if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
		percpu_offset = 0;

232 233
	ret = of_address_to_resource(np, 0, &res);
	if (ret) {
234
		pr_err("Failed to parse DGT resource\n");
235
		return ret;
236 237
	}

238 239
	cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
	if (!cpu0_base) {
240
		pr_err("Failed to map source base\n");
241
		return -EINVAL;
242 243 244 245
	}

	if (of_property_read_u32(np, "clock-frequency", &freq)) {
		pr_err("Unknown frequency\n");
246
		return -EINVAL;
247 248
	}

249
	event_base = base + 0x4;
250
	sts_base = base + 0x88;
251 252 253 254
	source_base = cpu0_base + 0x24;
	freq /= 4;
	writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);

255
	return msm_timer_init(freq, 32, irq, !!percpu_offset);
256
}
257 258
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);