op_model_mipsxx.c 6.88 KB
Newer Older
1
2
3
4
5
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
6
 * Copyright (C) 2004, 05, 06 by Ralf Baechle
7
8
9
10
11
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
12
#include <asm/irq_regs.h>
13
14
15

#include "op_impl.h"

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
#define M_PERFCTL_EXL			(1UL      <<  0)
#define M_PERFCTL_KERNEL		(1UL      <<  1)
#define M_PERFCTL_SUPERVISOR		(1UL      <<  2)
#define M_PERFCTL_USER			(1UL      <<  3)
#define M_PERFCTL_INTERRUPT_ENABLE	(1UL      <<  4)
#define M_PERFCTL_EVENT(event)		((event)  << 5)
#define M_PERFCTL_VPEID(vpe)		((vpe)    << 16)
#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
#define    M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
#define    M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
#define    M_TC_EN_TC			M_PERFCTL_MT_EN(2)
#define M_PERFCTL_TCID(tcid)		((tcid)   << 22)
#define M_PERFCTL_WIDE			(1UL      << 30)
#define M_PERFCTL_MORE			(1UL      << 31)

#define M_COUNTER_OVERFLOW		(1UL      << 31)

#ifdef CONFIG_MIPS_MT_SMP
34
35
#define WHAT		(M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
#define vpe_id()	smp_processor_id()
36
#else
37
38
#define WHAT		0
#define vpe_id()	smp_processor_id()
39
#endif
40

41
42
43
44
#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
45
	unsigned int cpu = vpe_id();					\
46
47
48
49
50
51
52
53
54
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
55
	return 0;							\
56
57
58
59
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
60
	unsigned int cpu = vpe_id();					\
61
62
63
64
65
66
67
68
69
70
71
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
72
	return;								\
73
74
75
76
77
78
79
80
81
82
83
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 2)
__define_perf_accessors(perfcntr, 3, 2)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 2)
__define_perf_accessors(perfctrl, 3, 2)
84

85
struct op_mips_model op_model_mipsxx_ops;
86
87
88
89
90
91
92
93
94
95

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.  */

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
96
	unsigned int counters = op_model_mipsxx_ops.num_counters;
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
	int i;

	/* Compute the performance counter control word.  */
	/* For now count kernel and user mode */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
		                 M_PERFCTL_INTERRUPT_ENABLE;
		if (ctr[i].kernel)
			reg.control[i] |= M_PERFCTL_KERNEL;
		if (ctr[i].user)
			reg.control[i] |= M_PERFCTL_USER;
		if (ctr[i].exl)
			reg.control[i] |= M_PERFCTL_EXL;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.  */

static void mipsxx_cpu_setup (void *args)
{
124
	unsigned int counters = op_model_mipsxx_ops.num_counters;
125
126
127

	switch (counters) {
	case 4:
128
129
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
130
	case 3:
131
132
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
133
	case 2:
134
135
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
136
	case 1:
137
138
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
139
140
141
142
143
144
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
145
	unsigned int counters = op_model_mipsxx_ops.num_counters;
146
147
148

	switch (counters) {
	case 4:
149
		w_c0_perfctrl3(WHAT | reg.control[3]);
150
	case 3:
151
		w_c0_perfctrl2(WHAT | reg.control[2]);
152
	case 2:
153
		w_c0_perfctrl1(WHAT | reg.control[1]);
154
	case 1:
155
		w_c0_perfctrl0(WHAT | reg.control[0]);
156
157
158
159
160
161
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
162
	unsigned int counters = op_model_mipsxx_ops.num_counters;
163
164
165

	switch (counters) {
	case 4:
166
		w_c0_perfctrl3(0);
167
	case 3:
168
		w_c0_perfctrl2(0);
169
	case 2:
170
		w_c0_perfctrl1(0);
171
	case 1:
172
		w_c0_perfctrl0(0);
173
174
175
	}
}

176
static int mipsxx_perfcount_handler(void)
177
{
178
	unsigned int counters = op_model_mipsxx_ops.num_counters;
179
180
	unsigned int control;
	unsigned int counter;
181
	int handled = 0;
182
183
184
185

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	case n + 1:							\
186
187
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
188
189
		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
		    (counter & M_COUNTER_OVERFLOW)) {			\
190
			oprofile_add_sample(get_irq_regs(), n);		\
191
			w_c0_perfcntr ## n(reg.counter[n]);		\
192
			handled = 1;					\
193
194
195
196
197
198
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}
199
200

	return handled;
201
202
203
204
}

#define M_CONFIG1_PC	(1 << 4)

205
static inline int __n_counters(void)
206
207
208
{
	if (!(read_c0_config1() & M_CONFIG1_PC))
		return 0;
209
	if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
210
		return 1;
211
	if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
212
		return 2;
213
	if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
214
215
216
217
218
		return 3;

	return 4;
}

219
220
221
222
223
224
225
226
227
228
229
230
static inline int n_counters(void)
{
	int counters = __n_counters();

#ifndef CONFIG_SMP
	if (current_cpu_data.cputype == CPU_34K)
		return counters >> 1;
#endif

	return counters;
}

231
232
233
234
static inline void reset_counters(int counters)
{
	switch (counters) {
	case 4:
235
236
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
237
	case 3:
238
239
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
240
	case 2:
241
242
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
243
	case 1:
244
245
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
246
247
248
249
250
251
252
253
	}
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
254
255
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
256
		return -ENODEV;
257
	}
258
259
260

	reset_counters(counters);

261
	op_model_mipsxx_ops.num_counters = counters;
262
	switch (current_cpu_data.cputype) {
263
	case CPU_20KC:
264
		op_model_mipsxx_ops.cpu_type = "mips/20K";
265
266
		break;

267
	case CPU_24K:
268
		op_model_mipsxx_ops.cpu_type = "mips/24K";
269
270
		break;

271
	case CPU_25KF:
272
		op_model_mipsxx_ops.cpu_type = "mips/25K";
273
274
		break;

275
	case CPU_34K:
276
		op_model_mipsxx_ops.cpu_type = "mips/34K";
277
		break;
278
279

	case CPU_74K:
280
		op_model_mipsxx_ops.cpu_type = "mips/74K";
281
		break;
282

283
	case CPU_5KC:
284
		op_model_mipsxx_ops.cpu_type = "mips/5K";
285
286
		break;

Mark Mason's avatar
Mark Mason committed
287
288
	case CPU_SB1:
	case CPU_SB1A:
289
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
Mark Mason's avatar
Mark Mason committed
290
291
		break;

292
293
294
295
296
297
298
299
300
301
302
303
304
	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	perf_irq = mipsxx_perfcount_handler;

	return 0;
}

static void mipsxx_exit(void)
{
305
	reset_counters(op_model_mipsxx_ops.num_counters);
306
307
308
309

	perf_irq = null_perf_irq;
}

310
struct op_mips_model op_model_mipsxx_ops = {
311
312
313
314
315
316
317
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};