i7core_edac.c 55.4 KB
Newer Older
1 2 3 4 5 6
/* Intel i7 core/Nehalem Memory Controller kernel module
 *
 * This driver supports yhe memory controllers found on the Intel
 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
 * and Westmere-EP.
7 8 9 10
 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
11
 * Copyright (c) 2009-2010 by:
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
 *	 Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Forked and adapted from the i5400_edac driver
 *
 * Based on the following public Intel datasheets:
 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
 * Datasheet, Volume 2:
 *	http://download.intel.com/design/processor/datashts/320835.pdf
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
Randy Dunlap's avatar
Randy Dunlap committed
33
#include <linux/delay.h>
34 35
#include <linux/edac.h>
#include <linux/mmzone.h>
36
#include <linux/edac_mce.h>
37
#include <linux/smp.h>
38
#include <asm/processor.h>
39 40 41

#include "edac_core.h"

42 43 44 45 46
/* Static vars */
static LIST_HEAD(i7core_edac_list);
static DEFINE_MUTEX(i7core_edac_lock);
static int probed;

47 48 49 50 51 52 53 54 55
/*
 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
 * registers start at bus 255, and are not reported by BIOS.
 * We currently find devices with only 2 sockets. In order to support more QPI
 * Quick Path Interconnect, just increment this number.
 */
#define MAX_SOCKET_BUSES	2


56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
/*
 * Alter this version for the module when modifications are made
 */
#define I7CORE_REVISION    " Ver: 1.0.0 " __DATE__
#define EDAC_MOD_STR      "i7core_edac"

/*
 * Debug macros
 */
#define i7core_printk(level, fmt, arg...)			\
	edac_printk(level, "i7core", fmt, ##arg)

#define i7core_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

/*
 * i7core Memory Controller Registers
 */

75 76 77 78
	/* OFFSETS for Device 0 Function 0 */

#define MC_CFG_CONTROL	0x90

79 80 81 82 83 84
	/* OFFSETS for Device 3 Function 0 */

#define MC_CONTROL	0x48
#define MC_STATUS	0x4c
#define MC_MAX_DOD	0x64

85 86 87 88 89 90 91 92 93 94 95 96
/*
 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#define MC_TEST_ERR_RCV1	0x60
  #define DIMM2_COR_ERR(r)			((r) & 0x7fff)

#define MC_TEST_ERR_RCV0	0x64
  #define DIMM1_COR_ERR(r)			(((r) >> 16) & 0x7fff)
  #define DIMM0_COR_ERR(r)			((r) & 0x7fff)

97 98 99 100 101 102 103 104 105 106 107 108
/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
#define MC_COR_ECC_CNT_0	0x80
#define MC_COR_ECC_CNT_1	0x84
#define MC_COR_ECC_CNT_2	0x88
#define MC_COR_ECC_CNT_3	0x8c
#define MC_COR_ECC_CNT_4	0x90
#define MC_COR_ECC_CNT_5	0x94

#define DIMM_TOP_COR_ERR(r)			(((r) >> 16) & 0x7fff)
#define DIMM_BOT_COR_ERR(r)			((r) & 0x7fff)


109 110
	/* OFFSETS for Devices 4,5 and 6 Function 0 */

111 112 113 114 115 116
#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  #define THREE_DIMMS_PRESENT		(1 << 24)
  #define SINGLE_QUAD_RANK_PRESENT	(1 << 23)
  #define QUAD_RANK_PRESENT		(1 << 22)
  #define REGISTERED_DIMM		(1 << 15)

117 118 119 120
#define MC_CHANNEL_MAPPER	0x60
  #define RDLCH(r, ch)		((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  #define WRLCH(r, ch)		((((r) >> (ch * 6)) & 0x07) - 1)

121 122 123
#define MC_CHANNEL_RANK_PRESENT 0x7c
  #define RANK_PRESENT_MASK		0xffff

124
#define MC_CHANNEL_ADDR_MATCH	0xf0
125 126 127 128 129 130 131 132 133 134
#define MC_CHANNEL_ERROR_MASK	0xf8
#define MC_CHANNEL_ERROR_INJECT	0xfc
  #define INJECT_ADDR_PARITY	0x10
  #define INJECT_ECC		0x08
  #define MASK_CACHELINE	0x06
  #define MASK_FULL_CACHELINE	0x06
  #define MASK_MSB32_CACHELINE	0x04
  #define MASK_LSB32_CACHELINE	0x02
  #define NO_MASK_CACHELINE	0x00
  #define REPEAT_EN		0x01
135

136
	/* OFFSETS for Devices 4,5 and 6 Function 1 */
137

138 139 140 141 142 143 144
#define MC_DOD_CH_DIMM0		0x48
#define MC_DOD_CH_DIMM1		0x4c
#define MC_DOD_CH_DIMM2		0x50
  #define RANKOFFSET_MASK	((1 << 12) | (1 << 11) | (1 << 10))
  #define RANKOFFSET(x)		((x & RANKOFFSET_MASK) >> 10)
  #define DIMM_PRESENT_MASK	(1 << 9)
  #define DIMM_PRESENT(x)	(((x) & DIMM_PRESENT_MASK) >> 9)
145 146 147 148
  #define MC_DOD_NUMBANK_MASK		((1 << 8) | (1 << 7))
  #define MC_DOD_NUMBANK(x)		(((x) & MC_DOD_NUMBANK_MASK) >> 7)
  #define MC_DOD_NUMRANK_MASK		((1 << 6) | (1 << 5))
  #define MC_DOD_NUMRANK(x)		(((x) & MC_DOD_NUMRANK_MASK) >> 5)
149
  #define MC_DOD_NUMROW_MASK		((1 << 4) | (1 << 3) | (1 << 2))
150
  #define MC_DOD_NUMROW(x)		(((x) & MC_DOD_NUMROW_MASK) >> 2)
151 152
  #define MC_DOD_NUMCOL_MASK		3
  #define MC_DOD_NUMCOL(x)		((x) & MC_DOD_NUMCOL_MASK)
153

154 155
#define MC_RANK_PRESENT		0x7c

156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178
#define MC_SAG_CH_0	0x80
#define MC_SAG_CH_1	0x84
#define MC_SAG_CH_2	0x88
#define MC_SAG_CH_3	0x8c
#define MC_SAG_CH_4	0x90
#define MC_SAG_CH_5	0x94
#define MC_SAG_CH_6	0x98
#define MC_SAG_CH_7	0x9c

#define MC_RIR_LIMIT_CH_0	0x40
#define MC_RIR_LIMIT_CH_1	0x44
#define MC_RIR_LIMIT_CH_2	0x48
#define MC_RIR_LIMIT_CH_3	0x4C
#define MC_RIR_LIMIT_CH_4	0x50
#define MC_RIR_LIMIT_CH_5	0x54
#define MC_RIR_LIMIT_CH_6	0x58
#define MC_RIR_LIMIT_CH_7	0x5C
#define MC_RIR_LIMIT_MASK	((1 << 10) - 1)

#define MC_RIR_WAY_CH		0x80
  #define MC_RIR_WAY_OFFSET_MASK	(((1 << 14) - 1) & ~0x7)
  #define MC_RIR_WAY_RANK_MASK		0x7

179 180 181 182 183
/*
 * i7core structs
 */

#define NUM_CHANS 3
184 185 186
#define MAX_DIMMS 3		/* Max DIMMS per channel */
#define MAX_MCR_FUNC  4
#define MAX_CHAN_FUNC 3
187 188 189 190 191

struct i7core_info {
	u32	mc_control;
	u32	mc_status;
	u32	max_dod;
192
	u32	ch_map;
193 194
};

195 196 197 198 199 200 201 202 203 204 205 206

struct i7core_inject {
	int	enable;

	u32	section;
	u32	type;
	u32	eccmask;

	/* Error address mask */
	int channel, dimm, rank, bank, page, col;
};

207
struct i7core_channel {
208 209
	u32		ranks;
	u32		dimms;
210 211
};

212
struct pci_id_descr {
213 214 215
	int			dev;
	int			func;
	int 			dev_id;
216
	int			optional;
217 218
};

219
struct pci_id_table {
220 221
	const struct pci_id_descr	*descr;
	int				n_devs;
222 223
};

224 225 226 227
struct i7core_dev {
	struct list_head	list;
	u8			socket;
	struct pci_dev		**pdev;
228
	int			n_devs;
229 230 231
	struct mem_ctl_info	*mci;
};

232
struct i7core_pvt {
233 234 235 236 237
	struct pci_dev	*pci_noncore;
	struct pci_dev	*pci_mcr[MAX_MCR_FUNC + 1];
	struct pci_dev	*pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];

	struct i7core_dev *i7core_dev;
238

239
	struct i7core_info	info;
240
	struct i7core_inject	inject;
241
	struct i7core_channel	channel[NUM_CHANS];
242

243
	int		channels; /* Number of active channels */
244

245 246
	int		ce_count_available;
	int 		csrow_map[NUM_CHANS][MAX_DIMMS];
247 248

			/* ECC corrected errors counts per udimm */
249 250
	unsigned long	udimm_ce_count[MAX_DIMMS];
	int		udimm_last_ce_count[MAX_DIMMS];
251
			/* ECC corrected errors counts per rdimm */
252 253
	unsigned long	rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
	int		rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
254

255
	unsigned int	is_registered;
256

257 258
	/* mcelog glue */
	struct edac_mce		edac_mce;
259 260

	/* Fifo double buffers */
261
	struct mce		mce_entry[MCE_LOG_LEN];
262 263 264 265 266 267 268
	struct mce		mce_outentry[MCE_LOG_LEN];

	/* Fifo in/out counters */
	unsigned		mce_in, mce_out;

	/* Count indicator to show errors not got */
	unsigned		mce_overrun;
269 270 271

	/* Struct to control EDAC polling */
	struct edac_pci_ctl_info *i7core_pci;
272 273
};

274 275 276 277 278
#define PCI_DESCR(device, function, device_id)	\
	.dev = (device),			\
	.func = (function),			\
	.dev_id = (device_id)

279
static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
280 281 282
		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
283 284
			/* Exists only for RDIMM */
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1  },
285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
304 305 306 307 308 309 310 311

		/* Generic Non-core registers */
	/*
	 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
	 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
	 * the probing code needs to test for the other address in case of
	 * failure of this one
	 */
312
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE)  },
313

314
};
315

316
static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
317 318 319 320 321 322 323 324 325
	{ PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR)         },
	{ PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD)      },
	{ PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST)     },

	{ PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
	{ PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
	{ PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
	{ PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC)   },

326 327 328 329
	{ PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
	{ PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
	{ PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
	{ PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC)   },
330

331 332 333 334
	/*
	 * This is the PCI device has an alternate address on some
	 * processors like Core i7 860
	 */
335 336 337
	{ PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE)     },
};

338
static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368
		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2)  },
			/* Exists only for RDIMM */
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1  },
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2)   },

		/* Generic Non-core registers */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2)  },

};

369 370
#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
static const struct pci_id_table pci_dev_table[] = {
371 372 373 374 375
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
	PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
};

376 377 378 379
/*
 *	pci_device_id	table for which devices we are looking for
 */
static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
380
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
381
	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
382 383 384
	{0,}			/* 0 terminated list. */
};

385 386 387 388 389
/****************************************************************************
			Anciliary status routines
 ****************************************************************************/

	/* MC_CONTROL bits */
390 391
#define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
#define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
392 393

	/* MC_STATUS bits */
394
#define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 4))
395
#define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
396 397

	/* MC_MAX_DOD read functions */
398
static inline int numdimms(u32 dimms)
399
{
400
	return (dimms & 0x3) + 1;
401 402
}

403
static inline int numrank(u32 rank)
404 405 406
{
	static int ranks[4] = { 1, 2, 4, -EINVAL };

407
	return ranks[rank & 0x3];
408 409
}

410
static inline int numbank(u32 bank)
411 412 413
{
	static int banks[4] = { 4, 8, 16, -EINVAL };

414
	return banks[bank & 0x3];
415 416
}

417
static inline int numrow(u32 row)
418 419 420 421 422 423
{
	static int rows[8] = {
		1 << 12, 1 << 13, 1 << 14, 1 << 15,
		1 << 16, -EINVAL, -EINVAL, -EINVAL,
	};

424
	return rows[row & 0x7];
425 426
}

427
static inline int numcol(u32 col)
428 429 430 431
{
	static int cols[8] = {
		1 << 10, 1 << 11, 1 << 12, -EINVAL,
	};
432
	return cols[col & 0x3];
433 434
}

435
static struct i7core_dev *get_i7core_dev(u8 socket)
436 437 438 439 440 441 442 443 444 445 446
{
	struct i7core_dev *i7core_dev;

	list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
		if (i7core_dev->socket == socket)
			return i7core_dev;
	}

	return NULL;
}

447 448 449
/****************************************************************************
			Memory check routines
 ****************************************************************************/
450 451
static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
					  unsigned func)
452
{
453
	struct i7core_dev *i7core_dev = get_i7core_dev(socket);
454 455
	int i;

456 457 458
	if (!i7core_dev)
		return NULL;

459
	for (i = 0; i < i7core_dev->n_devs; i++) {
460
		if (!i7core_dev->pdev[i])
461 462
			continue;

463 464 465
		if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
		    PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
			return i7core_dev->pdev[i];
466 467 468
		}
	}

469 470 471
	return NULL;
}

472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488
/**
 * i7core_get_active_channels() - gets the number of channels and csrows
 * @socket:	Quick Path Interconnect socket
 * @channels:	Number of channels that will be returned
 * @csrows:	Number of csrows found
 *
 * Since EDAC core needs to know in advance the number of available channels
 * and csrows, in order to allocate memory for csrows/channels, it is needed
 * to run two similar steps. At the first step, implemented on this function,
 * it checks the number of csrows/channels present at one socket.
 * this is used in order to properly allocate the size of mci components.
 *
 * It should be noticed that none of the current available datasheets explain
 * or even mention how csrows are seen by the memory controller. So, we need
 * to add a fake description for csrows.
 * So, this driver is attributing one DIMM memory for one csrow.
 */
489
static int i7core_get_active_channels(const u8 socket, unsigned *channels,
490
				      unsigned *csrows)
491 492 493 494 495 496 497 498
{
	struct pci_dev *pdev = NULL;
	int i, j;
	u32 status, control;

	*channels = 0;
	*csrows = 0;

499
	pdev = get_pdev_slot_func(socket, 3, 0);
500
	if (!pdev) {
501 502
		i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
			      socket);
503
		return -ENODEV;
504
	}
505 506 507 508 509 510

	/* Device 3 function 0 reads */
	pci_read_config_dword(pdev, MC_STATUS, &status);
	pci_read_config_dword(pdev, MC_CONTROL, &control);

	for (i = 0; i < NUM_CHANS; i++) {
511
		u32 dimm_dod[3];
512 513 514 515 516
		/* Check if the channel is active */
		if (!(control & (1 << (8 + i))))
			continue;

		/* Check if the channel is disabled */
517
		if (status & (1 << i))
518 519
			continue;

520
		pdev = get_pdev_slot_func(socket, i + 4, 1);
521
		if (!pdev) {
522 523 524
			i7core_printk(KERN_ERR, "Couldn't find socket %d "
						"fn %d.%d!!!\n",
						socket, i + 4, 1);
525 526 527 528 529 530 531 532 533 534
			return -ENODEV;
		}
		/* Devices 4-6 function 1 */
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM2, &dimm_dod[2]);

535
		(*channels)++;
536 537 538 539 540 541

		for (j = 0; j < 3; j++) {
			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;
			(*csrows)++;
		}
542 543
	}

544
	debugf0("Number of active channels on socket %d: %d\n",
545
		socket, *channels);
546

547 548 549
	return 0;
}

550
static int get_dimm_config(const struct mem_ctl_info *mci, int *csrow)
551 552
{
	struct i7core_pvt *pvt = mci->pvt_info;
553
	struct csrow_info *csr;
554
	struct pci_dev *pdev;
555
	int i, j;
556
	unsigned long last_page = 0;
557
	enum edac_type mode;
558
	enum mem_type mtype;
559

560
	/* Get data from the MC register, function 0 */
561
	pdev = pvt->pci_mcr[0];
562
	if (!pdev)
563 564
		return -ENODEV;

565
	/* Device 3 function 0 reads */
566 567 568 569
	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
570

571
	debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
572
		pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
573
		pvt->info.max_dod, pvt->info.ch_map);
574

575
	if (ECC_ENABLED(pvt)) {
576
		debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
577 578 579 580 581
		if (ECCx8(pvt))
			mode = EDAC_S8ECD8ED;
		else
			mode = EDAC_S4ECD4ED;
	} else {
582
		debugf0("ECC disabled\n");
583 584
		mode = EDAC_NONE;
	}
585 586

	/* FIXME: need to handle the error codes */
587 588
	debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
		"x%x x 0x%x\n",
589 590
		numdimms(pvt->info.max_dod),
		numrank(pvt->info.max_dod >> 2),
591
		numbank(pvt->info.max_dod >> 4),
592 593
		numrow(pvt->info.max_dod >> 6),
		numcol(pvt->info.max_dod >> 9));
594

595
	for (i = 0; i < NUM_CHANS; i++) {
596
		u32 data, dimm_dod[3], value[8];
597

598 599 600
		if (!pvt->pci_ch[i][0])
			continue;

601 602 603 604 605 606 607 608 609
		if (!CH_ACTIVE(pvt, i)) {
			debugf0("Channel %i is not active\n", i);
			continue;
		}
		if (CH_DISABLED(pvt, i)) {
			debugf0("Channel %i is disabled\n", i);
			continue;
		}

610
		/* Devices 4-6 function 0 */
611
		pci_read_config_dword(pvt->pci_ch[i][0],
612 613
				MC_CHANNEL_DIMM_INIT_PARAMS, &data);

614
		pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
615
						4 : 2;
616

617 618
		if (data & REGISTERED_DIMM)
			mtype = MEM_RDDR3;
619
		else
620 621
			mtype = MEM_DDR3;
#if 0
622 623 624 625 626 627
		if (data & THREE_DIMMS_PRESENT)
			pvt->channel[i].dimms = 3;
		else if (data & SINGLE_QUAD_RANK_PRESENT)
			pvt->channel[i].dimms = 1;
		else
			pvt->channel[i].dimms = 2;
628 629 630
#endif

		/* Devices 4-6 function 1 */
631
		pci_read_config_dword(pvt->pci_ch[i][1],
632
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
633
		pci_read_config_dword(pvt->pci_ch[i][1],
634
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
635
		pci_read_config_dword(pvt->pci_ch[i][1],
636
				MC_DOD_CH_DIMM2, &dimm_dod[2]);
637

638
		debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
639
			"%d ranks, %cDIMMs\n",
640 641 642
			i,
			RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
			data,
643
			pvt->channel[i].ranks,
644
			(data & REGISTERED_DIMM) ? 'R' : 'U');
645 646 647

		for (j = 0; j < 3; j++) {
			u32 banks, ranks, rows, cols;
648
			u32 size, npages;
649 650 651 652 653 654 655 656 657

			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;

			banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
			ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
			rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
			cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));

658 659 660
			/* DDR3 has 8 I/O banks */
			size = (rows * cols * banks * ranks) >> (20 - 3);

661
			pvt->channel[i].dimms++;
662

663 664 665
			debugf0("\tdimm %d %d Mb offset: %x, "
				"bank: %d, rank: %d, row: %#x, col: %#x\n",
				j, size,
666 667 668
				RANKOFFSET(dimm_dod[j]),
				banks, ranks, rows, cols);

669
			npages = MiB_TO_PAGES(size);
670

671
			csr = &mci->csrows[*csrow];
672 673 674 675 676
			csr->first_page = last_page + 1;
			last_page += npages;
			csr->last_page = last_page;
			csr->nr_pages = npages;

677
			csr->page_mask = 0;
678
			csr->grain = 8;
679
			csr->csrow_idx = *csrow;
680 681 682 683
			csr->nr_channels = 1;

			csr->channels[0].chan_idx = i;
			csr->channels[0].ce_count = 0;
684

685
			pvt->csrow_map[i][j] = *csrow;
686

687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703
			switch (banks) {
			case 4:
				csr->dtype = DEV_X4;
				break;
			case 8:
				csr->dtype = DEV_X8;
				break;
			case 16:
				csr->dtype = DEV_X16;
				break;
			default:
				csr->dtype = DEV_UNKNOWN;
			}

			csr->edac_mode = mode;
			csr->mtype = mtype;

704
			(*csrow)++;
705
		}
706

707 708 709 710 711 712 713 714
		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
		pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
		pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
		pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
		pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
715
		debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
716
		for (j = 0; j < 8; j++)
717
			debugf1("\t\t%#x\t%#x\t%#x\n",
718 719 720
				(value[j] >> 27) & 0x1,
				(value[j] >> 24) & 0x7,
				(value[j] && ((1 << 24) - 1)));
721 722
	}

723 724 725
	return 0;
}

726 727 728 729 730 731 732 733 734 735 736
/****************************************************************************
			Error insertion routines
 ****************************************************************************/

/* The i7core has independent error injection features per channel.
   However, to have a simpler code, we don't allow enabling error injection
   on more than one channel.
   Also, since a change at an inject parameter will be applied only at enable,
   we're disabling error injection on all write calls to the sysfs nodes that
   controls the error code injection.
 */
737
static int disable_inject(const struct mem_ctl_info *mci)
738 739 740 741 742
{
	struct i7core_pvt *pvt = mci->pvt_info;

	pvt->inject.enable = 0;

743
	if (!pvt->pci_ch[pvt->inject.channel][0])
744 745
		return -ENODEV;

746
	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
747
				MC_CHANNEL_ERROR_INJECT, 0);
748 749

	return 0;
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766
}

/*
 * i7core inject inject.section
 *
 *	accept and store error injection inject.section value
 *	bit 0 - refers to the lower 32-byte half cacheline
 *	bit 1 - refers to the upper 32-byte half cacheline
 */
static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
					   const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
767
		disable_inject(mci);
768 769 770

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 3))
771
		return -EIO;
772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799

	pvt->inject.section = (u32) value;
	return count;
}

static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.section);
}

/*
 * i7core inject.type
 *
 *	accept and store error injection inject.section value
 *	bit 0 - repeat enable - Enable error repetition
 *	bit 1 - inject ECC error
 *	bit 2 - inject parity error
 */
static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
800
		disable_inject(mci);
801 802 803

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 7))
804
		return -EIO;
805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834

	pvt->inject.type = (u32) value;
	return count;
}

static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.type);
}

/*
 * i7core_inject_inject.eccmask_store
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
835
		disable_inject(mci);
836 837 838

	rc = strict_strtoul(data, 10, &value);
	if (rc < 0)
839
		return -EIO;
840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862

	pvt->inject.eccmask = (u32) value;
	return count;
}

static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
}

/*
 * i7core_addrmatch
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */

863 864 865 866 867
#define DECLARE_ADDR_MATCH(param, limit)			\
static ssize_t i7core_inject_store_##param(			\
		struct mem_ctl_info *mci,			\
		const char *data, size_t count)			\
{								\
868
	struct i7core_pvt *pvt;					\
869 870 871
	long value;						\
	int rc;							\
								\
872 873 874
	debugf1("%s()\n", __func__);				\
	pvt = mci->pvt_info;					\
								\
875 876 877
	if (pvt->inject.enable)					\
		disable_inject(mci);				\
								\
878
	if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894
		value = -1;					\
	else {							\
		rc = strict_strtoul(data, 10, &value);		\
		if ((rc < 0) || (value >= limit))		\
			return -EIO;				\
	}							\
								\
	pvt->inject.param = value;				\
								\
	return count;						\
}								\
								\
static ssize_t i7core_inject_show_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
895 896 897 898
	struct i7core_pvt *pvt;					\
								\
	pvt = mci->pvt_info;					\
	debugf1("%s() pvt=%p\n", __func__, pvt);		\
899 900 901 902
	if (pvt->inject.param < 0)				\
		return sprintf(data, "any\n");			\
	else							\
		return sprintf(data, "%d\n", pvt->inject.param);\
903 904
}

905 906 907 908 909 910 911 912 913
#define ATTR_ADDR_MATCH(param)					\
	{							\
		.attr = {					\
			.name = #param,				\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_inject_show_##param,		\
		.store = i7core_inject_store_##param,		\
	}
914

915 916 917 918 919 920
DECLARE_ADDR_MATCH(channel, 3);
DECLARE_ADDR_MATCH(dimm, 3);
DECLARE_ADDR_MATCH(rank, 4);
DECLARE_ADDR_MATCH(bank, 32);
DECLARE_ADDR_MATCH(page, 0x10000);
DECLARE_ADDR_MATCH(col, 0x4000);
921

922
static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
923 924 925 926
{
	u32 read;
	int count;

927 928 929 930
	debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val);

931 932
	for (count = 0; count < 10; count++) {
		if (count)
933
			msleep(100);
934 935 936 937 938 939 940
		pci_write_config_dword(dev, where, val);
		pci_read_config_dword(dev, where, &read);

		if (read == val)
			return 0;
	}

941 942 943 944
	i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
		"write=%08x. Read=%08x\n",
		dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
		where, val, read);
945 946 947 948

	return -EINVAL;
}

949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975
/*
 * This routine prepares the Memory Controller for error injection.
 * The error will be injected when some process tries to write to the
 * memory that matches the given criteria.
 * The criteria can be set in terms of a mask where dimm, rank, bank, page
 * and col can be specified.
 * A -1 value for any of the mask items will make the MCU to ignore
 * that matching criteria for error injection.
 *
 * It should be noticed that the error will only happen after a write operation
 * on a memory that matches the condition. if REPEAT_EN is not enabled at
 * inject mask, then it will produce just one error. Otherwise, it will repeat
 * until the injectmask would be cleaned.
 *
 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 *    is reliable enough to check if the MC is using the
 *    three channels. However, this is not clear at the datasheet.
 */
static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
				       const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 injectmask;
	u64 mask = 0;
	int  rc;
	long enable;

976
	if (!pvt->pci_ch[pvt->inject.channel][0])
977 978
		return 0;

979 980 981 982 983 984 985 986 987 988 989 990 991
	rc = strict_strtoul(data, 10, &enable);
	if ((rc < 0))
		return 0;

	if (enable) {
		pvt->inject.enable = 1;
	} else {
		disable_inject(mci);
		return count;
	}

	/* Sets pvt->inject.dimm mask */
	if (pvt->inject.dimm < 0)
992
		mask |= 1LL << 41;
993
	else {
994
		if (pvt->channel[pvt->inject.channel].dimms > 2)
995
			mask |= (pvt->inject.dimm & 0x3LL) << 35;
996
		else
997
			mask |= (pvt->inject.dimm & 0x1LL) << 36;
998 999 1000 1001
	}

	/* Sets pvt->inject.rank mask */
	if (pvt->inject.rank < 0)
1002
		mask |= 1LL << 40;
1003
	else {
1004
		if (pvt->channel[pvt->inject.channel].dimms > 2)
1005
			mask |= (pvt->inject.rank & 0x1LL) << 34;
1006
		else
1007
			mask |= (pvt->inject.rank & 0x3LL) << 34;
1008 1009 1010 1011
	}

	/* Sets pvt->inject.bank mask */
	if (pvt->inject.bank < 0)
1012
		mask |= 1LL << 39;
1013
	else
1014
		mask |= (pvt->inject.bank & 0x15LL) << 30;
1015 1016 1017

	/* Sets pvt->inject.page mask */
	if (pvt->inject.page < 0)
1018
		mask |= 1LL << 38;
1019
	else
1020
		mask |= (pvt->inject.page & 0xffff) << 14;
1021 1022 1023

	/* Sets pvt->inject.column mask */
	if (pvt->inject.col < 0)
1024
		mask |= 1LL << 37;
1025
	else
1026
		mask |= (pvt->inject.col & 0x3fff);
1027

1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039
	/*
	 * bit    0: REPEAT_EN
	 * bits 1-2: MASK_HALF_CACHELINE
	 * bit    3: INJECT_ECC
	 * bit    4: INJECT_ADDR_PARITY
	 */

	injectmask = (pvt->inject.type & 1) |
		     (pvt->inject.section & 0x3) << 1 |
		     (pvt->inject.type & 0x6) << (3 - 1);

	/* Unlock writes to registers - this register is write only */
1040
	pci_write_config_dword(pvt->pci_noncore,
1041
			       MC_CFG_CONTROL, 0x2);
1042

1043
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1044
			       MC_CHANNEL_ADDR_MATCH, mask);
1045
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1046 1047
			       MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);

1048
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1049 1050
			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);

1051
	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1052
			       MC_CHANNEL_ERROR_INJECT, injectmask);
1053

1054
	/*
1055 1056 1057
	 * This is something undocumented, based on my tests
	 * Without writing 8 to this register, errors aren't injected. Not sure
	 * why.
1058
	 */
1059
	pci_write_config_dword(pvt->pci_noncore,
1060
			       MC_CFG_CONTROL, 8);
1061

1062 1063
	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
		" inject 0x%08x\n",
1064 1065
		mask, pvt->inject.eccmask, injectmask);

1066

1067 1068 1069 1070 1071 1072 1073
	return count;
}

static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
					char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
1074 1075
	u32 injectmask;

1076 1077 1078
	if (!pvt->pci_ch[pvt->inject.channel][0])
		return 0;

1079
	pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1080
			       MC_CHANNEL_ERROR_INJECT, &injectmask);
1081 1082 1083 1084 1085 1086

	debugf0("Inject error read: 0x%018x\n", injectmask);

	if (injectmask & 0x0c)
		pvt->inject.enable = 1;

1087 1088 1089
	return sprintf(data, "%d\n", pvt->inject.enable);
}

1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102
#define DECLARE_COUNTER(param)					\
static ssize_t i7core_show_counter_##param(			\
		struct mem_ctl_info *mci,			\
		char *data)					\
{								\
	struct i7core_pvt *pvt = mci->pvt_info;			\
								\
	debugf1("%s() \n", __func__);				\
	if (!pvt->ce_count_available || (pvt->is_registered))	\
		return sprintf(data, "data unavailable\n");	\
	return sprintf(data, "%lu\n",				\
			pvt->udimm_ce_count[param]);		\
}
1103

1104 1105 1106 1107 1108 1109 1110
#define ATTR_COUNTER(param)					\
	{							\
		.attr = {					\
			.name = __stringify(udimm##param),	\
			.mode = (S_IRUGO | S_IWUSR)		\
		},						\
		.show  = i7core_show_counter_##param		\
1111
	}
1112

1113 1114 1115
DECLARE_COUNTER(0);
DECLARE_COUNTER(1);
DECLARE_COUNTER(2);
1116

1117 1118 1119
/*
 * Sysfs struct
 */
1120

1121
static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
1122 1123 1124 1125 1126 1127
	ATTR_ADDR_MATCH(channel),
	ATTR_ADDR_MATCH(dimm),
	ATTR_ADDR_MATCH(rank),
	ATTR_ADDR_MATCH(bank),
	ATTR_ADDR_MATCH(page),
	ATTR_ADDR_MATCH(col),
1128
	{ } /* End of list */
1129 1130
};

1131
static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
1132 1133 1134 1135
	.name  = "inject_addrmatch",
	.mcidev_attr = i7core_addrmatch_attrs,
};

1136
static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
1137 1138 1139
	ATTR_COUNTER(0),
	ATTR_COUNTER(1),
	ATTR_COUNTER(2),
1140
	{ .attr = { .name = NULL } }
1141 1142
};

1143
static const struct mcidev_sysfs_group i7core_udimm_counters = {
1144 1145 1146 1147
	.name  = "all_channel_counts",
	.mcidev_attr = i7core_udimm_counters_attrs,
};

1148
static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
1171
		.grp = &i7core_inject_addrmatch,
1172 1173 1174 1175 1176 1177 1178 1179
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	},
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217
	{ }	/* End of list */
};

static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
	{
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
		.grp = &i7core_inject_addrmatch,
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
	}, {
		.grp = &i7core_udimm_counters,
	},
	{ }	/* End of list */
1218 1219
};

1220 1221 1222 1223 1224 1225 1226 1227
/****************************************************************************
	Device initialization routines: put/get, init/exit
 ****************************************************************************/

/*
 *	i7core_put_devices	'put' all the devices that we have
 *				reserved via 'get'
 */
1228
static void i7core_put_devices(struct i7core_dev *i7core_dev)
1229
{
1230
	int i;
1231

1232
	debugf0(__FILE__ ": %s()\n", __func__);
1233
	for (i = 0; i < i7core_dev->n_devs; i++) {
1234 1235 1236 1237 1238 1239 1240 1241
		struct pci_dev *pdev = i7core_dev->pdev[i];
		if (!pdev)
			continue;
		debugf0("Removing dev %02x:%02x.%d\n",
			pdev->bus->number,
			PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
		pci_dev_put(pdev);
	}
1242 1243
	kfree(i7core_dev->pdev);
}
1244

1245 1246
static void i7core_put_all_devices(void)
{
1247
	struct i7core_dev *i7core_dev, *tmp;
1248

1249
	list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
1250
		i7core_put_devices(i7core_dev);
1251 1252 1253
		list_del(&i7core_dev->list);
		kfree(i7core_dev);
	}
1254 1255
}

1256
static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
1257 1258 1259 1260 1261 1262 1263 1264
{
	struct pci_dev *pdev = NULL;
	int i;
	/*
	 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
	 * aren't announced by acpi. So, we need to use a legacy scan probing
	 * to detect them
	 */
1265 1266 1267 1268 1269 1270
	while (table && table->descr) {
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
		if (unlikely(!pdev)) {
			for (i = 0; i < MAX_SOCKET_BUSES; i++)
				pcibios_scan_specific_bus(255-i);
		}
1271
		pci_dev_put(pdev);
1272
		table++;
1273 1274 1275
	}
}

1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292
static unsigned i7core_pci_lastbus(void)
{
	int last_bus = 0, bus;
	struct pci_bus *b = NULL;

	while ((b = pci_find_next_bus(b)) != NULL) {
		bus = b->number;
		debugf0("Found bus %d\n", bus);
		if (bus > last_bus)
			last_bus = bus;
	}

	debugf0("Last bus %d\n", last_bus);

	return last_bus;
}

1293 1294 1295 1296 1297 1298
/*
 *	i7core_get_devices	Find and perform 'get' operation on the MCH's
 *			device/functions we want to reference for this driver
 *
 *			Need to 'get' device 16 func 1 and func 2
 */