hpt366.c 45.1 KB
Newer Older
Linus Torvalds's avatar
Linus Torvalds committed
1
/*
2
 * linux/drivers/ide/pci/hpt366.c		Version 1.24	Dec 8, 2007
Linus Torvalds's avatar
Linus Torvalds committed
3
4
5
6
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
7
 * Portions Copyright (C) 2007		Bartlomiej Zolnierkiewicz
8
 * Portions Copyright (C) 2005-2007	MontaVista Software, Inc.
Linus Torvalds's avatar
Linus Torvalds committed
9
10
11
12
13
14
 *
 * Thanks to HighPoint Technologies for their assistance, and hardware.
 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
 * donation of an ABit BP6 mainboard, processor, and memory acellerated
 * development and support.
 *
15
 *
16
17
18
19
20
 * HighPoint has its own drivers (open source except for the RAID part)
 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
 * This may be useful to anyone wanting to work on this driver, however  do not
 * trust  them too much since the code tends to become less and less meaningful
 * as the time passes... :-/
21
 *
Linus Torvalds's avatar
Linus Torvalds committed
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
 * Note that final HPT370 support was done by force extraction of GPL.
 *
 * - add function for getting/setting power status of drive
 * - the HPT370's state machine can get confused. reset it before each dma 
 *   xfer to prevent that from happening.
 * - reset state engine whenever we get an error.
 * - check for busmaster state at end of dma. 
 * - use new highpoint timings.
 * - detect bus speed using highpoint register.
 * - use pll if we don't have a clock table. added a 66MHz table that's
 *   just 2x the 33MHz table.
 * - removed turnaround. NOTE: we never want to switch between pll and
 *   pci clocks as the chip can glitch in those cases. the highpoint
 *   approved workaround slows everything down too much to be useful. in
 *   addition, we would have to serialize access to each chip.
 * 	Adrian Sun <a.sun@sun.com>
 *
 * add drive timings for 66MHz PCI bus,
 * fix ATA Cable signal detection, fix incorrect /proc info
 * add /proc display for per-drive PIO/DMA/UDMA mode and
 * per-channel ATA-33/66 Cable detect.
 * 	Duncan Laurie <void@sun.com>
 *
 * fixup /proc output for multiple controllers
 *	Tim Hockin <thockin@sun.com>
 *
 * On hpt366: 
 * Reset the hpt366 on error, reset on dma
 * Fix disabling Fast Interrupt hpt366.
 * 	Mike Waychison <crlf@sun.com>
 *
 * Added support for 372N clocking and clock switching. The 372N needs
 * different clocks on read/write. This requires overloading rw_disk and
 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
 * keeping me sane. 
 *		Alan Cox <alan@redhat.com>
 *
59
60
61
62
63
 * - fix the clock turnaround code: it was writing to the wrong ports when
 *   called for the secondary channel, caching the current clock mode per-
 *   channel caused the cached register value to get out of sync with the
 *   actual one, the channels weren't serialized, the turnaround shouldn't
 *   be done on 66 MHz PCI bus
Sergei Shtylyov's avatar
Sergei Shtylyov committed
64
65
66
67
 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
 *   does not allow for this speed anyway
 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
 *   their primary channel is kind of virtual, it isn't tied to any pins)
68
69
70
 * - fix/remove bad/unused timing tables and use one set of tables for the whole
 *   HPT37x chip family; save space by introducing the separate transfer mode
 *   table in which the mode lookup is done
71
 * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
72
73
 *   the wrong PCI frequency since DPLL has already been calibrated by BIOS;
 *   read it only from the function 0 of HPT374 chips
74
75
 * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
 *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
76
77
 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
 *   they tamper with its fields
Sergei Shtylyov's avatar
Sergei Shtylyov committed
78
79
 * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
 *   since they may tamper with its fields
80
81
 * - prefix the driver startup messages with the real chip name
 * - claim the extra 240 bytes of I/O space for all chips
82
 * - optimize the UltraDMA filtering and the drive list lookup code
83
 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov's avatar
Sergei Shtylyov committed
84
85
86
87
 * - cache offset of the channel's misc. control registers (MCRs) being used
 *   throughout the driver
 * - only touch the relevant MCR when detecting the cable type on HPT374's
 *   function 1
88
 * - rename all the register related variables consistently
Sergei Shtylyov's avatar
Sergei Shtylyov committed
89
90
91
92
93
94
95
 * - move all the interrupt twiddling code from the speedproc handlers into
 *   init_hwif_hpt366(), also grouping all the DMA related code together there
 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
 *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
 *   when setting an UltraDMA mode
 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
 *   the best possible one
96
 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov's avatar
Sergei Shtylyov committed
97
98
99
100
101
102
103
 * - switch to using the enumeration type to differ between the numerous chip
 *   variants, matching PCI device/revision ID with the chip type early, at the
 *   init_setup stage
 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
 *   stop duplicating it for each channel by storing the pointer in the pci_dev
 *   structure: first, at the init_setup stage, point it to a static "template"
 *   with only the chip type and its specific base DPLL frequency, the highest
104
105
106
 *   UltraDMA mode, and the chip settings table pointer filled,  then, at the
 *   init_chipset stage, allocate per-chip instance  and fill it with the rest
 *   of the necessary information
Sergei Shtylyov's avatar
Sergei Shtylyov committed
107
108
109
110
 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 *   frequency
 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
111
112
 *   anything  newer than HPT370/A (except HPT374 that is not capable of this
 *   mode according to the manual)
113
114
 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
115
116
 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 *   the register setting lists into the table indexed by the clock selected
117
 * - set the correct hwif->ultra_mask for each individual chip
118
 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyov's avatar
Sergei Shtylyov committed
119
 *	Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds's avatar
Linus Torvalds committed
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>

#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>

/* various tuning parameters */
#define HPT_RESET_STATE_ENGINE
143
144
#undef	HPT_DELAY_INTERRUPT
#define HPT_SERIALIZE_IO	0
Linus Torvalds's avatar
Linus Torvalds committed
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188

static const char *quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static const char *bad_ata100_5[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
189
	"MAXTOR STM3320620A",
Linus Torvalds's avatar
Linus Torvalds committed
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
static u8 xfer_speeds[] = {
	XFER_UDMA_6,
	XFER_UDMA_5,
	XFER_UDMA_4,
	XFER_UDMA_3,
	XFER_UDMA_2,
	XFER_UDMA_1,
	XFER_UDMA_0,

	XFER_MW_DMA_2,
	XFER_MW_DMA_1,
	XFER_MW_DMA_0,

	XFER_PIO_4,
	XFER_PIO_3,
	XFER_PIO_2,
	XFER_PIO_1,
	XFER_PIO_0
Linus Torvalds's avatar
Linus Torvalds committed
227
228
};

229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
/* Key for bus clock timings
 * 36x   37x
 * bits  bits
 * 0:3	 0:3	data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *		cycles = value + 1
 * 4:7	 4:8	data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *		cycles = value + 1
 * 8:11  9:12	cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *		register access.
 * 12:15 13:17	cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *		register access.
 * 16:18 18:20	udma_cycle_time. Clock cycles for UDMA xfer.
 * -	 21	CLK frequency: 0=ATA clock, 1=dual ATA clock.
 * 19:21 22:24	pre_high_time. Time to initialize the 1st cycle for PIO and
 *		MW DMA xfer.
 * 22:24 25:27	cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 *		task file register access.
 * 28	 28	UDMA enable.
 * 29	 29	DMA  enable.
 * 30	 30	PIO MST enable. If set, the chip is in bus master mode during
 *		PIO xfer.
 * 31	 31	FIFO enable.
Linus Torvalds's avatar
Linus Torvalds committed
251
252
 */

253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
static u32 forty_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x900fd943,
	/* XFER_UDMA_5 */	0x900fd943,
	/* XFER_UDMA_4 */	0x900fd943,
	/* XFER_UDMA_3 */	0x900ad943,
	/* XFER_UDMA_2 */	0x900bd943,
	/* XFER_UDMA_1 */	0x9008d943,
	/* XFER_UDMA_0 */	0x9008d943,

	/* XFER_MW_DMA_2 */	0xa008d943,
	/* XFER_MW_DMA_1 */	0xa010d955,
	/* XFER_MW_DMA_0 */	0xa010d9fc,

	/* XFER_PIO_4 */	0xc008d963,
	/* XFER_PIO_3 */	0xc010d974,
	/* XFER_PIO_2 */	0xc010d997,
	/* XFER_PIO_1 */	0xc010d9c7,
	/* XFER_PIO_0 */	0xc018d9d9
Linus Torvalds's avatar
Linus Torvalds committed
271
272
};

273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
static u32 thirty_three_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x90c9a731,
	/* XFER_UDMA_5 */	0x90c9a731,
	/* XFER_UDMA_4 */	0x90c9a731,
	/* XFER_UDMA_3 */	0x90cfa731,
	/* XFER_UDMA_2 */	0x90caa731,
	/* XFER_UDMA_1 */	0x90cba731,
	/* XFER_UDMA_0 */	0x90c8a731,

	/* XFER_MW_DMA_2 */	0xa0c8a731,
	/* XFER_MW_DMA_1 */	0xa0c8a732,	/* 0xa0c8a733 */
	/* XFER_MW_DMA_0 */	0xa0c8a797,

	/* XFER_PIO_4 */	0xc0c8a731,
	/* XFER_PIO_3 */	0xc0c8a742,
	/* XFER_PIO_2 */	0xc0d0a753,
	/* XFER_PIO_1 */	0xc0d0a7a3,	/* 0xc0d0a793 */
	/* XFER_PIO_0 */	0xc0d0a7aa	/* 0xc0d0a7a7 */
Linus Torvalds's avatar
Linus Torvalds committed
291
292
};

293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
static u32 twenty_five_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x90c98521,
	/* XFER_UDMA_5 */	0x90c98521,
	/* XFER_UDMA_4 */	0x90c98521,
	/* XFER_UDMA_3 */	0x90cf8521,
	/* XFER_UDMA_2 */	0x90cf8521,
	/* XFER_UDMA_1 */	0x90cb8521,
	/* XFER_UDMA_0 */	0x90cb8521,

	/* XFER_MW_DMA_2 */	0xa0ca8521,
	/* XFER_MW_DMA_1 */	0xa0ca8532,
	/* XFER_MW_DMA_0 */	0xa0ca8575,

	/* XFER_PIO_4 */	0xc0ca8521,
	/* XFER_PIO_3 */	0xc0ca8532,
	/* XFER_PIO_2 */	0xc0ca8542,
	/* XFER_PIO_1 */	0xc0d08572,
	/* XFER_PIO_0 */	0xc0d08585
Linus Torvalds's avatar
Linus Torvalds committed
311
312
};

313
314
#if 0
/* These are the timing tables from the HighPoint open source drivers... */
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
static u32 thirty_three_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x12446231,	/* 0x12646231 ?? */
	/* XFER_UDMA_5 */	0x12446231,
	/* XFER_UDMA_4 */	0x12446231,
	/* XFER_UDMA_3 */	0x126c6231,
	/* XFER_UDMA_2 */	0x12486231,
	/* XFER_UDMA_1 */	0x124c6233,
	/* XFER_UDMA_0 */	0x12506297,

	/* XFER_MW_DMA_2 */	0x22406c31,
	/* XFER_MW_DMA_1 */	0x22406c33,
	/* XFER_MW_DMA_0 */	0x22406c97,

	/* XFER_PIO_4 */	0x06414e31,
	/* XFER_PIO_3 */	0x06414e42,
	/* XFER_PIO_2 */	0x06414e53,
	/* XFER_PIO_1 */	0x06814e93,
	/* XFER_PIO_0 */	0x06814ea7
Linus Torvalds's avatar
Linus Torvalds committed
333
334
};

335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
static u32 fifty_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x12848242,
	/* XFER_UDMA_5 */	0x12848242,
	/* XFER_UDMA_4 */	0x12ac8242,
	/* XFER_UDMA_3 */	0x128c8242,
	/* XFER_UDMA_2 */	0x120c8242,
	/* XFER_UDMA_1 */	0x12148254,
	/* XFER_UDMA_0 */	0x121882ea,

	/* XFER_MW_DMA_2 */	0x22808242,
	/* XFER_MW_DMA_1 */	0x22808254,
	/* XFER_MW_DMA_0 */	0x228082ea,

	/* XFER_PIO_4 */	0x0a81f442,
	/* XFER_PIO_3 */	0x0a81f443,
	/* XFER_PIO_2 */	0x0a81f454,
	/* XFER_PIO_1 */	0x0ac1f465,
	/* XFER_PIO_0 */	0x0ac1f48a
Linus Torvalds's avatar
Linus Torvalds committed
353
354
};

355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
static u32 sixty_six_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x1c869c62,
	/* XFER_UDMA_5 */	0x1cae9c62,	/* 0x1c8a9c62 */
	/* XFER_UDMA_4 */	0x1c8a9c62,
	/* XFER_UDMA_3 */	0x1c8e9c62,
	/* XFER_UDMA_2 */	0x1c929c62,
	/* XFER_UDMA_1 */	0x1c9a9c62,
	/* XFER_UDMA_0 */	0x1c829c62,

	/* XFER_MW_DMA_2 */	0x2c829c62,
	/* XFER_MW_DMA_1 */	0x2c829c66,
	/* XFER_MW_DMA_0 */	0x2c829d2e,

	/* XFER_PIO_4 */	0x0c829c62,
	/* XFER_PIO_3 */	0x0c829c84,
	/* XFER_PIO_2 */	0x0c829ca6,
	/* XFER_PIO_1 */	0x0d029d26,
	/* XFER_PIO_0 */	0x0d029d5e
Linus Torvalds's avatar
Linus Torvalds committed
373
};
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
#else
/*
 * The following are the new timing tables with PIO mode data/taskfile transfer
 * overclocking fixed...
 */

/* This table is taken from the HPT370 data manual rev. 1.02 */
static u32 thirty_three_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x16455031,	/* 0x16655031 ?? */
	/* XFER_UDMA_5 */	0x16455031,
	/* XFER_UDMA_4 */	0x16455031,
	/* XFER_UDMA_3 */	0x166d5031,
	/* XFER_UDMA_2 */	0x16495031,
	/* XFER_UDMA_1 */	0x164d5033,
	/* XFER_UDMA_0 */	0x16515097,

	/* XFER_MW_DMA_2 */	0x26515031,
	/* XFER_MW_DMA_1 */	0x26515033,
	/* XFER_MW_DMA_0 */	0x26515097,

	/* XFER_PIO_4 */	0x06515021,
	/* XFER_PIO_3 */	0x06515022,
	/* XFER_PIO_2 */	0x06515033,
	/* XFER_PIO_1 */	0x06915065,
	/* XFER_PIO_0 */	0x06d1508a
};

static u32 fifty_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x1a861842,
	/* XFER_UDMA_5 */	0x1a861842,
	/* XFER_UDMA_4 */	0x1aae1842,
	/* XFER_UDMA_3 */	0x1a8e1842,
	/* XFER_UDMA_2 */	0x1a0e1842,
	/* XFER_UDMA_1 */	0x1a161854,
	/* XFER_UDMA_0 */	0x1a1a18ea,

	/* XFER_MW_DMA_2 */	0x2a821842,
	/* XFER_MW_DMA_1 */	0x2a821854,
	/* XFER_MW_DMA_0 */	0x2a8218ea,

	/* XFER_PIO_4 */	0x0a821842,
	/* XFER_PIO_3 */	0x0a821843,
	/* XFER_PIO_2 */	0x0a821855,
	/* XFER_PIO_1 */	0x0ac218a8,
	/* XFER_PIO_0 */	0x0b02190c
};

static u32 sixty_six_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x1c86fe62,
	/* XFER_UDMA_5 */	0x1caefe62,	/* 0x1c8afe62 */
	/* XFER_UDMA_4 */	0x1c8afe62,
	/* XFER_UDMA_3 */	0x1c8efe62,
	/* XFER_UDMA_2 */	0x1c92fe62,
	/* XFER_UDMA_1 */	0x1c9afe62,
	/* XFER_UDMA_0 */	0x1c82fe62,

	/* XFER_MW_DMA_2 */	0x2c82fe62,
	/* XFER_MW_DMA_1 */	0x2c82fe66,
	/* XFER_MW_DMA_0 */	0x2c82ff2e,

	/* XFER_PIO_4 */	0x0c82fe62,
	/* XFER_PIO_3 */	0x0c82fe84,
	/* XFER_PIO_2 */	0x0c82fea6,
	/* XFER_PIO_1 */	0x0d02ff26,
	/* XFER_PIO_0 */	0x0d42ff7f
};
#endif
Linus Torvalds's avatar
Linus Torvalds committed
441
442

#define HPT366_DEBUG_DRIVE_INFO		0
Sergei Shtylyov's avatar
Sergei Shtylyov committed
443
444
445
#define HPT371_ALLOW_ATA133_6		1
#define HPT302_ALLOW_ATA133_6		1
#define HPT372_ALLOW_ATA133_6		1
446
#define HPT370_ALLOW_ATA100_5		0
Linus Torvalds's avatar
Linus Torvalds committed
447
448
449
450
#define HPT366_ALLOW_ATA66_4		1
#define HPT366_ALLOW_ATA66_3		1
#define HPT366_MAX_DEVS			8

Sergei Shtylyov's avatar
Sergei Shtylyov committed
451
452
453
454
455
456
457
458
459
/* Supported ATA clock frequencies */
enum ata_clock {
	ATA_CLOCK_25MHZ,
	ATA_CLOCK_33MHZ,
	ATA_CLOCK_40MHZ,
	ATA_CLOCK_50MHZ,
	ATA_CLOCK_66MHZ,
	NUM_ATA_CLOCKS
};
Linus Torvalds's avatar
Linus Torvalds committed
460

461
/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
462
 *	Hold all the HighPoint chip information in one place.
463
 */
Linus Torvalds's avatar
Linus Torvalds committed
464

Sergei Shtylyov's avatar
Sergei Shtylyov committed
465
struct hpt_info {
466
	char *chip_name;	/* Chip name */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
467
	u8 chip_type;		/* Chip type */
468
	u8 udma_mask;		/* Allowed UltraDMA modes mask. */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
469
470
471
	u8 dpll_clk;		/* DPLL clock in MHz */
	u8 pci_clk;		/* PCI  clock in MHz */
	u32 **settings; 	/* Chipset settings table */
472
473
};

Sergei Shtylyov's avatar
Sergei Shtylyov committed
474
475
476
477
478
479
480
481
482
483
484
485
486
487
/* Supported HighPoint chips */
enum {
	HPT36x,
	HPT370,
	HPT370A,
	HPT374,
	HPT372,
	HPT372A,
	HPT302,
	HPT371,
	HPT372N,
	HPT302N,
	HPT371N
};
488

Sergei Shtylyov's avatar
Sergei Shtylyov committed
489
490
491
492
493
494
495
static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
	twenty_five_base_hpt36x,
	thirty_three_base_hpt36x,
	forty_base_hpt36x,
	NULL,
	NULL
};
496

Sergei Shtylyov's avatar
Sergei Shtylyov committed
497
498
499
500
501
502
503
static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
	NULL,
	thirty_three_base_hpt37x,
	NULL,
	fifty_base_hpt37x,
	sixty_six_base_hpt37x
};
Linus Torvalds's avatar
Linus Torvalds committed
504

505
static const struct hpt_info hpt36x __devinitdata = {
506
	.chip_name	= "HPT36x",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
507
	.chip_type	= HPT36x,
508
	.udma_mask	= HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
509
510
511
512
	.dpll_clk	= 0,	/* no DPLL */
	.settings	= hpt36x_settings
};

513
static const struct hpt_info hpt370 __devinitdata = {
514
	.chip_name	= "HPT370",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
515
	.chip_type	= HPT370,
516
	.udma_mask	= HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
517
518
519
520
	.dpll_clk	= 48,
	.settings	= hpt37x_settings
};

521
static const struct hpt_info hpt370a __devinitdata = {
522
	.chip_name	= "HPT370A",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
523
	.chip_type	= HPT370A,
524
	.udma_mask	= HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
525
526
527
528
	.dpll_clk	= 48,
	.settings	= hpt37x_settings
};

529
static const struct hpt_info hpt374 __devinitdata = {
530
	.chip_name	= "HPT374",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
531
	.chip_type	= HPT374,
532
	.udma_mask	= ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
533
534
535
536
	.dpll_clk	= 48,
	.settings	= hpt37x_settings
};

537
static const struct hpt_info hpt372 __devinitdata = {
538
	.chip_name	= "HPT372",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
539
	.chip_type	= HPT372,
540
	.udma_mask	= HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
541
542
543
544
	.dpll_clk	= 55,
	.settings	= hpt37x_settings
};

545
static const struct hpt_info hpt372a __devinitdata = {
546
	.chip_name	= "HPT372A",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
547
	.chip_type	= HPT372A,
548
	.udma_mask	= HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
549
550
551
552
	.dpll_clk	= 66,
	.settings	= hpt37x_settings
};

553
static const struct hpt_info hpt302 __devinitdata = {
554
	.chip_name	= "HPT302",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
555
	.chip_type	= HPT302,
556
	.udma_mask	= HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
557
558
559
560
	.dpll_clk	= 66,
	.settings	= hpt37x_settings
};

561
static const struct hpt_info hpt371 __devinitdata = {
562
	.chip_name	= "HPT371",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
563
	.chip_type	= HPT371,
564
	.udma_mask	= HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
565
566
567
568
	.dpll_clk	= 66,
	.settings	= hpt37x_settings
};

569
static const struct hpt_info hpt372n __devinitdata = {
570
	.chip_name	= "HPT372N",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
571
	.chip_type	= HPT372N,
572
	.udma_mask	= HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
573
574
575
576
	.dpll_clk	= 77,
	.settings	= hpt37x_settings
};

577
static const struct hpt_info hpt302n __devinitdata = {
578
	.chip_name	= "HPT302N",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
579
	.chip_type	= HPT302N,
580
	.udma_mask	= HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
581
	.dpll_clk	= 77,
582
	.settings	= hpt37x_settings
Sergei Shtylyov's avatar
Sergei Shtylyov committed
583
584
};

585
static const struct hpt_info hpt371n __devinitdata = {
586
	.chip_name	= "HPT371N",
Sergei Shtylyov's avatar
Sergei Shtylyov committed
587
	.chip_type	= HPT371N,
588
	.udma_mask	= HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov's avatar
Sergei Shtylyov committed
589
590
591
	.dpll_clk	= 77,
	.settings	= hpt37x_settings
};
Linus Torvalds's avatar
Linus Torvalds committed
592

593
594
595
596
597
598
599
600
601
static int check_in_drive_list(ide_drive_t *drive, const char **list)
{
	struct hd_driveid *id = drive->id;

	while (*list)
		if (!strcmp(*list++,id->model))
			return 1;
	return 0;
}
Linus Torvalds's avatar
Linus Torvalds committed
602
603

/*
604
605
 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds's avatar
Linus Torvalds committed
606
 */
607
608

static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
609
{
610
611
612
	ide_hwif_t *hwif	= HWIF(drive);
	struct hpt_info *info	= pci_get_drvdata(hwif->pci_dev);
	u8 mask 		= hwif->ultra_mask;
Linus Torvalds's avatar
Linus Torvalds committed
613

614
615
616
617
	switch (info->chip_type) {
	case HPT36x:
		if (!HPT366_ALLOW_ATA66_4 ||
		    check_in_drive_list(drive, bad_ata66_4))
618
			mask = ATA_UDMA3;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
619

620
621
		if (!HPT366_ALLOW_ATA66_3 ||
		    check_in_drive_list(drive, bad_ata66_3))
622
			mask = ATA_UDMA2;
623
		break;
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
	case HPT370:
		if (!HPT370_ALLOW_ATA100_5 ||
		    check_in_drive_list(drive, bad_ata100_5))
			mask = ATA_UDMA4;
		break;
	case HPT370A:
		if (!HPT370_ALLOW_ATA100_5 ||
		    check_in_drive_list(drive, bad_ata100_5))
			return ATA_UDMA4;
	case HPT372 :
	case HPT372A:
	case HPT372N:
	case HPT374 :
		if (ide_dev_is_sata(drive->id))
			mask &= ~0x0e;
		/* Fall thru */
640
	default:
641
		return mask;
Linus Torvalds's avatar
Linus Torvalds committed
642
	}
643
644

	return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds's avatar
Linus Torvalds committed
645
646
}

647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct hpt_info *info	= pci_get_drvdata(hwif->pci_dev);

	switch (info->chip_type) {
	case HPT372 :
	case HPT372A:
	case HPT372N:
	case HPT374 :
		if (ide_dev_is_sata(drive->id))
			return 0x00;
		/* Fall thru */
	default:
		return 0x07;
	}
}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
665
static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds's avatar
Linus Torvalds committed
666
{
667
668
669
670
671
672
673
674
675
676
677
	int i;

	/*
	 * Lookup the transfer mode table to get the index into
	 * the timing table.
	 *
	 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
	 */
	for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
		if (xfer_speeds[i] == speed)
			break;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
678
679
680
681
682
	/*
	 * NOTE: info->settings only points to the pointer
	 * to the list of the actual register values
	 */
	return (*info->settings)[i];
Linus Torvalds's avatar
Linus Torvalds committed
683
684
}

685
static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds's avatar
Linus Torvalds committed
686
{
687
688
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev  *dev	= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
689
	struct hpt_info	*info	= pci_get_drvdata(dev);
690
	u8  itr_addr		= drive->dn ? 0x44 : 0x40;
691
	u32 old_itr		= 0;
692
693
694
695
	u32 new_itr		= get_speed_setting(speed, info);
	u32 itr_mask		= speed < XFER_MW_DMA_0 ? 0xc1f8ffff :
				 (speed < XFER_UDMA_0   ? 0x303800ff :
							  0x30070000);
696

697
698
	pci_read_config_dword(dev, itr_addr, &old_itr);
	new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds's avatar
Linus Torvalds committed
699
	/*
700
701
	 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
	 * to avoid problems handling I/O errors later
Linus Torvalds's avatar
Linus Torvalds committed
702
	 */
703
	new_itr &= ~0xc0000000;
Linus Torvalds's avatar
Linus Torvalds committed
704

705
	pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds's avatar
Linus Torvalds committed
706
707
}

708
static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds's avatar
Linus Torvalds committed
709
{
710
711
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev  *dev	= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
712
	struct hpt_info	*info	= pci_get_drvdata(dev);
713
	u8  itr_addr		= 0x40 + (drive->dn * 4);
714
	u32 old_itr		= 0;
715
716
717
718
	u32 new_itr		= get_speed_setting(speed, info);
	u32 itr_mask		= speed < XFER_MW_DMA_0 ? 0xcfc3ffff :
				 (speed < XFER_UDMA_0   ? 0x31c001ff :
							  0x303c0000);
Linus Torvalds's avatar
Linus Torvalds committed
719

720
	pci_read_config_dword(dev, itr_addr, &old_itr);
721
722
	new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);

723
	if (speed < XFER_MW_DMA_0)
724
725
		new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
	pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds's avatar
Linus Torvalds committed
726
727
}

728
static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds's avatar
Linus Torvalds committed
729
{
730
	HWIF(drive)->set_dma_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds's avatar
Linus Torvalds committed
731
732
}

733
static int hpt3xx_quirkproc(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
734
{
735
736
737
738
739
740
741
	struct hd_driveid *id	= drive->id;
	const  char **list	= quirk_drives;

	while (*list)
		if (strstr(id->model, *list++))
			return 1;
	return 0;
Linus Torvalds's avatar
Linus Torvalds committed
742
743
}

744
static void hpt3xx_intrproc(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
745
746
747
{
	if (drive->quirk_list)
		return;
748

Linus Torvalds's avatar
Linus Torvalds committed
749
	/* drives in the quirk_list may not like intr setups/cleanups */
750
	outb(drive->ctl | 2, IDE_CONTROL_REG);
Linus Torvalds's avatar
Linus Torvalds committed
751
752
}

753
static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds's avatar
Linus Torvalds committed
754
{
755
756
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev	*dev	= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
757
	struct hpt_info *info	= pci_get_drvdata(dev);
Linus Torvalds's avatar
Linus Torvalds committed
758
759

	if (drive->quirk_list) {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
760
		if (info->chip_type >= HPT370) {
761
762
763
764
765
766
767
768
769
770
			u8 scr1 = 0;

			pci_read_config_byte(dev, 0x5a, &scr1);
			if (((scr1 & 0x10) >> 4) != mask) {
				if (mask)
					scr1 |=  0x10;
				else
					scr1 &= ~0x10;
				pci_write_config_byte(dev, 0x5a, scr1);
			}
Linus Torvalds's avatar
Linus Torvalds committed
771
		} else {
772
			if (mask)
773
				disable_irq(hwif->irq);
774
775
			else
				enable_irq (hwif->irq);
Linus Torvalds's avatar
Linus Torvalds committed
776
		}
777
	} else
778
779
		outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
		     IDE_CONTROL_REG);
Linus Torvalds's avatar
Linus Torvalds committed
780
781
782
}

/*
783
 * This is specific to the HPT366 UDMA chipset
Linus Torvalds's avatar
Linus Torvalds committed
784
785
 * by HighPoint|Triones Technologies, Inc.
 */
786
static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
787
{
788
789
790
791
792
793
794
795
796
797
	struct pci_dev *dev = HWIF(drive)->pci_dev;
	u8 mcr1 = 0, mcr3 = 0, scr1 = 0;

	pci_read_config_byte(dev, 0x50, &mcr1);
	pci_read_config_byte(dev, 0x52, &mcr3);
	pci_read_config_byte(dev, 0x5a, &scr1);
	printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
		drive->name, __FUNCTION__, mcr1, mcr3, scr1);
	if (scr1 & 0x10)
		pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
798
	ide_dma_lost_irq(drive);
Linus Torvalds's avatar
Linus Torvalds committed
799
800
}

801
static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
802
{
803
804
805
	ide_hwif_t *hwif = HWIF(drive);

	pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
Linus Torvalds's avatar
Linus Torvalds committed
806
807
808
	udelay(10);
}

809
810
811
812
813
814
815
816
817
818
static void hpt370_irq_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u16 bfifo		= 0;
	u8  dma_cmd;

	pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
	printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);

	/* get DMA command mode */
819
	dma_cmd = inb(hwif->dma_command);
820
	/* stop DMA */
821
	outb(dma_cmd & ~0x1, hwif->dma_command);
822
823
824
	hpt370_clear_engine(drive);
}

Linus Torvalds's avatar
Linus Torvalds committed
825
826
827
828
829
830
831
832
static void hpt370_ide_dma_start(ide_drive_t *drive)
{
#ifdef HPT_RESET_STATE_ENGINE
	hpt370_clear_engine(drive);
#endif
	ide_dma_start(drive);
}

833
static int hpt370_ide_dma_end(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
834
835
{
	ide_hwif_t *hwif	= HWIF(drive);
836
	u8  dma_stat		= inb(hwif->dma_status);
Linus Torvalds's avatar
Linus Torvalds committed
837
838
839
840

	if (dma_stat & 0x01) {
		/* wait a little */
		udelay(20);
841
		dma_stat = inb(hwif->dma_status);
842
843
		if (dma_stat & 0x01)
			hpt370_irq_timeout(drive);
Linus Torvalds's avatar
Linus Torvalds committed
844
845
846
847
	}
	return __ide_dma_end(drive);
}

848
static void hpt370_dma_timeout(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
849
{
850
	hpt370_irq_timeout(drive);
851
	ide_dma_timeout(drive);
Linus Torvalds's avatar
Linus Torvalds committed
852
853
854
855
856
857
858
}

/* returns 1 if DMA IRQ issued, 0 otherwise */
static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u16 bfifo		= 0;
859
	u8  dma_stat;
Linus Torvalds's avatar
Linus Torvalds committed
860

861
	pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
Linus Torvalds's avatar
Linus Torvalds committed
862
863
864
865
866
	if (bfifo & 0x1FF) {
//		printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
		return 0;
	}

867
	dma_stat = inb(hwif->dma_status);
Linus Torvalds's avatar
Linus Torvalds committed
868
	/* return 1 if INTR asserted */
869
	if (dma_stat & 4)
Linus Torvalds's avatar
Linus Torvalds committed
870
871
872
873
874
875
876
877
		return 1;

	if (!drive->waiting_for_dma)
		printk(KERN_WARNING "%s: (%s) called while not waiting\n",
				drive->name, __FUNCTION__);
	return 0;
}

878
static int hpt374_ide_dma_end(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
879
880
{
	ide_hwif_t *hwif	= HWIF(drive);
881
882
883
884
885
886
887
888
	struct pci_dev	*dev	= hwif->pci_dev;
	u8 mcr	= 0, mcr_addr	= hwif->select_data;
	u8 bwsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	pci_read_config_byte(dev, 0x6a, &bwsr);
	pci_read_config_byte(dev, mcr_addr, &mcr);
	if (bwsr & mask)
		pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Linus Torvalds's avatar
Linus Torvalds committed
889
890
891
892
	return __ide_dma_end(drive);
}

/**
893
894
895
 *	hpt3xxn_set_clock	-	perform clock switching dance
 *	@hwif: hwif to switch
 *	@mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds's avatar
Linus Torvalds committed
896
 *
897
 *	Switch the DPLL clock on the HPT3xxN devices. This is a	right mess.
Linus Torvalds's avatar
Linus Torvalds committed
898
 */
899
900

static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds's avatar
Linus Torvalds committed
901
{
902
	u8 scr2 = inb(hwif->dma_master + 0x7b);
903
904
905
906

	if ((scr2 & 0x7f) == mode)
		return;

Linus Torvalds's avatar
Linus Torvalds committed
907
	/* Tristate the bus */
908
909
	outb(0x80, hwif->dma_master + 0x73);
	outb(0x80, hwif->dma_master + 0x77);
910

Linus Torvalds's avatar
Linus Torvalds committed
911
	/* Switch clock and reset channels */
912
913
	outb(mode, hwif->dma_master + 0x7b);
	outb(0xc0, hwif->dma_master + 0x79);
914

Sergei Shtylyov's avatar
Sergei Shtylyov committed
915
916
917
918
	/*
	 * Reset the state machines.
	 * NOTE: avoid accidentally enabling the disabled channels.
	 */
919
920
	outb(inb(hwif->dma_master + 0x70) | 0x32, hwif->dma_master + 0x70);
	outb(inb(hwif->dma_master + 0x74) | 0x32, hwif->dma_master + 0x74);
921

Linus Torvalds's avatar
Linus Torvalds committed
922
	/* Complete reset */
923
	outb(0x00, hwif->dma_master + 0x79);
924

Linus Torvalds's avatar
Linus Torvalds committed
925
	/* Reconnect channels to bus */
926
927
	outb(0x00, hwif->dma_master + 0x73);
	outb(0x00, hwif->dma_master + 0x77);
Linus Torvalds's avatar
Linus Torvalds committed
928
929
930
}

/**
931
 *	hpt3xxn_rw_disk		-	prepare for I/O
Linus Torvalds's avatar
Linus Torvalds committed
932
933
934
 *	@drive: drive for command
 *	@rq: block request structure
 *
935
 *	This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds's avatar
Linus Torvalds committed
936
937
938
 *	We need it because of the clock switching.
 */

939
static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds's avatar
Linus Torvalds committed
940
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
941
	hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds's avatar
Linus Torvalds committed
942
943
944
}

/* 
945
 * Set/get power state for a drive.
946
 * NOTE: affects both drives on each channel.
Linus Torvalds's avatar
Linus Torvalds committed
947
 *
948
 * When we turn the power back on, we need to re-initialize things.
Linus Torvalds's avatar
Linus Torvalds committed
949
950
 */
#define TRISTATE_BIT  0x8000
951
952

static int hpt3xx_busproc(ide_drive_t *drive, int state)
Linus Torvalds's avatar
Linus Torvalds committed
953
{
954
	ide_hwif_t *hwif	= HWIF(drive);
Linus Torvalds's avatar
Linus Torvalds committed
955
	struct pci_dev *dev	= hwif->pci_dev;
956
957
958
959
	u8  mcr_addr		= hwif->select_data + 2;
	u8  resetmask		= hwif->channel ? 0x80 : 0x40;
	u8  bsr2		= 0;
	u16 mcr			= 0;
Linus Torvalds's avatar
Linus Torvalds committed
960
961
962

	hwif->bus_state = state;

963
	/* Grab the status. */
964
965
	pci_read_config_word(dev, mcr_addr, &mcr);
	pci_read_config_byte(dev, 0x59, &bsr2);
Linus Torvalds's avatar
Linus Torvalds committed
966

967
968
969
970
	/*
	 * Set the state. We don't set it if we don't need to do so.
	 * Make sure that the drive knows that it has failed if it's off.
	 */
Linus Torvalds's avatar
Linus Torvalds committed
971
972
	switch (state) {
	case BUSSTATE_ON:
973
		if (!(bsr2 & resetmask))
Linus Torvalds's avatar
Linus Torvalds committed
974
			return 0;
975
976
		hwif->drives[0].failures = hwif->drives[1].failures = 0;

977
978
		pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
		pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
979
		return 0;
Linus Torvalds's avatar
Linus Torvalds committed
980
	case BUSSTATE_OFF:
981
		if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
Linus Torvalds's avatar
Linus Torvalds committed
982
			return 0;
983
		mcr &= ~TRISTATE_BIT;
Linus Torvalds's avatar
Linus Torvalds committed
984
985
		break;
	case BUSSTATE_TRISTATE:
986
		if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
Linus Torvalds's avatar
Linus Torvalds committed
987
			return 0;
988
		mcr |= TRISTATE_BIT;
Linus Torvalds's avatar
Linus Torvalds committed
989
		break;
990
991
	default:
		return -EINVAL;
Linus Torvalds's avatar
Linus Torvalds committed
992
993
	}

994
995
996
	hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
	hwif->drives[1].failures = hwif->drives[1].max_failures + 1;

997
998
	pci_write_config_word(dev, mcr_addr, mcr);
	pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
Linus Torvalds's avatar
Linus Torvalds committed
999
1000
1001
	return 0;
}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1002
1003
1004
1005
1006
1007
1008
1009
/**
 *	hpt37x_calibrate_dpll	-	calibrate the DPLL
 *	@dev: PCI device
 *
 *	Perform a calibration cycle on the DPLL.
 *	Returns 1 if this succeeds
 */
static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds's avatar
Linus Torvalds committed
1010
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1011
1012
1013
	u32 dpll = (f_high << 16) | f_low | 0x100;
	u8  scr2;
	int i;
1014

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1015
	pci_write_config_dword(dev, 0x5c, dpll);
1016

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1017
1018
1019
1020
1021
	/* Wait for oscillator ready */
	for(i = 0; i < 0x5000; ++i) {
		udelay(50);
		pci_read_config_byte(dev, 0x5b, &scr2);
		if (scr2 & 0x80)
1022
1023
			break;
	}
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
	/* See if it stays ready (we'll just bail out if it's not yet) */
	for(i = 0; i < 0x1000; ++i) {
		pci_read_config_byte(dev, 0x5b, &scr2);
		/* DPLL destabilized? */
		if(!(scr2 & 0x80))
			return 0;
	}
	/* Turn off tuning, we have the DPLL set */
	pci_read_config_dword (dev, 0x5c, &dpll);
	pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
	return 1;
1035
1036
}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1037
static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1038
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1039
1040
1041
	struct hpt_info *info	= kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
	unsigned long io_base	= pci_resource_start(dev, 4);
	u8 pci_clk,  dpll_clk	= 0;	/* PCI and DPLL clock in MHz */
1042
	u8 chip_type;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1043
1044
1045
1046
1047
1048
1049
	enum ata_clock	clock;

	if (info == NULL) {
		printk(KERN_ERR "%s: out of memory!\n", name);
		return -ENOMEM;
	}

Linus Torvalds's avatar
Linus Torvalds committed
1050
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1051
1052
	 * Copy everything from a static "template" structure
	 * to just allocated per-chip hpt_info structure.
Linus Torvalds's avatar
Linus Torvalds committed
1053
	 */
1054
1055
	memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
	chip_type = info->chip_type;
Linus Torvalds's avatar
Linus Torvalds committed
1056

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1057
1058
1059
1060
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1061

Linus Torvalds's avatar
Linus Torvalds committed
1062
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1063
	 * First, try to estimate the PCI clock frequency...
Linus Torvalds's avatar
Linus Torvalds committed
1064
	 */
1065
	if (chip_type >= HPT370) {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
		u8  scr1  = 0;
		u16 f_cnt = 0;
		u32 temp  = 0;

		/* Interrupt force enable. */
		pci_read_config_byte(dev, 0x5a, &scr1);
		if (scr1 & 0x10)
			pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);

		/*
		 * HighPoint does this for HPT372A.
		 * NOTE: This register is only writeable via I/O space.
		 */
1079
		if (chip_type == HPT372A)
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1080
1081
1082
1083
1084
1085
1086
			outb(0x0e, io_base + 0x9c);

		/*
		 * Default to PCI clock. Make sure MA15/16 are set to output
		 * to prevent drives having problems with 40-pin cables.
		 */
		pci_write_config_byte(dev, 0x5b, 0x23);
1087

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
		/*
		 * We'll have to read f_CNT value in order to determine
		 * the PCI clock frequency according to the following ratio:
		 *
		 * f_CNT = Fpci * 192 / Fdpll
		 *
		 * First try reading the register in which the HighPoint BIOS
		 * saves f_CNT value before  reprogramming the DPLL from its
		 * default setting (which differs for the various chips).
		 *
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
		 * NOTE: This register is only accessible via I/O space;
		 * HPT374 BIOS only saves it for the function 0, so we have to
		 * always read it from there -- no need to check the result of
		 * pci_get_slot() for the function 0 as the whole device has
		 * been already "pinned" (via function 1) in init_setup_hpt374()
		 */
		if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
			struct pci_dev	*dev1 = pci_get_slot(dev->bus,
							     dev->devfn - 1);
			unsigned long io_base = pci_resource_start(dev1, 4);

			temp =	inl(io_base + 0x90);
			pci_dev_put(dev1);
		} else
			temp =	inl(io_base + 0x90);

		/*
		 * In case the signature check fails, we'll have to
		 * resort to reading the f_CNT register itself in hopes
		 * that nobody has touched the DPLL yet...
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
		 */
		if ((temp & 0xFFFFF000) != 0xABCDE000) {
			int i;

			printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
			       name);

			/* Calculate the average value of f_CNT. */
			for (temp = i = 0; i < 128; i++) {
				pci_read_config_word(dev, 0x78, &f_cnt);
				temp += f_cnt & 0x1ff;
				mdelay(1);
			}
			f_cnt = temp / 128;
		} else
			f_cnt = temp & 0x1ff;

		dpll_clk = info->dpll_clk;
		pci_clk  = (f_cnt * dpll_clk) / 192;

		/* Clamp PCI clock to bands. */
		if (pci_clk < 40)
			pci_clk = 33;
		else if(pci_clk < 45)
			pci_clk = 40;
		else if(pci_clk < 55)
			pci_clk = 50;
Linus Torvalds's avatar
Linus Torvalds committed
1145
		else
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1146
			pci_clk = 66;
1147

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1148
1149
		printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
		       "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1150
	} else {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1151
1152
1153
1154
1155
1156
1157
1158
		u32 itr1 = 0;

		pci_read_config_dword(dev, 0x40, &itr1);

		/* Detect PCI clock by looking at cmd_high_time. */
		switch((itr1 >> 8) & 0x07) {
			case 0x09:
				pci_clk = 40;
1159
				break;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1160
1161
			case 0x05:
				pci_clk = 25;
1162
				break;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1163
1164
1165
			case 0x07:
			default:
				pci_clk = 33;
1166
				break;
Linus Torvalds's avatar
Linus Torvalds committed
1167
1168
		}
	}
1169

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
	/* Let's assume we'll use PCI clock for the ATA clock... */
	switch (pci_clk) {
		case 25:
			clock = ATA_CLOCK_25MHZ;
			break;
		case 33:
		default:
			clock = ATA_CLOCK_33MHZ;
			break;
		case 40:
			clock = ATA_CLOCK_40MHZ;
			break;
		case 50:
			clock = ATA_CLOCK_50MHZ;
			break;
		case 66:
			clock = ATA_CLOCK_66MHZ;
			break;
	}
1189

Linus Torvalds's avatar
Linus Torvalds committed
1190
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1191
1192
	 * Only try the DPLL if we don't have a table for the PCI clock that
	 * we are running at for HPT370/A, always use it  for anything newer...
1193
	 *
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1194
1195
1196
	 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
	 * We also  don't like using  the DPLL because this causes glitches
	 * on PRST-/SRST- when the state engine gets reset...
Linus Torvalds's avatar
Linus Torvalds committed
1197
	 */
1198
	if (chip_type >= HPT374 || info->settings[clock] == NULL) {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1199
1200
1201
1202
1203
1204
1205
		u16 f_low, delta = pci_clk < 50 ? 2 : 4;
		int adjust;

		 /*
		  * Select 66 MHz DPLL clock only if UltraATA/133 mode is
		  * supported/enabled, use 50 MHz DPLL clock otherwise...
		  */
1206
		if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1207
1208
1209
1210
1211
1212
			dpll_clk = 66;
			clock = ATA_CLOCK_66MHZ;
		} else if (dpll_clk) {	/* HPT36x chips don't have DPLL */
			dpll_clk = 50;
			clock = ATA_CLOCK_50MHZ;
		}
1213

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1214
1215
1216
1217
		if (info->settings[clock] == NULL) {
			printk(KERN_ERR "%s: unknown bus timing!\n", name);
			kfree(info);
			return -EIO;
Linus Torvalds's avatar
Linus Torvalds committed
1218
1219
		}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
		/* Select the DPLL clock. */
		pci_write_config_byte(dev, 0x5b, 0x21);

		/*
		 * Adjust the DPLL based upon PCI clock, enable it,
		 * and wait for stabilization...
		 */
		f_low = (pci_clk * 48) / dpll_clk;

		for (adjust = 0; adjust < 8; adjust++) {
			if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
				break;

			/*
			 * See if it'll settle at a fractionally different clock
			 */
			if (adjust & 1)
				f_low -= adjust >> 1;
			else
				f_low += adjust >> 1;
		}
		if (adjust == 8) {
			printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
			kfree(info);
			return -EIO;
		}

		printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
	} else {
		/* Mark the fact that we're not using the DPLL. */
		dpll_clk = 0;

		printk("%s: using %d MHz PCI clock\n", name, pci_clk);
	}
1254

1255
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1256
1257
	 * Advance the table pointer to a slot which points to the list
	 * of the register values settings matching the clock being used.
1258
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1259
	info->settings += clock;
Linus Torvalds's avatar
Linus Torvalds committed
1260

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1261
1262
1263
	/* Store the clock frequencies. */
	info->dpll_clk	= dpll_clk;
	info->pci_clk	= pci_clk;
Linus Torvalds's avatar
Linus Torvalds committed
1264

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1265
1266
	/* Point to this chip's own instance of the hpt_info structure. */
	pci_set_drvdata(dev, info);
1267

1268
	if (chip_type >= HPT370) {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
		u8  mcr1, mcr4;

		/*
		 * Reset the state engines.
		 * NOTE: Avoid accidentally enabling the disabled channels.
		 */
		pci_read_config_byte (dev, 0x50, &mcr1);
		pci_read_config_byte (dev, 0x54, &mcr4);
		pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
		pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
		udelay(100);
1280
	}
Linus Torvalds's avatar
Linus Torvalds committed
1281

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1282
1283
1284
1285
1286
	/*
	 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
	 * the MISC. register to stretch the UltraDMA Tss timing.
	 * NOTE: This register is only writeable via I/O space.
	 */
1287
	if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1288
1289
1290

		outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);