clock-sh7786.c 3.15 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
 *
 * SH7786 support for the clock framework
 *
 * Copyright (C) 2008, 2009  Renesas Solutions Corp.
 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
 *
 * Based on SH7785
 *  Copyright (C) 2007  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/clock.h>
#include <asm/freq.h>
#include <asm/io.h>

static int ifc_divisors[] = { 1, 2, 4, 1 };
static int sfc_divisors[] = { 1, 1, 4, 1 };
static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
			     24, 32, 1, 1, 1, 1, 1, 1 };
static int mfc_divisors[] = { 1, 1, 4, 1 };
static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
			      24, 32, 1, 48, 1, 1, 1, 1 };

static void master_clk_init(struct clk *clk)
{
	clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
}

static struct clk_ops sh7786_master_clk_ops = {
	.init		= master_clk_init,
};

39
static unsigned long module_clk_recalc(struct clk *clk)
40 41
{
	int idx = (ctrl_inl(FRQMR1) & 0x000f);
42
	return clk->parent->rate / pfc_divisors[idx];
43 44 45 46 47 48
}

static struct clk_ops sh7786_module_clk_ops = {
	.recalc		= module_clk_recalc,
};

49
static unsigned long bus_clk_recalc(struct clk *clk)
50 51
{
	int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52
	return clk->parent->rate / bfc_divisors[idx];
53 54 55 56 57 58
}

static struct clk_ops sh7786_bus_clk_ops = {
	.recalc		= bus_clk_recalc,
};

59
static unsigned long cpu_clk_recalc(struct clk *clk)
60 61
{
	int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62
	return clk->parent->rate / ifc_divisors[idx];
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
}

static struct clk_ops sh7786_cpu_clk_ops = {
	.recalc		= cpu_clk_recalc,
};

static struct clk_ops *sh7786_clk_ops[] = {
	&sh7786_master_clk_ops,
	&sh7786_module_clk_ops,
	&sh7786_bus_clk_ops,
	&sh7786_cpu_clk_ops,
};

void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
{
	if (idx < ARRAY_SIZE(sh7786_clk_ops))
		*ops = sh7786_clk_ops[idx];
}

82
static unsigned long shyway_clk_recalc(struct clk *clk)
83 84
{
	int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85
	return clk->parent->rate / sfc_divisors[idx];
86 87 88 89 90 91 92 93
}

static struct clk_ops sh7786_shyway_clk_ops = {
	.recalc		= shyway_clk_recalc,
};

static struct clk sh7786_shyway_clk = {
	.name		= "shyway_clk",
94
	.flags		= CLK_ENABLE_ON_INIT,
95 96 97
	.ops		= &sh7786_shyway_clk_ops,
};

98
static unsigned long ddr_clk_recalc(struct clk *clk)
99 100
{
	int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101
	return clk->parent->rate / mfc_divisors[idx];
102 103 104 105 106 107 108 109
}

static struct clk_ops sh7786_ddr_clk_ops = {
	.recalc		= ddr_clk_recalc,
};

static struct clk sh7786_ddr_clk = {
	.name		= "ddr_clk",
110
	.flags		= CLK_ENABLE_ON_INIT,
111 112 113 114 115 116 117 118 119 120 121 122
	.ops		= &sh7786_ddr_clk_ops,
};

/*
 * Additional SH7786-specific on-chip clocks that aren't already part of the
 * clock framework
 */
static struct clk *sh7786_onchip_clocks[] = {
	&sh7786_shyway_clk,
	&sh7786_ddr_clk,
};

123
int __init arch_clk_init(void)
124 125
{
	struct clk *clk = clk_get(NULL, "master_clk");
126
	int i, ret = 0;
127 128 129 130 131

	for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
		struct clk *clkp = sh7786_onchip_clocks[i];

		clkp->parent = clk;
132
		ret |= clk_register(clkp);
133 134 135 136
	}

	clk_put(clk);

137
	return ret;
138
}