ath.h 8.05 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ATH_H
#define ATH_H

#include <linux/skbuff.h>
21
#include <linux/if_ether.h>
22
#include <linux/spinlock.h>
23
#include <net/mac80211.h>
24

25
26
27
28
29
30
31
32
33
34
/*
 * The key cache is used for h/w cipher state and also for
 * tracking station state such as the current tx antenna.
 * We also setup a mapping table between key cache slot indices
 * and station state to short-circuit node lookups on rx.
 * Different parts have different size key caches.  We handle
 * up to ATH_KEYMAX entries (could dynamically allocate state).
 */
#define	ATH_KEYMAX	        128     /* max key cache size we handle */

35
36
static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

37
38
39
40
41
42
43
44
45
struct ath_ani {
	bool caldone;
	unsigned int longcal_timer;
	unsigned int shortcal_timer;
	unsigned int resetcal_timer;
	unsigned int checkani_timer;
	struct timer_list timer;
};

46
47
48
49
50
51
52
struct ath_cycle_counters {
	u32 cycles;
	u32 rx_busy;
	u32 rx_frame;
	u32 tx_frame;
};

53
54
55
56
57
enum ath_device_state {
	ATH_HW_UNAVAILABLE,
	ATH_HW_INITIALIZED,
};

Sujith's avatar
Sujith committed
58
59
60
61
62
63
enum ath_bus_type {
	ATH_PCI,
	ATH_AHB,
	ATH_USB,
};

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
struct reg_dmn_pair_mapping {
	u16 regDmnEnum;
	u16 reg_5ghz_ctl;
	u16 reg_2ghz_ctl;
};

struct ath_regulatory {
	char alpha2[2];
	u16 country_code;
	u16 max_power_level;
	u16 current_rd;
	int16_t power_limit;
	struct reg_dmn_pair_mapping *regpair;
};

79
enum ath_crypt_caps {
80
81
	ATH_CRYPT_CAP_CIPHER_AESCCM		= BIT(0),
	ATH_CRYPT_CAP_MIC_COMBINED		= BIT(1),
82
83
};

84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
struct ath_keyval {
	u8 kv_type;
	u8 kv_pad;
	u16 kv_len;
	u8 kv_val[16]; /* TK */
	u8 kv_mic[8]; /* Michael MIC key */
	u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
			 * supports both MIC keys in the same key cache entry;
			 * in that case, kv_mic is the RX key) */
};

enum ath_cipher {
	ATH_CIPHER_WEP = 0,
	ATH_CIPHER_AES_OCB = 1,
	ATH_CIPHER_AES_CCM = 2,
	ATH_CIPHER_CKIP = 3,
	ATH_CIPHER_TKIP = 4,
	ATH_CIPHER_CLR = 5,
	ATH_CIPHER_MIC = 127
};

105
106
107
108
/**
 * struct ath_ops - Register read/write operations
 *
 * @read: Register read
109
 * @multi_read: Multiple register read
110
111
 * @write: Register write
 * @enable_write_buffer: Enable multiple register writes
112
 * @write_flush: flush buffered register writes and disable buffering
113
 */
114
115
struct ath_ops {
	unsigned int (*read)(void *, u32 reg_offset);
116
	void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
117
118
119
	void (*write)(void *, u32 val, u32 reg_offset);
	void (*enable_write_buffer)(void *);
	void (*write_flush) (void *);
120
	u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
121
122
};

123
struct ath_common;
124
struct ath_bus_ops;
125

126
struct ath_common {
127
	void *ah;
128
	void *priv;
129
	struct ieee80211_hw *hw;
130
	int debug_mask;
131
	enum ath_device_state state;
132

133
134
	struct ath_ani ani;

135
	u16 cachelsz;
136
137
138
139
	u16 curaid;
	u8 macaddr[ETH_ALEN];
	u8 curbssid[ETH_ALEN];
	u8 bssidmask[ETH_ALEN];
140

141
142
	u32 rx_bufsize;

143
144
	u32 keymax;
	DECLARE_BITMAP(keymap, ATH_KEYMAX);
145
	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
146
	enum ath_crypt_caps crypt_caps;
147

148
149
	unsigned int clockrate;

150
151
152
153
	spinlock_t cc_lock;
	struct ath_cycle_counters cc_ani;
	struct ath_cycle_counters cc_survey;

154
	struct ath_regulatory regulatory;
155
	struct ath_regulatory reg_world_copy;
156
	const struct ath_ops *ops;
157
	const struct ath_bus_ops *bus_ops;
158
159

	bool btcoex_enabled;
160
	bool disable_ani;
161
162
163
164
165
166
};

struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
				u32 len,
				gfp_t gfp_mask);

167
void ath_hw_setbssidmask(struct ath_common *common);
168
169
170
171
172
173
void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
int ath_key_config(struct ath_common *common,
			  struct ieee80211_vif *vif,
			  struct ieee80211_sta *sta,
			  struct ieee80211_key_conf *key);
bool ath_hw_keyreset(struct ath_common *common, u16 entry);
174
175
void ath_hw_cycle_counters_update(struct ath_common *common);
int32_t ath_hw_get_listen_time(struct ath_common *common);
176

177
178
179
__printf(3, 4)
void ath_printk(const char *level, const struct ath_common *common,
		const char *fmt, ...);
180
181

#define ath_emerg(common, fmt, ...)				\
182
	ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
183
#define ath_alert(common, fmt, ...)				\
184
	ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
185
#define ath_crit(common, fmt, ...)				\
186
	ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
187
#define ath_err(common, fmt, ...)				\
188
	ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
189
#define ath_warn(common, fmt, ...)				\
190
	ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
191
#define ath_notice(common, fmt, ...)				\
192
	ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
193
#define ath_info(common, fmt, ...)				\
194
	ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213

/**
 * enum ath_debug_level - atheros wireless debug level
 *
 * @ATH_DBG_RESET: reset processing
 * @ATH_DBG_QUEUE: hardware queue management
 * @ATH_DBG_EEPROM: eeprom processing
 * @ATH_DBG_CALIBRATE: periodic calibration
 * @ATH_DBG_INTERRUPT: interrupt processing
 * @ATH_DBG_REGULATORY: regulatory processing
 * @ATH_DBG_ANI: adaptive noise immunitive processing
 * @ATH_DBG_XMIT: basic xmit operation
 * @ATH_DBG_BEACON: beacon handling
 * @ATH_DBG_CONFIG: configuration of the hardware
 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
 * @ATH_DBG_PS: power save processing
 * @ATH_DBG_HWTIMER: hardware timer handling
 * @ATH_DBG_BTCOEX: bluetooth coexistance
 * @ATH_DBG_BSTUCK: stuck beacons
Luis R. Rodriguez's avatar
Luis R. Rodriguez committed
214
215
216
 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
 *	used exclusively for WLAN-BT coexistence starting from
 *	AR9462.
Zefir Kurtisi's avatar
Zefir Kurtisi committed
217
 * @ATH_DBG_DFS: radar datection
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
 * @ATH_DBG_ANY: enable all debugging
 *
 * The debug level is used to control the amount and type of debugging output
 * we want to see. Each driver has its own method for enabling debugging and
 * modifying debug level states -- but this is typically done through a
 * module parameter 'debug' along with a respective 'debug' debugfs file
 * entry.
 */
enum ATH_DEBUG {
	ATH_DBG_RESET		= 0x00000001,
	ATH_DBG_QUEUE		= 0x00000002,
	ATH_DBG_EEPROM		= 0x00000004,
	ATH_DBG_CALIBRATE	= 0x00000008,
	ATH_DBG_INTERRUPT	= 0x00000010,
	ATH_DBG_REGULATORY	= 0x00000020,
	ATH_DBG_ANI		= 0x00000040,
	ATH_DBG_XMIT		= 0x00000080,
	ATH_DBG_BEACON		= 0x00000100,
	ATH_DBG_CONFIG		= 0x00000200,
	ATH_DBG_FATAL		= 0x00000400,
	ATH_DBG_PS		= 0x00000800,
	ATH_DBG_HWTIMER		= 0x00001000,
	ATH_DBG_BTCOEX		= 0x00002000,
	ATH_DBG_WMI		= 0x00004000,
	ATH_DBG_BSTUCK		= 0x00008000,
243
	ATH_DBG_MCI		= 0x00010000,
Zefir Kurtisi's avatar
Zefir Kurtisi committed
244
	ATH_DBG_DFS		= 0x00020000,
245
246
247
248
249
250
251
	ATH_DBG_ANY		= 0xffffffff
};

#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)

#ifdef CONFIG_ATH_DEBUG

Joe Perches's avatar
Joe Perches committed
252
253
#define ath_dbg(common, dbg_mask, fmt, ...)				\
do {									\
254
	if ((common)->debug_mask & ATH_DBG_##dbg_mask)			\
255
		ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__);	\
Joe Perches's avatar
Joe Perches committed
256
257
} while (0)

258
#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
259
#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
260
261
262

#else

263
static inline  __attribute__ ((format (printf, 3, 4)))
264
void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
Joe Perches's avatar
Joe Perches committed
265
	     const char *fmt, ...)
266
267
{
}
268
269
270
#define ath_dbg(common, dbg_mask, fmt, ...)				\
	_ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)

271
#define ATH_DBG_WARN(foo, arg...) do {} while (0)
272
273
274
275
#define ATH_DBG_WARN_ON_ONCE(foo) ({				\
	int __ret_warn_once = !!(foo);				\
	unlikely(__ret_warn_once);				\
})
276
277
278
279
280
281
282
283
284
285
286
287
288

#endif /* CONFIG_ATH_DEBUG */

/** Returns string describing opmode, or NULL if unknown mode. */
#ifdef CONFIG_ATH_DEBUG
const char *ath_opmode_to_string(enum nl80211_iftype opmode);
#else
static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
{
	return "UNKNOWN";
}
#endif

289
#endif /* ATH_H */