recv.c 53.3 KB
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/*
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 * Copyright (c) 2008-2011 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

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#include <linux/dma-mapping.h>
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#include "ath9k.h"
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#include "ar9003_mac.h"
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#define SKB_CB_ATHBUF(__skb)	(*((struct ath_buf **)__skb->cb))

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static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
					       int mindelta, int main_rssi_avg,
					       int alt_rssi_avg, int pkt_count)
{
	return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
		(alt_rssi_avg > main_rssi_avg + maxdelta)) ||
		(alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
}

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static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
					int curr_main_set, int curr_alt_set,
					int alt_rssi_avg, int main_rssi_avg)
{
	bool result = false;
	switch (div_group) {
	case 0:
		if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
			result = true;
		break;
	case 1:
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	case 2:
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		if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
			(curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
				(alt_rssi_avg >= (main_rssi_avg - 5))) ||
			((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
			(curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
				(alt_rssi_avg >= (main_rssi_avg - 2)))) &&
							(alt_rssi_avg >= 4))
			result = true;
		else
			result = false;
		break;
	}

	return result;
}

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static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
{
	return sc->ps_enabled &&
	       (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
}

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/*
 * Setup and link descriptors.
 *
 * 11N: we can no longer afford to self link the last descriptor.
 * MAC acknowledges BA status as long as it copies frames to host
 * buffer (or rx fifo). This can incorrectly acknowledge packets
 * to a sender if last desc is self-linked.
 */
static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	struct ath_desc *ds;
	struct sk_buff *skb;

	ATH_RXBUF_RESET(bf);

	ds = bf->bf_desc;
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	ds->ds_link = 0; /* link to null */
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	ds->ds_data = bf->bf_buf_addr;

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	/* virtual addr of the beginning of the buffer. */
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	skb = bf->bf_mpdu;
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	BUG_ON(skb == NULL);
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	ds->ds_vdata = skb->data;

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	/*
	 * setup rx descriptors. The rx_bufsize here tells the hardware
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	 * how much data it can DMA to us and that we are prepared
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	 * to process
	 */
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	ath9k_hw_setuprxdesc(ah, ds,
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			     common->rx_bufsize,
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			     0);

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	if (sc->rx.rxlink == NULL)
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		ath9k_hw_putrxbuf(ah, bf->bf_daddr);
	else
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		*sc->rx.rxlink = bf->bf_daddr;
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	sc->rx.rxlink = &ds->ds_link;
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}

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static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
{
	/* XXX block beacon interrupts */
	ath9k_hw_setantenna(sc->sc_ah, antenna);
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	sc->rx.defant = antenna;
	sc->rx.rxotherant = 0;
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}

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static void ath_opmode_init(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);

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	u32 rfilt, mfilt[2];

	/* configure rx filter */
	rfilt = ath_calcrxfilter(sc);
	ath9k_hw_setrxfilter(ah, rfilt);

	/* configure bssid mask */
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	ath_hw_setbssidmask(common);
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	/* configure operational mode */
	ath9k_hw_setopmode(ah);

	/* calculate and install multicast filter */
	mfilt[0] = mfilt[1] = ~0;
	ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
}

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static bool ath_rx_edma_buf_link(struct ath_softc *sc,
				 enum ath9k_rx_qtype qtype)
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{
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	struct ath_hw *ah = sc->sc_ah;
	struct ath_rx_edma *rx_edma;
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	struct sk_buff *skb;
	struct ath_buf *bf;

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	rx_edma = &sc->rx.rx_edma[qtype];
	if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
		return false;
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	bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
	list_del_init(&bf->list);
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	skb = bf->bf_mpdu;

	ATH_RXBUF_RESET(bf);
	memset(skb->data, 0, ah->caps.rx_status_len);
	dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
				ah->caps.rx_status_len, DMA_TO_DEVICE);
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	SKB_CB_ATHBUF(skb) = bf;
	ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
	skb_queue_tail(&rx_edma->rx_fifo, skb);
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	return true;
}

static void ath_rx_addbuffer_edma(struct ath_softc *sc,
				  enum ath9k_rx_qtype qtype, int size)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	u32 nbuf = 0;

	if (list_empty(&sc->rx.rxbuf)) {
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		ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
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		return;
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	}
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	while (!list_empty(&sc->rx.rxbuf)) {
		nbuf++;

		if (!ath_rx_edma_buf_link(sc, qtype))
			break;

		if (nbuf >= size)
			break;
	}
}

static void ath_rx_remove_buffer(struct ath_softc *sc,
				 enum ath9k_rx_qtype qtype)
{
	struct ath_buf *bf;
	struct ath_rx_edma *rx_edma;
	struct sk_buff *skb;

	rx_edma = &sc->rx.rx_edma[qtype];

	while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
		bf = SKB_CB_ATHBUF(skb);
		BUG_ON(!bf);
		list_add_tail(&bf->list, &sc->rx.rxbuf);
	}
}

static void ath_rx_edma_cleanup(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
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	struct ath_buf *bf;

	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);

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	list_for_each_entry(bf, &sc->rx.rxbuf, list) {
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		if (bf->bf_mpdu) {
			dma_unmap_single(sc->dev, bf->bf_buf_addr,
					common->rx_bufsize,
					DMA_BIDIRECTIONAL);
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			dev_kfree_skb_any(bf->bf_mpdu);
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			bf->bf_buf_addr = 0;
			bf->bf_mpdu = NULL;
		}
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	}

	INIT_LIST_HEAD(&sc->rx.rxbuf);

	kfree(sc->rx.rx_bufptr);
	sc->rx.rx_bufptr = NULL;
}

static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
{
	skb_queue_head_init(&rx_edma->rx_fifo);
	skb_queue_head_init(&rx_edma->rx_buffers);
	rx_edma->rx_fifo_hwsize = size;
}

static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct ath_hw *ah = sc->sc_ah;
	struct sk_buff *skb;
	struct ath_buf *bf;
	int error = 0, i;
	u32 size;

	ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
				    ah->caps.rx_status_len);

	ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
			       ah->caps.rx_lp_qdepth);
	ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
			       ah->caps.rx_hp_qdepth);

	size = sizeof(struct ath_buf) * nbufs;
	bf = kzalloc(size, GFP_KERNEL);
	if (!bf)
		return -ENOMEM;

	INIT_LIST_HEAD(&sc->rx.rxbuf);
	sc->rx.rx_bufptr = bf;

	for (i = 0; i < nbufs; i++, bf++) {
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		skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
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		if (!skb) {
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			error = -ENOMEM;
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			goto rx_init_fail;
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		}

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		memset(skb->data, 0, common->rx_bufsize);
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		bf->bf_mpdu = skb;
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		bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
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						 common->rx_bufsize,
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						 DMA_BIDIRECTIONAL);
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		if (unlikely(dma_mapping_error(sc->dev,
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						bf->bf_buf_addr))) {
				dev_kfree_skb_any(skb);
				bf->bf_mpdu = NULL;
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				bf->bf_buf_addr = 0;
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				ath_err(common,
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					"dma_mapping_error() on RX init\n");
				error = -ENOMEM;
				goto rx_init_fail;
		}

		list_add_tail(&bf->list, &sc->rx.rxbuf);
	}

	return 0;

rx_init_fail:
	ath_rx_edma_cleanup(sc);
	return error;
}

static void ath_edma_start_recv(struct ath_softc *sc)
{
	spin_lock_bh(&sc->rx.rxbuflock);

	ath9k_hw_rxena(sc->sc_ah);

	ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
			      sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);

	ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
			      sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);

	ath_opmode_init(sc);

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	ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
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	spin_unlock_bh(&sc->rx.rxbuflock);
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}

static void ath_edma_stop_recv(struct ath_softc *sc)
{
	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
	ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
}

int ath_rx_init(struct ath_softc *sc, int nbufs)
{
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	struct sk_buff *skb;
	struct ath_buf *bf;
	int error = 0;

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	spin_lock_init(&sc->sc_pcu_lock);
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	sc->sc_flags &= ~SC_OP_RXFLUSH;
	spin_lock_init(&sc->rx.rxbuflock);

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	common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
			     sc->sc_ah->caps.rx_status_len;

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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
		return ath_rx_edma_init(sc, nbufs);
	} else {
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		ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
			common->cachelsz, common->rx_bufsize);
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		/* Initialize rx descriptors */

		error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
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				"rx", nbufs, 1, 0);
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		if (error != 0) {
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			ath_err(common,
				"failed to allocate rx descriptors: %d\n",
				error);
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			goto err;
		}
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		list_for_each_entry(bf, &sc->rx.rxbuf, list) {
			skb = ath_rxbuf_alloc(common, common->rx_bufsize,
					      GFP_KERNEL);
			if (skb == NULL) {
				error = -ENOMEM;
				goto err;
			}

			bf->bf_mpdu = skb;
			bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
					common->rx_bufsize,
					DMA_FROM_DEVICE);
			if (unlikely(dma_mapping_error(sc->dev,
							bf->bf_buf_addr))) {
				dev_kfree_skb_any(skb);
				bf->bf_mpdu = NULL;
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				bf->bf_buf_addr = 0;
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				ath_err(common,
					"dma_mapping_error() on RX init\n");
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				error = -ENOMEM;
				goto err;
			}
		}
		sc->rx.rxlink = NULL;
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	}
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	if (error)
		ath_rx_cleanup(sc);

	return error;
}

void ath_rx_cleanup(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
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	struct sk_buff *skb;
	struct ath_buf *bf;

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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
		ath_rx_edma_cleanup(sc);
		return;
	} else {
		list_for_each_entry(bf, &sc->rx.rxbuf, list) {
			skb = bf->bf_mpdu;
			if (skb) {
				dma_unmap_single(sc->dev, bf->bf_buf_addr,
						common->rx_bufsize,
						DMA_FROM_DEVICE);
				dev_kfree_skb(skb);
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				bf->bf_buf_addr = 0;
				bf->bf_mpdu = NULL;
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			}
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		}
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		if (sc->rx.rxdma.dd_desc_len != 0)
			ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
	}
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}

/*
 * Calculate the receive filter according to the
 * operating mode and state:
 *
 * o always accept unicast, broadcast, and multicast traffic
 * o maintain current state of phy error reception (the hal
 *   may enable phy error frames for noise immunity work)
 * o probe request frames are accepted only when operating in
 *   hostap, adhoc, or monitor modes
 * o enable promiscuous mode according to the interface state
 * o accept beacons:
 *   - when operating in adhoc mode so the 802.11 layer creates
 *     node table entries for peers,
 *   - when operating in station mode for collecting rssi data when
 *     the station is otherwise quiet, or
 *   - when operating as a repeater so we see repeater-sta beacons
 *   - when scanning
 */

u32 ath_calcrxfilter(struct ath_softc *sc)
{
	u32 rfilt;

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	rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
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		| ATH9K_RX_FILTER_MCAST;

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	if (sc->rx.rxfilter & FIF_PROBE_REQ)
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		rfilt |= ATH9K_RX_FILTER_PROBEREQ;

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	/*
	 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
	 * mode interface or when in monitor mode. AP mode does not need this
	 * since it receives all in-BSS frames anyway.
	 */
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	if (sc->sc_ah->is_monitoring)
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		rfilt |= ATH9K_RX_FILTER_PROM;

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	if (sc->rx.rxfilter & FIF_CONTROL)
		rfilt |= ATH9K_RX_FILTER_CONTROL;

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	if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
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	    (sc->nvifs <= 1) &&
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	    !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
		rfilt |= ATH9K_RX_FILTER_MYBEACON;
	else
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		rfilt |= ATH9K_RX_FILTER_BEACON;

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	if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
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	    (sc->rx.rxfilter & FIF_PSPOLL))
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		rfilt |= ATH9K_RX_FILTER_PSPOLL;
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	if (conf_is_ht(&sc->hw->conf))
		rfilt |= ATH9K_RX_FILTER_COMP_BAR;

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	if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
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		/* The following may also be needed for other older chips */
		if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
			rfilt |= ATH9K_RX_FILTER_PROM;
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		rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
	}

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	return rfilt;
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#undef RX_FILTER_PRESERVE
}

int ath_startrecv(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_buf *bf, *tbf;

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	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
		ath_edma_start_recv(sc);
		return 0;
	}

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	spin_lock_bh(&sc->rx.rxbuflock);
	if (list_empty(&sc->rx.rxbuf))
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		goto start_recv;

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	sc->rx.rxlink = NULL;
	list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
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		ath_rx_buf_link(sc, bf);
	}

	/* We could have deleted elements so the list may be empty now */
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	if (list_empty(&sc->rx.rxbuf))
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		goto start_recv;

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	bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
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	ath9k_hw_putrxbuf(ah, bf->bf_daddr);
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	ath9k_hw_rxena(ah);
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start_recv:
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	ath_opmode_init(sc);
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	ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
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	spin_unlock_bh(&sc->rx.rxbuflock);

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	return 0;
}

bool ath_stoprecv(struct ath_softc *sc)
{
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	struct ath_hw *ah = sc->sc_ah;
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	bool stopped, reset = false;
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	spin_lock_bh(&sc->rx.rxbuflock);
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	ath9k_hw_abortpcurecv(ah);
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	ath9k_hw_setrxfilter(ah, 0);
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	stopped = ath9k_hw_stopdmarecv(ah, &reset);
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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
		ath_edma_stop_recv(sc);
	else
		sc->rx.rxlink = NULL;
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	spin_unlock_bh(&sc->rx.rxbuflock);
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	if (!(ah->ah_flags & AH_UNPLUGGED) &&
	    unlikely(!stopped)) {
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		ath_err(ath9k_hw_common(sc->sc_ah),
			"Could not stop RX, we could be "
			"confusing the DMA engine when we start RX up\n");
		ATH_DBG_WARN_ON_ONCE(!stopped);
	}
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	return stopped && !reset;
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}

void ath_flushrecv(struct ath_softc *sc)
{
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	sc->sc_flags |= SC_OP_RXFLUSH;
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	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
		ath_rx_tasklet(sc, 1, true);
	ath_rx_tasklet(sc, 1, false);
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	sc->sc_flags &= ~SC_OP_RXFLUSH;
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}

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static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
{
	/* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
	struct ieee80211_mgmt *mgmt;
	u8 *pos, *end, id, elen;
	struct ieee80211_tim_ie *tim;

	mgmt = (struct ieee80211_mgmt *)skb->data;
	pos = mgmt->u.beacon.variable;
	end = skb->data + skb->len;

	while (pos + 2 < end) {
		id = *pos++;
		elen = *pos++;
		if (pos + elen > end)
			break;

		if (id == WLAN_EID_TIM) {
			if (elen < sizeof(*tim))
				break;
			tim = (struct ieee80211_tim_ie *) pos;
			if (tim->dtim_count != 0)
				break;
			return tim->bitmap_ctrl & 0x01;
		}

		pos += elen;
	}

	return false;
}

static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
{
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	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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	if (skb->len < 24 + 8 + 2 + 2)
		return;

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	sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
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	if (sc->ps_flags & PS_BEACON_SYNC) {
		sc->ps_flags &= ~PS_BEACON_SYNC;
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		ath_dbg(common, ATH_DBG_PS,
			"Reconfigure Beacon timers based on timestamp from the AP\n");
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		ath_set_beacon(sc);
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	}

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	if (ath_beacon_dtim_pending_cab(skb)) {
		/*
		 * Remain awake waiting for buffered broadcast/multicast
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		 * frames. If the last broadcast/multicast frame is not
		 * received properly, the next beacon frame will work as
		 * a backup trigger for returning into NETWORK SLEEP state,
		 * so we are waiting for it as well.
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		 */
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		ath_dbg(common, ATH_DBG_PS,
			"Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
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		sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
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		return;
	}

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	if (sc->ps_flags & PS_WAIT_FOR_CAB) {
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		/*
		 * This can happen if a broadcast frame is dropped or the AP
		 * fails to send a frame indicating that all CAB frames have
		 * been delivered.
		 */
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		sc->ps_flags &= ~PS_WAIT_FOR_CAB;
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		ath_dbg(common, ATH_DBG_PS,
			"PS wait for CAB frames timed out\n");
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	}
}

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static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
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{
	struct ieee80211_hdr *hdr;
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	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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	hdr = (struct ieee80211_hdr *)skb->data;

	/* Process Beacon and CAB receive in PS state */
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	if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
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	    && mybeacon)
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		ath_rx_ps_beacon(sc, skb);
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	else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
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		 (ieee80211_is_data(hdr->frame_control) ||
		  ieee80211_is_action(hdr->frame_control)) &&
		 is_multicast_ether_addr(hdr->addr1) &&
		 !ieee80211_has_moredata(hdr->frame_control)) {
		/*
		 * No more broadcast/multicast frames to be received at this
		 * point.
		 */
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		sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
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		ath_dbg(common, ATH_DBG_PS,
			"All PS CAB frames received, back to sleep\n");
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	} else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
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		   !is_multicast_ether_addr(hdr->addr1) &&
		   !ieee80211_has_morefrags(hdr->frame_control)) {
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		sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
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		ath_dbg(common, ATH_DBG_PS,
			"Going back to sleep after having received PS-Poll data (0x%lx)\n",
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			sc->ps_flags & (PS_WAIT_FOR_BEACON |
					PS_WAIT_FOR_CAB |
					PS_WAIT_FOR_PSPOLL_DATA |
					PS_WAIT_FOR_TX_ACK));
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	}
}

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static bool ath_edma_get_buffers(struct ath_softc *sc,
				 enum ath9k_rx_qtype qtype)
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{
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	struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	struct sk_buff *skb;
	struct ath_buf *bf;
	int ret;

	skb = skb_peek(&rx_edma->rx_fifo);
	if (!skb)
		return false;

	bf = SKB_CB_ATHBUF(skb);
	BUG_ON(!bf);

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	dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
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				common->rx_bufsize, DMA_FROM_DEVICE);

	ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
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	if (ret == -EINPROGRESS) {
		/*let device gain the buffer again*/
		dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
				common->rx_bufsize, DMA_FROM_DEVICE);
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		return false;
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	}
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	__skb_unlink(skb, &rx_edma->rx_fifo);
	if (ret == -EINVAL) {
		/* corrupt descriptor, skip this one and the following one */
		list_add_tail(&bf->list, &sc->rx.rxbuf);
		ath_rx_edma_buf_link(sc, qtype);
		skb = skb_peek(&rx_edma->rx_fifo);
		if (!skb)
			return true;

		bf = SKB_CB_ATHBUF(skb);
		BUG_ON(!bf);

		__skb_unlink(skb, &rx_edma->rx_fifo);
		list_add_tail(&bf->list, &sc->rx.rxbuf);
		ath_rx_edma_buf_link(sc, qtype);
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		return true;
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	}
	skb_queue_tail(&rx_edma->rx_buffers, skb);

	return true;
}
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static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
						struct ath_rx_status *rs,
						enum ath9k_rx_qtype qtype)
{
	struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
	struct sk_buff *skb;
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	struct ath_buf *bf;
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	while (ath_edma_get_buffers(sc, qtype));
	skb = __skb_dequeue(&rx_edma->rx_buffers);
	if (!skb)
		return NULL;

	bf = SKB_CB_ATHBUF(skb);
	ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
	return bf;
}

static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
					   struct ath_rx_status *rs)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
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	struct ath_desc *ds;
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	struct ath_buf *bf;
	int ret;

	if (list_empty(&sc->rx.rxbuf)) {
		sc->rx.rxlink = NULL;
		return NULL;
	}

	bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
	ds = bf->bf_desc;

	/*
	 * Must provide the virtual address of the current
	 * descriptor, the physical address, and the virtual
	 * address of the next descriptor in the h/w chain.
	 * This allows the HAL to look ahead to see if the
	 * hardware is done with a descriptor by checking the
	 * done bit in the following descriptor and the address
	 * of the current descriptor the DMA engine is working
	 * on.  All this is necessary because of our use of
	 * a self-linked list to avoid rx overruns.
	 */
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	ret = ath9k_hw_rxprocdesc(ah, ds, rs);
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	if (ret == -EINPROGRESS) {
		struct ath_rx_status trs;
		struct ath_buf *tbf;
		struct ath_desc *tds;

		memset(&trs, 0, sizeof(trs));
		if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
			sc->rx.rxlink = NULL;
			return NULL;
		}

		tbf = list_entry(bf->list.next, struct ath_buf, list);

		/*
		 * On some hardware the descriptor status words could
		 * get corrupted, including the done bit. Because of
		 * this, check if the next descriptor's done bit is
		 * set or not.
		 *
		 * If the next descriptor's done bit is set, the current
		 * descriptor has been corrupted. Force s/w to discard
		 * this descriptor and continue...
		 */

		tds = tbf->bf_desc;
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		ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
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		if (ret == -EINPROGRESS)
			return NULL;
	}

	if (!bf->bf_mpdu)
		return bf;

	/*
	 * Synchronize the DMA transfer with CPU before
	 * 1. accessing the frame
	 * 2. requeueing the same buffer to h/w
	 */
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	dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
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			common->rx_bufsize,
			DMA_FROM_DEVICE);

	return bf;
}

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/* Assumes you've already done the endian to CPU conversion */
static bool ath9k_rx_accept(struct ath_common *common,
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			    struct ieee80211_hdr *hdr,
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			    struct ieee80211_rx_status *rxs,
			    struct ath_rx_status *rx_stats,
			    bool *decrypt_error)
{
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	struct ath_softc *sc = (struct ath_softc *) common->priv;
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	bool is_mc, is_valid_tkip, strip_mic, mic_error;
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	struct ath_hw *ah = common->ah;
	__le16 fc;
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	u8 rx_status_len = ah->caps.rx_status_len;
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	fc = hdr->frame_control;

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	is_mc = !!is_multicast_ether_addr(hdr->addr1);
	is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
		test_bit(rx_stats->rs_keyix, common->tkip_keymap);
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	strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
		!(rx_stats->rs_status &
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		(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
		 ATH9K_RXERR_KEYMISS));
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	if (!rx_stats->rs_datalen)
		return false;
        /*
         * rs_status follows rs_datalen so if rs_datalen is too large
         * we can take a hint that hardware corrupted it, so ignore
         * those frames.
         */
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	if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
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		return false;

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	/* Only use error bits from the last fragment */
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	if (rx_stats->rs_more)
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		return true;
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	mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
		!ieee80211_has_morefrags(fc) &&
		!(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
		(rx_stats->rs_status & ATH9K_RXERR_MIC);

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	/*
	 * The rx_stats->rs_status will not be set until the end of the
	 * chained descriptors so it can be ignored if rs_more is set. The
	 * rs_more will be false at the last element of the chained
	 * descriptors.
	 */
	if (rx_stats->rs_status != 0) {
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		u8 status_mask;

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		if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
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			rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
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			mic_error = false;
		}
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		if (rx_stats->rs_status & ATH9K_RXERR_PHY)
			return false;

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		if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
		    (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
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			*decrypt_error = true;
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			mic_error = false;
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		}
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		/*
		 * Reject error frames with the exception of
		 * decryption and MIC failures. For monitor mode,
		 * we also ignore the CRC error.
		 */
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		status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
			      ATH9K_RXERR_KEYMISS;

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		if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
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			status_mask |= ATH9K_RXERR_CRC;

		if (rx_stats->rs_status & ~status_mask)
			return false;
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	}
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	/*
	 * For unicast frames the MIC error bit can have false positives,
	 * so all MIC error reports need to be validated in software.
	 * False negatives are not common, so skip software verification
	 * if the hardware considers the MIC valid.
	 */
	if (strip_mic)
		rxs->flag |= RX_FLAG_MMIC_STRIPPED;
	else if (is_mc && mic_error)
		rxs->flag |= RX_FLAG_MMIC_ERROR;

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	return true;
}

static int ath9k_process_rate(struct ath_common *common,
			      struct ieee80211_hw *hw,
			      struct ath_rx_status *rx_stats,
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			      struct ieee80211_rx_status *rxs)
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{
	struct ieee80211_supported_band *sband;
	enum ieee80211_band band;
	unsigned int i = 0;

	band = hw->conf.channel->band;
	sband = hw->wiphy->bands[band];

	if (rx_stats->rs_rate & 0x80) {
		/* HT rate */
		rxs->flag |= RX_FLAG_HT;
		if (rx_stats->rs_flags & ATH9K_RX_2040)
			rxs->flag |= RX_FLAG_40MHZ;
		if (rx_stats->rs_flags & ATH9K_RX_GI)
			rxs->flag |= RX_FLAG_SHORT_GI;
		rxs->rate_idx = rx_stats->rs_rate & 0x7f;
		return 0;
	}

	for (i = 0; i < sband->n_bitrates; i++) {
		if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
			rxs->rate_idx = i;
			return 0;
		}
		if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
			rxs->flag |= RX_FLAG_SHORTPRE;
			rxs->rate_idx = i;
			return 0;
		}
	}

	/*
	 * No valid hardware bitrate found -- we should not get here
	 * because hardware has already validated this frame as OK.
	 */
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		"unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
		rx_stats->rs_rate);
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	return -EINVAL;
}

static void ath9k_process_rssi(struct ath_common *common,
			       struct ieee80211_hw *hw,
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			       struct ieee80211_hdr *hdr,
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			       struct ath_rx_status *rx_stats)
{
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	struct ath_softc *sc = hw->priv;
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	struct ath_hw *ah = common->ah;
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	int last_rssi;
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	if (!rx_stats->is_mybeacon ||
	    ((ah->opmode != NL80211_IFTYPE_STATION) &&
	     (ah->opmode != NL80211_IFTYPE_ADHOC)))
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		return;

	if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
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		ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
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	last_rssi = sc->last_rssi;
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	if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
		rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
					      ATH_RSSI_EP_MULTIPLIER);
	if (rx_stats->rs_rssi < 0)
		rx_stats->rs_rssi = 0;

	/* Update Beacon RSSI, this is used by ANI. */
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	ah->stats.avgbrssi = rx_stats->rs_rssi;
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}

/*
 * For Decrypt or Demic errors, we only mark packet status here and always push
 * up the frame up to let mac80211 handle the actual error case, be it no
 * decryption key or real decryption error. This let us keep statistics there.
 */
static int ath9k_rx_skb_preprocess(struct ath_common *common,
				   struct ieee80211_hw *hw,
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				   struct ieee80211_hdr *hdr,
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				   struct ath_rx_status *rx_stats,
				   struct ieee80211_rx_status *rx_status,
				   bool *decrypt_error)
{
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	struct ath_hw *ah = common->ah;

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	memset(rx_status, 0, sizeof(struct ieee80211_rx_status));

	/*
	 * everything but the rate is checked here, the rate check is done
	 * separately to avoid doing two lookups for a rate for each frame.
	 */
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	if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
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		return -EINVAL;

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	/* Only use status info from the last fragment */
	if (rx_stats->rs_more)
		return 0;

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	ath9k_process_rssi(common, hw, hdr, rx_stats);
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	if (ath9k_process_rate(common, hw, rx_stats, rx_status))
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