xmit.c 62.7 KB
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

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#include "ath9k.h"
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#include "ar9003_mac.h"
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#define BITS_PER_BYTE           8
#define OFDM_PLCP_BITS          22
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#define HT_RC_2_MCS(_rc)        ((_rc) & 0x1f)
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#define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
#define L_STF                   8
#define L_LTF                   8
#define L_SIG                   4
#define HT_SIG                  8
#define HT_STF                  4
#define HT_LTF(_ns)             (4 * (_ns))
#define SYMBOL_TIME(_ns)        ((_ns) << 2) /* ns * 4 us */
#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)  /* ns * 3.6 us */
#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)

#define OFDM_SIFS_TIME    	    16

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static u16 bits_per_symbol[][2] = {
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	/* 20MHz 40MHz */
	{    26,   54 },     /*  0: BPSK */
	{    52,  108 },     /*  1: QPSK 1/2 */
	{    78,  162 },     /*  2: QPSK 3/4 */
	{   104,  216 },     /*  3: 16-QAM 1/2 */
	{   156,  324 },     /*  4: 16-QAM 3/4 */
	{   208,  432 },     /*  5: 64-QAM 2/3 */
	{   234,  486 },     /*  6: 64-QAM 3/4 */
	{   260,  540 },     /*  7: 64-QAM 5/6 */
};

#define IS_HT_RATE(_rate)     ((_rate) & 0x80)

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static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
				  struct ath_atx_tid *tid,
				  struct list_head *bf_head);
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static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
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				struct ath_txq *txq, struct list_head *bf_q,
				struct ath_tx_status *ts, int txok, int sendbar);
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static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
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			     struct list_head *head);
static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
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static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
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			      struct ath_tx_status *ts, int txok);
static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
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			     int nbad, int txok, bool update_rc);
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enum {
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	MCS_HT20,
	MCS_HT20_SGI,
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	MCS_HT40,
	MCS_HT40_SGI,
};

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static int ath_max_4ms_framelen[4][32] = {
	[MCS_HT20] = {
		3212,  6432,  9648,  12864,  19300,  25736,  28952,  32172,
		6424,  12852, 19280, 25708,  38568,  51424,  57852,  64280,
		9628,  19260, 28896, 38528,  57792,  65532,  65532,  65532,
		12828, 25656, 38488, 51320,  65532,  65532,  65532,  65532,
	},
	[MCS_HT20_SGI] = {
		3572,  7144,  10720,  14296,  21444,  28596,  32172,  35744,
		7140,  14284, 21428,  28568,  42856,  57144,  64288,  65532,
		10700, 21408, 32112,  42816,  64228,  65532,  65532,  65532,
		14256, 28516, 42780,  57040,  65532,  65532,  65532,  65532,
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	},
	[MCS_HT40] = {
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		6680,  13360,  20044,  26724,  40092,  53456,  60140,  65532,
		13348, 26700,  40052,  53400,  65532,  65532,  65532,  65532,
		20004, 40008,  60016,  65532,  65532,  65532,  65532,  65532,
		26644, 53292,  65532,  65532,  65532,  65532,  65532,  65532,
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	},
	[MCS_HT40_SGI] = {
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		7420,  14844,  22272,  29696,  44544,  59396,  65532,  65532,
		14832, 29668,  44504,  59340,  65532,  65532,  65532,  65532,
		22232, 44464,  65532,  65532,  65532,  65532,  65532,  65532,
		29616, 59232,  65532,  65532,  65532,  65532,  65532,  65532,
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	}
};

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/*********************/
/* Aggregation logic */
/*********************/
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static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
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{
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	struct ath_atx_ac *ac = tid->ac;
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	if (tid->paused)
		return;
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	if (tid->sched)
		return;
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	tid->sched = true;
	list_add_tail(&tid->list, &ac->tid_q);
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	if (ac->sched)
		return;
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	ac->sched = true;
	list_add_tail(&ac->list, &txq->axq_acq);
}
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static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
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{
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	struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
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	WARN_ON(!tid->paused);
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	spin_lock_bh(&txq->axq_lock);
	tid->paused = false;
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	if (list_empty(&tid->buf_q))
		goto unlock;
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	ath_tx_queue_tid(txq, tid);
	ath_txq_schedule(sc, txq);
unlock:
	spin_unlock_bh(&txq->axq_lock);
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}
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static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
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{
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	struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
	struct ath_buf *bf;
	struct list_head bf_head;
	INIT_LIST_HEAD(&bf_head);
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	WARN_ON(!tid->paused);
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	spin_lock_bh(&txq->axq_lock);
	tid->paused = false;
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	while (!list_empty(&tid->buf_q)) {
		bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
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		BUG_ON(bf_isretried(bf));
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		list_move_tail(&bf->list, &bf_head);
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		ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
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	}
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	spin_unlock_bh(&txq->axq_lock);
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}
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static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
			      int seqno)
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{
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	int index, cindex;
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	index  = ATH_BA_INDEX(tid->seq_start, seqno);
	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
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	__clear_bit(cindex, tid->tx_buf);
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	while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
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		INCR(tid->seq_start, IEEE80211_SEQ_MAX);
		INCR(tid->baw_head, ATH_TID_MAX_BUFS);
	}
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}
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static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
			     struct ath_buf *bf)
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{
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	int index, cindex;
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	if (bf_isretried(bf))
		return;
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	index  = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
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	__set_bit(cindex, tid->tx_buf);
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	if (index >= ((tid->baw_tail - tid->baw_head) &
		(ATH_TID_MAX_BUFS - 1))) {
		tid->baw_tail = cindex;
		INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
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	}
}

/*
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 * TODO: For frame(s) that are in the retry state, we will reuse the
 * sequence number(s) without setting the retry bit. The
 * alternative is to give up on these and BAR the receiver's window
 * forward.
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 */
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static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
			  struct ath_atx_tid *tid)
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{
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	struct ath_buf *bf;
	struct list_head bf_head;
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	struct ath_tx_status ts;

	memset(&ts, 0, sizeof(ts));
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	INIT_LIST_HEAD(&bf_head);
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	for (;;) {
		if (list_empty(&tid->buf_q))
			break;
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		bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
		list_move_tail(&bf->list, &bf_head);
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		if (bf_isretried(bf))
			ath_tx_update_baw(sc, tid, bf->bf_seqno);
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		spin_unlock(&txq->axq_lock);
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		ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
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		spin_lock(&txq->axq_lock);
	}
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	tid->seq_next = tid->seq_start;
	tid->baw_tail = tid->baw_head;
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}

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static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
			     struct ath_buf *bf)
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{
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	struct sk_buff *skb;
	struct ieee80211_hdr *hdr;
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	bf->bf_state.bf_type |= BUF_RETRY;
	bf->bf_retries++;
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	TX_STAT_INC(txq->axq_qnum, a_retries);
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	skb = bf->bf_mpdu;
	hdr = (struct ieee80211_hdr *)skb->data;
	hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
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}

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static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
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{
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	struct ath_buf *bf = NULL;
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	spin_lock_bh(&sc->tx.txbuflock);
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	if (unlikely(list_empty(&sc->tx.txbuf))) {
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		spin_unlock_bh(&sc->tx.txbuflock);
		return NULL;
	}
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	bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
	list_del(&bf->list);

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	spin_unlock_bh(&sc->tx.txbuflock);

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	return bf;
}

static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
{
	spin_lock_bh(&sc->tx.txbuflock);
	list_add_tail(&bf->list, &sc->tx.txbuf);
	spin_unlock_bh(&sc->tx.txbuflock);
}

static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
{
	struct ath_buf *tbf;

	tbf = ath_tx_get_buffer(sc);
	if (WARN_ON(!tbf))
		return NULL;

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	ATH_TXBUF_RESET(tbf);

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	tbf->aphy = bf->aphy;
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	tbf->bf_mpdu = bf->bf_mpdu;
	tbf->bf_buf_addr = bf->bf_buf_addr;
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	memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
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	tbf->bf_state = bf->bf_state;
	tbf->bf_dmacontext = bf->bf_dmacontext;

	return tbf;
}

static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
				 struct ath_buf *bf, struct list_head *bf_q,
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				 struct ath_tx_status *ts, int txok)
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{
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	struct ath_node *an = NULL;
	struct sk_buff *skb;
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	struct ieee80211_sta *sta;
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	struct ieee80211_hw *hw;
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	struct ieee80211_hdr *hdr;
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	struct ieee80211_tx_info *tx_info;
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	struct ath_atx_tid *tid = NULL;
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	struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
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	struct list_head bf_head, bf_pending;
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	u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
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	u32 ba[WME_BA_BMP_SIZE >> 5];
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	int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
	bool rc_update = true;
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	struct ieee80211_tx_rate rates[4];
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	skb = bf->bf_mpdu;
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	hdr = (struct ieee80211_hdr *)skb->data;

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	tx_info = IEEE80211_SKB_CB(skb);
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	hw = bf->aphy->hw;
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	memcpy(rates, tx_info->control.rates, sizeof(rates));

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	rcu_read_lock();
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	/* XXX: use ieee80211_find_sta! */
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	sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
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	if (!sta) {
		rcu_read_unlock();
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		INIT_LIST_HEAD(&bf_head);
		while (bf) {
			bf_next = bf->bf_next;

			bf->bf_state.bf_type |= BUF_XRETRY;
			if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
			    !bf->bf_stale || bf_next != NULL)
				list_move_tail(&bf->list, &bf_head);

			ath_tx_rc_status(bf, ts, 0, 0, false);
			ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
				0, 0);

			bf = bf_next;
		}
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		return;
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	}

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	an = (struct ath_node *)sta->drv_priv;
	tid = ATH_AN_2_TID(an, bf->bf_tidno);

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	/*
	 * The hardware occasionally sends a tx status for the wrong TID.
	 * In this case, the BA status cannot be considered valid and all
	 * subframes need to be retransmitted
	 */
	if (bf->bf_tidno != ts->tid)
		txok = false;

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	isaggr = bf_isaggr(bf);
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	memset(ba, 0, WME_BA_BMP_SIZE >> 3);
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	if (isaggr && txok) {
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		if (ts->ts_flags & ATH9K_TX_BA) {
			seq_st = ts->ts_seqnum;
			memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
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		} else {
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			/*
			 * AR5416 can become deaf/mute when BA
			 * issue happens. Chip needs to be reset.
			 * But AP code may have sychronization issues
			 * when perform internal reset in this routine.
			 * Only enable reset in STA mode for now.
			 */
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			if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
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				needreset = 1;
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		}
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	}

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	INIT_LIST_HEAD(&bf_pending);
	INIT_LIST_HEAD(&bf_head);
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	nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
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	while (bf) {
		txfail = txpending = 0;
		bf_next = bf->bf_next;
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		skb = bf->bf_mpdu;
		tx_info = IEEE80211_SKB_CB(skb);

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		if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
			/* transmit completion, subframe is
			 * acked by block ack */
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			acked_cnt++;
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		} else if (!isaggr && txok) {
			/* transmit completion */
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			acked_cnt++;
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		} else {
			if (!(tid->state & AGGR_CLEANUP) &&
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			    !bf_last->bf_tx_aborted) {
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				if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
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					ath_tx_set_retry(sc, txq, bf);
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					txpending = 1;
				} else {
					bf->bf_state.bf_type |= BUF_XRETRY;
					txfail = 1;
					sendbar = 1;
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					txfail_cnt++;
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				}
			} else {
				/*
				 * cleanup in progress, just fail
				 * the un-acked sub-frames
				 */
				txfail = 1;
			}
		}
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		if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
		    bf_next == NULL) {
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			/*
			 * Make sure the last desc is reclaimed if it
			 * not a holding desc.
			 */
			if (!bf_last->bf_stale)
				list_move_tail(&bf->list, &bf_head);
			else
				INIT_LIST_HEAD(&bf_head);
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		} else {
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			BUG_ON(list_empty(bf_q));
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			list_move_tail(&bf->list, &bf_head);
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		}
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		if (!txpending) {
			/*
			 * complete the acked-ones/xretried ones; update
			 * block-ack window
			 */
			spin_lock_bh(&txq->axq_lock);
			ath_tx_update_baw(sc, tid, bf->bf_seqno);
			spin_unlock_bh(&txq->axq_lock);
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			if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
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				memcpy(tx_info->control.rates, rates, sizeof(rates));
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				ath_tx_rc_status(bf, ts, nbad, txok, true);
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				rc_update = false;
			} else {
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				ath_tx_rc_status(bf, ts, nbad, txok, false);
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			}

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			ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
				!txfail, sendbar);
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		} else {
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			/* retry the un-acked ones */
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			if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
				if (bf->bf_next == NULL && bf_last->bf_stale) {
					struct ath_buf *tbf;

					tbf = ath_clone_txbuf(sc, bf_last);
					/*
					 * Update tx baw and complete the
					 * frame with failed status if we
					 * run out of tx buf.
					 */
					if (!tbf) {
						spin_lock_bh(&txq->axq_lock);
						ath_tx_update_baw(sc, tid,
								bf->bf_seqno);
						spin_unlock_bh(&txq->axq_lock);

						bf->bf_state.bf_type |=
							BUF_XRETRY;
						ath_tx_rc_status(bf, ts, nbad,
								0, false);
						ath_tx_complete_buf(sc, bf, txq,
								    &bf_head,
								    ts, 0, 0);
						break;
					}

					ath9k_hw_cleartxdesc(sc->sc_ah,
							     tbf->bf_desc);
					list_add_tail(&tbf->list, &bf_head);
				} else {
					/*
					 * Clear descriptor status words for
					 * software retry
					 */
					ath9k_hw_cleartxdesc(sc->sc_ah,
							     bf->bf_desc);
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				}
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			}

			/*
			 * Put this buffer to the temporary pending
			 * queue to retain ordering
			 */
			list_splice_tail_init(&bf_head, &bf_pending);
		}

		bf = bf_next;
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	}

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	/* prepend un-acked frames to the beginning of the pending frame queue */
	if (!list_empty(&bf_pending)) {
		spin_lock_bh(&txq->axq_lock);
		list_splice(&bf_pending, &tid->buf_q);
		ath_tx_queue_tid(txq, tid);
		spin_unlock_bh(&txq->axq_lock);
	}

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	if (tid->state & AGGR_CLEANUP) {
		if (tid->baw_head == tid->baw_tail) {
			tid->state &= ~AGGR_ADDBA_COMPLETE;
			tid->state &= ~AGGR_CLEANUP;
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			/* send buffered frames as singles */
			ath_tx_flush_tid(sc, tid);
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		}
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		rcu_read_unlock();
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		return;
	}
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	rcu_read_unlock();

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	if (needreset)
		ath_reset(sc, false);
}
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static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
			   struct ath_atx_tid *tid)
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{
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	struct sk_buff *skb;
	struct ieee80211_tx_info *tx_info;
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	struct ieee80211_tx_rate *rates;
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	u32 max_4ms_framelen, frmlen;
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	u16 aggr_limit, legacy = 0;
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	int i;
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	skb = bf->bf_mpdu;
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	tx_info = IEEE80211_SKB_CB(skb);
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	rates = tx_info->control.rates;
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	/*
	 * Find the lowest frame length among the rate series that will have a
	 * 4ms transmit duration.
	 * TODO - TXOP limit needs to be considered.
	 */
	max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
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	for (i = 0; i < 4; i++) {
		if (rates[i].count) {
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			int modeidx;
			if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
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				legacy = 1;
				break;
			}

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			if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
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				modeidx = MCS_HT40;
			else
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				modeidx = MCS_HT20;

			if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
				modeidx++;
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			frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
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			max_4ms_framelen = min(max_4ms_framelen, frmlen);
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		}
	}
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	/*
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	 * limit aggregate size by the minimum rate if rate selected is
	 * not a probe rate, if rate selected is a probe rate then
	 * avoid aggregation of this packet.
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	 */
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	if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
		return 0;
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	if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
		aggr_limit = min((max_4ms_framelen * 3) / 8,
				 (u32)ATH_AMPDU_LIMIT_MAX);
	else
		aggr_limit = min(max_4ms_framelen,
				 (u32)ATH_AMPDU_LIMIT_MAX);
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	/*
	 * h/w can accept aggregates upto 16 bit lengths (65535).
	 * The IE, however can hold upto 65536, which shows up here
	 * as zero. Ignore 65536 since we  are constrained by hw.
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	 */
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	if (tid->an->maxampdu)
		aggr_limit = min(aggr_limit, tid->an->maxampdu);
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	return aggr_limit;
}
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/*
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 * Returns the number of delimiters to be added to
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 * meet the minimum required mpdudensity.
 */
static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
				  struct ath_buf *bf, u16 frmlen)
{
	struct sk_buff *skb = bf->bf_mpdu;
	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
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	u32 nsymbits, nsymbols;
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	u16 minlen;
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	u8 flags, rix;
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	int width, streams, half_gi, ndelim, mindelim;
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	/* Select standard number of delimiters based on frame length alone */
	ndelim = ATH_AGGR_GET_NDELIM(frmlen);
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	/*
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	 * If encryption enabled, hardware requires some more padding between
	 * subframes.
	 * TODO - this could be improved to be dependent on the rate.
	 *      The hardware can keep up at lower rates, but not higher rates
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	 */
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	if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
		ndelim += ATH_AGGR_ENCRYPTDELIM;
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	/*
	 * Convert desired mpdu density from microeconds to bytes based
	 * on highest rate in rate series (i.e. first rate) to determine
	 * required minimum length for subframe. Take into account
	 * whether high rate is 20 or 40Mhz and half or full GI.
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	 *
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	 * If there is no mpdu density restriction, no further calculation
	 * is needed.
	 */
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	if (tid->an->mpdudensity == 0)
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		return ndelim;
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	rix = tx_info->control.rates[0].idx;
	flags = tx_info->control.rates[0].flags;
	width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
	half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
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	if (half_gi)
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		nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
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	else
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		nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
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	if (nsymbols == 0)
		nsymbols = 1;
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	streams = HT_RC_2_STREAMS(rix);
	nsymbits = bits_per_symbol[rix % 8][width] * streams;
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	minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
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	if (frmlen < minlen) {
		mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
		ndelim = max(mindelim, ndelim);
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	}

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	return ndelim;
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}

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static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
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					     struct ath_txq *txq,
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					     struct ath_atx_tid *tid,
					     struct list_head *bf_q)
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{
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#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
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	struct ath_buf *bf, *bf_first, *bf_prev = NULL;
	int rl = 0, nframes = 0, ndelim, prev_al = 0;
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	u16 aggr_limit = 0, al = 0, bpad = 0,
		al_delta, h_baw = tid->baw_size / 2;
	enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
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	bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
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	do {
		bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
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		/* do not step over block-ack window */
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		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
			status = ATH_AGGR_BAW_CLOSED;
			break;
		}
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		if (!rl) {
			aggr_limit = ath_lookup_rate(sc, bf, tid);
			rl = 1;
		}
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		/* do not exceed aggregation limit */
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		al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
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		if (nframes &&
		    (aggr_limit < (al + bpad + al_delta + prev_al))) {
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			status = ATH_AGGR_LIMITED;
			break;
		}
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		/* do not exceed subframe limit */
		if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
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			status = ATH_AGGR_LIMITED;
			break;
		}
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		nframes++;
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		/* add padding for previous frame to aggregation length */
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		al += bpad + al_delta;
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		/*
		 * Get the delimiters needed to meet the MPDU
		 * density for this node.
		 */
		ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
		bpad = PADBYTES(al_delta) + (ndelim << 2);
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		bf->bf_next = NULL;
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		ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
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		/* link buffers of this frame to the aggregate */
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		ath_tx_addto_baw(sc, tid, bf);
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		ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
		list_move_tail(&bf->list, bf_q);
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		if (bf_prev) {
			bf_prev->bf_next = bf;
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			ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
					       bf->bf_daddr);
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		}
		bf_prev = bf;
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	} while (!list_empty(&tid->buf_q));
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	bf_first->bf_al = al;
	bf_first->bf_nframes = nframes;
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	return status;
#undef PADBYTES
}
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static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
			      struct ath_atx_tid *tid)
{
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	struct ath_buf *bf;
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	enum ATH_AGGR_STATUS status;
	struct list_head bf_q;
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	do {
		if (list_empty(&tid->buf_q))
			return;
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		INIT_LIST_HEAD(&bf_q);

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		status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
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		/*
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		 * no frames picked up to be aggregated;
		 * block-ack window is not open.
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		 */
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		if (list_empty(&bf_q))
			break;
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		bf = list_first_entry(&bf_q, struct ath_buf, list);
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		bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
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		/* if only one frame, send as non-aggregate */
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		if (bf->bf_nframes == 1) {
			bf->bf_state.bf_type &= ~BUF_AGGR;
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			ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
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			ath_buf_set_rate(sc, bf);
			ath_tx_txqaddbuf(sc, txq, &bf_q);
			continue;
		}
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		/* setup first desc of aggregate */
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		bf->bf_state.bf_type |= BUF_AGGR;
		ath_buf_set_rate(sc, bf);
		ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
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		/* anchor last desc of aggregate */
		ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
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		ath_tx_txqaddbuf(sc, txq, &bf_q);
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		TX_STAT_INC(txq->axq_qnum, a_aggr);
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	} while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
		 status != ATH_AGGR_BAW_CLOSED);
}

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void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
		       u16 tid, u16 *ssn)
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{
	struct ath_atx_tid *txtid;
	struct ath_node *an;

	an = (struct ath_node *)sta->drv_priv;
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	txtid = ATH_AN_2_TID(an, tid);
	txtid->state |= AGGR_ADDBA_PROGRESS;
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	txtid->paused = true;
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	*ssn = txtid->seq_start;
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}
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void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
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{
	struct ath_node *an = (struct ath_node *)sta->drv_priv;
	struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
	struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
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	struct ath_tx_status ts;
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	struct ath_buf *bf;
	struct list_head bf_head;
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	memset(&ts, 0, sizeof(ts));
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	INIT_LIST_HEAD(&bf_head);
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	if (txtid->state & AGGR_CLEANUP)
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		return;
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	if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
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		txtid->state &= ~AGGR_ADDBA_PROGRESS;
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		return;
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	}
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	/* drop all software retried frames and mark this TID */
	spin_lock_bh(&txq->axq_lock);
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	txtid->paused = true;
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	while (!list_empty(&txtid->buf_q)) {
		bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
		if (!bf_isretried(bf)) {
			/*
			 * NB: it's based on the assumption that
			 * software retried frame will always stay
			 * at the head of software queue.
			 */
			break;
		}
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		list_move_tail(&bf->list, &bf_head);
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		ath_tx_update_baw(sc, txtid, bf->bf_seqno);
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		ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
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	}
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	spin_unlock_bh(&txq->axq_lock);
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	if (txtid->baw_head != txtid->baw_tail) {
		txtid->state |= AGGR_CLEANUP;
	} else {
		txtid->state &= ~AGGR_ADDBA_COMPLETE;
		ath_tx_flush_tid(sc, txtid);
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	}
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}
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void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
{
	struct ath_atx_tid *txtid;
	struct ath_node *an;

	an = (struct ath_node *)sta->drv_priv;

	if (sc->sc_flags & SC_OP_TXAGGR) {
		txtid = ATH_AN_2_TID(an, tid);
		txtid->baw_size =
			IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
		txtid->state |= AGGR_ADDBA_COMPLETE;
		txtid->state &= ~AGGR_ADDBA_PROGRESS;
		ath_tx_resume_tid(sc, txtid);
	}
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}

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bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
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{
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	struct ath_atx_tid *txtid;
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	if (!(sc->sc_flags & SC_OP_TXAGGR))
		return false;
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	txtid = ATH_AN_2_TID(an, tidno);

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	if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
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			return true;
	return false;
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}

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/********************/
/* Queue Management */
/********************/
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static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
					  struct ath_txq *txq)
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{
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	struct ath_atx_ac *ac, *ac_tmp;
	struct ath_atx_tid *tid, *tid_tmp;
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	list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
		list_del(&ac->list);
		ac->sched = false;
		list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
			list_del(&tid->list);
			tid->sched = false;
			ath_tid_drain(sc, txq, tid);
		}
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	}
}

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struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
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{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	struct ath9k_tx_queue_info qi;
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	int qnum, i;
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	memset(&qi, 0, sizeof(qi));
	qi.tqi_subtype = subtype;
	qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
	qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
	qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
	qi.tqi_physCompBuf = 0;
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	/*
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	 * Enable interrupts only for EOL and DESC conditions.
	 * We mark tx descriptors to receive a DESC interrupt
	 * when a tx queue gets deep; otherwise waiting for the
	 * EOL to reap descriptors.  Note that this is done to
	 * reduce interrupt load and this only defers reaping
	 * descriptors, never transmitting frames.  Aside from
	 * reducing interrupts this also permits more concurrency.
	 * The only potential downside is if the tx queue backs
	 * up in which case the top half of the kernel may backup
	 * due to a lack of tx descriptors.
	 *
	 * The UAPSD queue is an exception, since we take a desc-
	 * based intr on the EOSP frames.
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	 */
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	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
		qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
				TXQ_FLAG_TXERRINT_ENABLE;
	} else {
		if (qtype == ATH9K_TX_QUEUE_UAPSD)
			qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
		else
			qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
					TXQ_FLAG_TXDESCINT_ENABLE;
	}
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	qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
	if (qnum == -1) {
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		/*
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		 * NB: don't print a message, this happens
		 * normally on parts with too few tx queues
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		 */