at32ap700x.c 51.8 KB
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/*
 * Copyright (C) 2005-2006 Atmel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/init.h>
#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/spi/spi.h>
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#include <linux/usb/atmel_usba_udc.h>
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#include <asm/atmel-mci.h>
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#include <asm/io.h>
Haavard Skinnemoen's avatar
Haavard Skinnemoen committed
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#include <asm/irq.h>
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#include <asm/arch/at32ap700x.h>
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#include <asm/arch/board.h>
#include <asm/arch/portmux.h>
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#include <asm/arch/sram.h>
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#include <video/atmel_lcdc.h>

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#include "clock.h"
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#include "hmatrix.h"
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#include "pio.h"
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#include "pm.h"

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#define PBMEM(base)					\
	{						\
		.start		= base,			\
		.end		= base + 0x3ff,		\
		.flags		= IORESOURCE_MEM,	\
	}
#define IRQ(num)					\
	{						\
		.start		= num,			\
		.end		= num,			\
		.flags		= IORESOURCE_IRQ,	\
	}
#define NAMED_IRQ(num, _name)				\
	{						\
		.start		= num,			\
		.end		= num,			\
		.name		= _name,		\
		.flags		= IORESOURCE_IRQ,	\
	}

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/* REVISIT these assume *every* device supports DMA, but several
 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
 */
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#define DEFINE_DEV(_name, _id)					\
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static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;		\
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static struct platform_device _name##_id##_device = {		\
	.name		= #_name,				\
	.id		= _id,					\
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	.dev		= {					\
		.dma_mask = &_name##_id##_dma_mask,		\
		.coherent_dma_mask = DMA_32BIT_MASK,		\
	},							\
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	.resource	= _name##_id##_resource,		\
	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
}
#define DEFINE_DEV_DATA(_name, _id)				\
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static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;		\
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static struct platform_device _name##_id##_device = {		\
	.name		= #_name,				\
	.id		= _id,					\
	.dev		= {					\
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		.dma_mask = &_name##_id##_dma_mask,		\
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		.platform_data	= &_name##_id##_data,		\
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		.coherent_dma_mask = DMA_32BIT_MASK,		\
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	},							\
	.resource	= _name##_id##_resource,		\
	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
}

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#define select_peripheral(pin, periph, flags)			\
	at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)

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#define DEV_CLK(_name, devname, bus, _index)			\
static struct clk devname##_##_name = {				\
	.name		= #_name,				\
	.dev		= &devname##_device.dev,		\
	.parent		= &bus##_clk,				\
	.mode		= bus##_clk_mode,			\
	.get_rate	= bus##_clk_get_rate,			\
	.index		= _index,				\
}

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static DEFINE_SPINLOCK(pm_lock);

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static struct clk osc0;
static struct clk osc1;

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static unsigned long osc_get_rate(struct clk *clk)
{
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	return at32_board_osc_rates[clk->index];
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}

static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
{
	unsigned long div, mul, rate;

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	div = PM_BFEXT(PLLDIV, control) + 1;
	mul = PM_BFEXT(PLLMUL, control) + 1;
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	rate = clk->parent->get_rate(clk->parent);
	rate = (rate + div / 2) / div;
	rate *= mul;

	return rate;
}

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static long pll_set_rate(struct clk *clk, unsigned long rate,
			 u32 *pll_ctrl)
{
	unsigned long mul;
	unsigned long mul_best_fit = 0;
	unsigned long div;
	unsigned long div_min;
	unsigned long div_max;
	unsigned long div_best_fit = 0;
	unsigned long base;
	unsigned long pll_in;
	unsigned long actual = 0;
	unsigned long rate_error;
	unsigned long rate_error_prev = ~0UL;
	u32 ctrl;

	/* Rate must be between 80 MHz and 200 Mhz. */
	if (rate < 80000000UL || rate > 200000000UL)
		return -EINVAL;

	ctrl = PM_BF(PLLOPT, 4);
	base = clk->parent->get_rate(clk->parent);

	/* PLL input frequency must be between 6 MHz and 32 MHz. */
	div_min = DIV_ROUND_UP(base, 32000000UL);
	div_max = base / 6000000UL;

	if (div_max < div_min)
		return -EINVAL;

	for (div = div_min; div <= div_max; div++) {
		pll_in = (base + div / 2) / div;
		mul = (rate + pll_in / 2) / pll_in;

		if (mul == 0)
			continue;

		actual = pll_in * mul;
		rate_error = abs(actual - rate);

		if (rate_error < rate_error_prev) {
			mul_best_fit = mul;
			div_best_fit = div;
			rate_error_prev = rate_error;
		}

		if (rate_error == 0)
			break;
	}

	if (div_best_fit == 0)
		return -EINVAL;

	ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
	ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
	ctrl |= PM_BF(PLLCOUNT, 16);

	if (clk->parent == &osc1)
		ctrl |= PM_BIT(PLLOSC);

	*pll_ctrl = ctrl;

	return actual;
}

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static unsigned long pll0_get_rate(struct clk *clk)
{
	u32 control;

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	control = pm_readl(PLL0);
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	return pll_get_rate(clk, control);
}

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static void pll1_mode(struct clk *clk, int enabled)
{
	unsigned long timeout;
	u32 status;
	u32 ctrl;

	ctrl = pm_readl(PLL1);

	if (enabled) {
		if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
			pr_debug("clk %s: failed to enable, rate not set\n",
					clk->name);
			return;
		}

		ctrl |= PM_BIT(PLLEN);
		pm_writel(PLL1, ctrl);

		/* Wait for PLL lock. */
		for (timeout = 10000; timeout; timeout--) {
			status = pm_readl(ISR);
			if (status & PM_BIT(LOCK1))
				break;
			udelay(10);
		}

		if (!(status & PM_BIT(LOCK1)))
			printk(KERN_ERR "clk %s: timeout waiting for lock\n",
					clk->name);
	} else {
		ctrl &= ~PM_BIT(PLLEN);
		pm_writel(PLL1, ctrl);
	}
}

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static unsigned long pll1_get_rate(struct clk *clk)
{
	u32 control;

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	control = pm_readl(PLL1);
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	return pll_get_rate(clk, control);
}

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static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
{
	u32 ctrl = 0;
	unsigned long actual_rate;

	actual_rate = pll_set_rate(clk, rate, &ctrl);

	if (apply) {
		if (actual_rate != rate)
			return -EINVAL;
		if (clk->users > 0)
			return -EBUSY;
		pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
				clk->name, rate, actual_rate);
		pm_writel(PLL1, ctrl);
	}

	return actual_rate;
}

static int pll1_set_parent(struct clk *clk, struct clk *parent)
{
	u32 ctrl;

	if (clk->users > 0)
		return -EBUSY;

	ctrl = pm_readl(PLL1);
	WARN_ON(ctrl & PM_BIT(PLLEN));

	if (parent == &osc0)
		ctrl &= ~PM_BIT(PLLOSC);
	else if (parent == &osc1)
		ctrl |= PM_BIT(PLLOSC);
	else
		return -EINVAL;

	pm_writel(PLL1, ctrl);
	clk->parent = parent;

	return 0;
}

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/*
 * The AT32AP7000 has five primary clock sources: One 32kHz
 * oscillator, two crystal oscillators and two PLLs.
 */
static struct clk osc32k = {
	.name		= "osc32k",
	.get_rate	= osc_get_rate,
	.users		= 1,
	.index		= 0,
};
static struct clk osc0 = {
	.name		= "osc0",
	.get_rate	= osc_get_rate,
	.users		= 1,
	.index		= 1,
};
static struct clk osc1 = {
	.name		= "osc1",
	.get_rate	= osc_get_rate,
	.index		= 2,
};
static struct clk pll0 = {
	.name		= "pll0",
	.get_rate	= pll0_get_rate,
	.parent		= &osc0,
};
static struct clk pll1 = {
	.name		= "pll1",
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	.mode		= pll1_mode,
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	.get_rate	= pll1_get_rate,
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	.set_rate	= pll1_set_rate,
	.set_parent	= pll1_set_parent,
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	.parent		= &osc0,
};

/*
 * The main clock can be either osc0 or pll0.  The boot loader may
 * have chosen one for us, so we don't really know which one until we
 * have a look at the SM.
 */
static struct clk *main_clock;

/*
 * Synchronous clocks are generated from the main clock. The clocks
 * must satisfy the constraint
 *   fCPU >= fHSB >= fPB
 * i.e. each clock must not be faster than its parent.
 */
static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
{
	return main_clock->get_rate(main_clock) >> shift;
};

static void cpu_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(CPU_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(CPU_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long cpu_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(CPUDIV))
		shift = PM_BFEXT(CPUSEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

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static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
{
	u32 control;
	unsigned long parent_rate, child_div, actual_rate, div;

	parent_rate = clk->parent->get_rate(clk->parent);
	control = pm_readl(CKSEL);

	if (control & PM_BIT(HSBDIV))
		child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
	else
		child_div = 1;

	if (rate > 3 * (parent_rate / 4) || child_div == 1) {
		actual_rate = parent_rate;
		control &= ~PM_BIT(CPUDIV);
	} else {
		unsigned int cpusel;
		div = (parent_rate + rate / 2) / rate;
		if (div > child_div)
			div = child_div;
		cpusel = (div > 1) ? (fls(div) - 2) : 0;
		control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
		actual_rate = parent_rate / (1 << (cpusel + 1));
	}

	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
			clk->name, rate, actual_rate);

	if (apply)
		pm_writel(CKSEL, control);

	return actual_rate;
}

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static void hsb_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(HSB_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(HSB_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long hsb_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(HSBDIV))
		shift = PM_BFEXT(HSBSEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

static void pba_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(PBA_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(PBA_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long pba_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(PBADIV))
		shift = PM_BFEXT(PBASEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

static void pbb_clk_mode(struct clk *clk, int enabled)
{
	unsigned long flags;
	u32 mask;

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	spin_lock_irqsave(&pm_lock, flags);
	mask = pm_readl(PBB_MASK);
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	if (enabled)
		mask |= 1 << clk->index;
	else
		mask &= ~(1 << clk->index);
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	pm_writel(PBB_MASK, mask);
	spin_unlock_irqrestore(&pm_lock, flags);
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}

static unsigned long pbb_clk_get_rate(struct clk *clk)
{
	unsigned long cksel, shift = 0;

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	cksel = pm_readl(CKSEL);
	if (cksel & PM_BIT(PBBDIV))
		shift = PM_BFEXT(PBBSEL, cksel) + 1;
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	return bus_clk_get_rate(clk, shift);
}

static struct clk cpu_clk = {
	.name		= "cpu",
	.get_rate	= cpu_clk_get_rate,
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	.set_rate	= cpu_clk_set_rate,
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	.users		= 1,
};
static struct clk hsb_clk = {
	.name		= "hsb",
	.parent		= &cpu_clk,
	.get_rate	= hsb_clk_get_rate,
};
static struct clk pba_clk = {
	.name		= "pba",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 1,
};
static struct clk pbb_clk = {
	.name		= "pbb",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.users		= 1,
	.index		= 2,
};

/* --------------------------------------------------------------------
 *  Generic Clock operations
 * -------------------------------------------------------------------- */

static void genclk_mode(struct clk *clk, int enabled)
{
	u32 control;

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	control = pm_readl(GCCTRL(clk->index));
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	if (enabled)
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		control |= PM_BIT(CEN);
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	else
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		control &= ~PM_BIT(CEN);
	pm_writel(GCCTRL(clk->index), control);
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}

static unsigned long genclk_get_rate(struct clk *clk)
{
	u32 control;
	unsigned long div = 1;

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	control = pm_readl(GCCTRL(clk->index));
	if (control & PM_BIT(DIVEN))
		div = 2 * (PM_BFEXT(DIV, control) + 1);
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	return clk->parent->get_rate(clk->parent) / div;
}

static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
{
	u32 control;
	unsigned long parent_rate, actual_rate, div;

	parent_rate = clk->parent->get_rate(clk->parent);
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	control = pm_readl(GCCTRL(clk->index));
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	if (rate > 3 * parent_rate / 4) {
		actual_rate = parent_rate;
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		control &= ~PM_BIT(DIVEN);
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	} else {
		div = (parent_rate + rate) / (2 * rate) - 1;
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		control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
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		actual_rate = parent_rate / (2 * (div + 1));
	}

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	dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
		clk->name, rate, actual_rate);
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	if (apply)
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		pm_writel(GCCTRL(clk->index), control);
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	return actual_rate;
}

int genclk_set_parent(struct clk *clk, struct clk *parent)
{
	u32 control;

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	dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
		clk->name, parent->name, clk->parent->name);
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	control = pm_readl(GCCTRL(clk->index));
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	if (parent == &osc1 || parent == &pll1)
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		control |= PM_BIT(OSCSEL);
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	else if (parent == &osc0 || parent == &pll0)
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		control &= ~PM_BIT(OSCSEL);
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	else
		return -EINVAL;

	if (parent == &pll0 || parent == &pll1)
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		control |= PM_BIT(PLLSEL);
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	else
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		control &= ~PM_BIT(PLLSEL);
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	pm_writel(GCCTRL(clk->index), control);
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	clk->parent = parent;

	return 0;
}

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static void __init genclk_init_parent(struct clk *clk)
{
	u32 control;
	struct clk *parent;

	BUG_ON(clk->index > 7);

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	control = pm_readl(GCCTRL(clk->index));
	if (control & PM_BIT(OSCSEL))
		parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
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	else
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		parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
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	clk->parent = parent;
}

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/* --------------------------------------------------------------------
 *  System peripherals
 * -------------------------------------------------------------------- */
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static struct resource at32_pm0_resource[] = {
	{
		.start	= 0xfff00000,
		.end	= 0xfff0007f,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(20),
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};
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static struct resource at32ap700x_rtc0_resource[] = {
	{
		.start	= 0xfff00080,
		.end	= 0xfff000af,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(21),
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};
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static struct resource at32_wdt0_resource[] = {
	{
		.start	= 0xfff000b0,
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		.end	= 0xfff000cf,
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		.flags	= IORESOURCE_MEM,
	},
};

static struct resource at32_eic0_resource[] = {
	{
		.start	= 0xfff00100,
		.end	= 0xfff0013f,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(19),
};

DEFINE_DEV(at32_pm, 0);
DEFINE_DEV(at32ap700x_rtc, 0);
DEFINE_DEV(at32_wdt, 0);
DEFINE_DEV(at32_eic, 0);

/*
 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 * is always running.
 */
static struct clk at32_pm_pclk = {
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	.name		= "pclk",
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	.dev		= &at32_pm0_device.dev,
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	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.users		= 1,
	.index		= 0,
};
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static struct resource intc0_resource[] = {
	PBMEM(0xfff00400),
};
struct platform_device at32_intc0_device = {
	.name		= "intc",
	.id		= 0,
	.resource	= intc0_resource,
	.num_resources	= ARRAY_SIZE(intc0_resource),
};
DEV_CLK(pclk, at32_intc0, pbb, 1);

static struct clk ebi_clk = {
	.name		= "ebi",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= hsb_clk_get_rate,
	.users		= 1,
};
static struct clk hramc_clk = {
	.name		= "hramc",
	.parent		= &hsb_clk,
	.mode		= hsb_clk_mode,
	.get_rate	= hsb_clk_get_rate,
	.users		= 1,
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	.index		= 3,
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};
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static struct clk sdramc_clk = {
	.name		= "sdramc_clk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.users		= 1,
	.index		= 14,
};
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static struct resource smc0_resource[] = {
	PBMEM(0xfff03400),
};
DEFINE_DEV(smc, 0);
DEV_CLK(pclk, smc0, pbb, 13);
DEV_CLK(mck, smc0, hsb, 0);

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static struct platform_device pdc_device = {
	.name		= "pdc",
	.id		= 0,
};
DEV_CLK(hclk, pdc, hsb, 4);
DEV_CLK(pclk, pdc, pba, 16);

static struct clk pico_clk = {
	.name		= "pico",
	.parent		= &cpu_clk,
	.mode		= cpu_clk_mode,
	.get_rate	= cpu_clk_get_rate,
	.users		= 1,
};

711 712 713 714 715 716 717 718 719 720 721
static struct resource dmaca0_resource[] = {
	{
		.start	= 0xff200000,
		.end	= 0xff20ffff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(2),
};
DEFINE_DEV(dmaca, 0);
DEV_CLK(hclk, dmaca0, hsb, 10);

722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757
/* --------------------------------------------------------------------
 * HMATRIX
 * -------------------------------------------------------------------- */

static struct clk hmatrix_clk = {
	.name		= "hmatrix_clk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 2,
	.users		= 1,
};
#define HMATRIX_BASE	((void __iomem *)0xfff00800)

#define hmatrix_readl(reg)					\
	__raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
#define hmatrix_writel(reg,value)				\
	__raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)

/*
 * Set bits in the HMATRIX Special Function Register (SFR) used by the
 * External Bus Interface (EBI). This can be used to enable special
 * features like CompactFlash support, NAND Flash support, etc. on
 * certain chipselects.
 */
static inline void set_ebi_sfr_bits(u32 mask)
{
	u32 sfr;

	clk_enable(&hmatrix_clk);
	sfr = hmatrix_readl(SFR4);
	sfr |= mask;
	hmatrix_writel(SFR4, sfr);
	clk_disable(&hmatrix_clk);
}

758
/* --------------------------------------------------------------------
759
 *  Timer/Counter (TC)
760
 * -------------------------------------------------------------------- */
761 762

static struct resource at32_tcb0_resource[] = {
763 764 765
	PBMEM(0xfff00c00),
	IRQ(22),
};
766 767
static struct platform_device at32_tcb0_device = {
	.name		= "atmel_tcb",
768
	.id		= 0,
769 770 771 772 773 774 775 776 777 778 779 780 781 782
	.resource	= at32_tcb0_resource,
	.num_resources	= ARRAY_SIZE(at32_tcb0_resource),
};
DEV_CLK(t0_clk, at32_tcb0, pbb, 3);

static struct resource at32_tcb1_resource[] = {
	PBMEM(0xfff01000),
	IRQ(23),
};
static struct platform_device at32_tcb1_device = {
	.name		= "atmel_tcb",
	.id		= 1,
	.resource	= at32_tcb1_resource,
	.num_resources	= ARRAY_SIZE(at32_tcb1_resource),
783
};
784
DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
785

786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817
/* --------------------------------------------------------------------
 *  PIO
 * -------------------------------------------------------------------- */

static struct resource pio0_resource[] = {
	PBMEM(0xffe02800),
	IRQ(13),
};
DEFINE_DEV(pio, 0);
DEV_CLK(mck, pio0, pba, 10);

static struct resource pio1_resource[] = {
	PBMEM(0xffe02c00),
	IRQ(14),
};
DEFINE_DEV(pio, 1);
DEV_CLK(mck, pio1, pba, 11);

static struct resource pio2_resource[] = {
	PBMEM(0xffe03000),
	IRQ(15),
};
DEFINE_DEV(pio, 2);
DEV_CLK(mck, pio2, pba, 12);

static struct resource pio3_resource[] = {
	PBMEM(0xffe03400),
	IRQ(16),
};
DEFINE_DEV(pio, 3);
DEV_CLK(mck, pio3, pba, 13);

818 819 820 821 822 823 824
static struct resource pio4_resource[] = {
	PBMEM(0xffe03800),
	IRQ(17),
};
DEFINE_DEV(pio, 4);
DEV_CLK(mck, pio4, pba, 14);

825 826
void __init at32_add_system_devices(void)
{
827
	platform_device_register(&at32_pm0_device);
828
	platform_device_register(&at32_intc0_device);
829 830 831
	platform_device_register(&at32ap700x_rtc0_device);
	platform_device_register(&at32_wdt0_device);
	platform_device_register(&at32_eic0_device);
832
	platform_device_register(&smc0_device);
833
	platform_device_register(&pdc_device);
834
	platform_device_register(&dmaca0_device);
835

836 837
	platform_device_register(&at32_tcb0_device);
	platform_device_register(&at32_tcb1_device);
838

839 840 841 842
	platform_device_register(&pio0_device);
	platform_device_register(&pio1_device);
	platform_device_register(&pio2_device);
	platform_device_register(&pio3_device);
843
	platform_device_register(&pio4_device);
844 845
}

846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920
/* --------------------------------------------------------------------
 *  PSIF
 * -------------------------------------------------------------------- */
static struct resource atmel_psif0_resource[] __initdata = {
	{
		.start	= 0xffe03c00,
		.end	= 0xffe03cff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(18),
};
static struct clk atmel_psif0_pclk = {
	.name		= "pclk",
	.parent		= &pba_clk,
	.mode		= pba_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 15,
};

static struct resource atmel_psif1_resource[] __initdata = {
	{
		.start	= 0xffe03d00,
		.end	= 0xffe03dff,
		.flags	= IORESOURCE_MEM,
	},
	IRQ(18),
};
static struct clk atmel_psif1_pclk = {
	.name		= "pclk",
	.parent		= &pba_clk,
	.mode		= pba_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 15,
};

struct platform_device *__init at32_add_device_psif(unsigned int id)
{
	struct platform_device *pdev;

	if (!(id == 0 || id == 1))
		return NULL;

	pdev = platform_device_alloc("atmel_psif", id);
	if (!pdev)
		return NULL;

	switch (id) {
	case 0:
		if (platform_device_add_resources(pdev, atmel_psif0_resource,
					ARRAY_SIZE(atmel_psif0_resource)))
			goto err_add_resources;
		atmel_psif0_pclk.dev = &pdev->dev;
		select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
		select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
		break;
	case 1:
		if (platform_device_add_resources(pdev, atmel_psif1_resource,
					ARRAY_SIZE(atmel_psif1_resource)))
			goto err_add_resources;
		atmel_psif1_pclk.dev = &pdev->dev;
		select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
		select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
		break;
	default:
		return NULL;
	}

	platform_device_add(pdev);
	return pdev;

err_add_resources:
	platform_device_put(pdev);
	return NULL;
}

921 922 923 924
/* --------------------------------------------------------------------
 *  USART
 * -------------------------------------------------------------------- */

925 926 927 928
static struct atmel_uart_data atmel_usart0_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
929
static struct resource atmel_usart0_resource[] = {
930
	PBMEM(0xffe00c00),
931
	IRQ(6),
932
};
933
DEFINE_DEV_DATA(atmel_usart, 0);
934
DEV_CLK(usart, atmel_usart0, pba, 3);
935

936 937 938 939
static struct atmel_uart_data atmel_usart1_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
940
static struct resource atmel_usart1_resource[] = {
941 942 943
	PBMEM(0xffe01000),
	IRQ(7),
};
944
DEFINE_DEV_DATA(atmel_usart, 1);
945
DEV_CLK(usart, atmel_usart1, pba, 4);
946

947 948 949 950
static struct atmel_uart_data atmel_usart2_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
951
static struct resource atmel_usart2_resource[] = {
952 953 954
	PBMEM(0xffe01400),
	IRQ(8),
};
955
DEFINE_DEV_DATA(atmel_usart, 2);
956
DEV_CLK(usart, atmel_usart2, pba, 5);
957

958 959 960 961
static struct atmel_uart_data atmel_usart3_data = {
	.use_dma_tx	= 1,
	.use_dma_rx	= 1,
};
962
static struct resource atmel_usart3_resource[] = {
963 964 965
	PBMEM(0xffe01800),
	IRQ(9),
};
966
DEFINE_DEV_DATA(atmel_usart, 3);
967
DEV_CLK(usart, atmel_usart3, pba, 6);
968 969 970

static inline void configure_usart0_pins(void)
{
971 972
	select_peripheral(PA(8),  PERIPH_B, 0);	/* RXD	*/
	select_peripheral(PA(9),  PERIPH_B, 0);	/* TXD	*/
973 974 975 976
}

static inline void configure_usart1_pins(void)
{
977 978
	select_peripheral(PA(17), PERIPH_A, 0);	/* RXD	*/
	select_peripheral(PA(18), PERIPH_A, 0);	/* TXD	*/
979 980 981 982
}

static inline void configure_usart2_pins(void)
{
983 984
	select_peripheral(PB(26), PERIPH_B, 0);	/* RXD	*/
	select_peripheral(PB(27), PERIPH_B, 0);	/* TXD	*/
985 986 987 988
}

static inline void configure_usart3_pins(void)
{
989 990
	select_peripheral(PB(18), PERIPH_B, 0);	/* RXD	*/
	select_peripheral(PB(17), PERIPH_B, 0);	/* TXD	*/
991 992
}

993
static struct platform_device *__initdata at32_usarts[4];
994 995

void __init at32_map_usart(unsigned int hw_id, unsigned int line)
996 997 998
{
	struct platform_device *pdev;

999
	switch (hw_id) {
1000
	case 0:
1001
		pdev = &atmel_usart0_device;
1002 1003 1004
		configure_usart0_pins();
		break;
	case 1:
1005
		pdev = &atmel_usart1_device;
1006 1007 1008
		configure_usart1_pins();
		break;
	case 2:
1009
		pdev = &atmel_usart2_device;
1010 1011 1012
		configure_usart2_pins();
		break;
	case 3:
1013
		pdev = &atmel_usart3_device;
1014 1015 1016
		configure_usart3_pins();
		break;
	default:
1017
		return;
1018 1019 1020 1021 1022 1023
	}

	if (PXSEG(pdev->resource[0].start) == P4SEG) {
		/* Addresses in the P4 segment are permanently mapped 1:1 */
		struct atmel_uart_data *data = pdev->dev.platform_data;
		data->regs = (void __iomem *)pdev->resource[0].start;
1024 1025
	}

1026 1027
	pdev->id = line;
	at32_usarts[line] = pdev;
1028 1029 1030 1031
}

struct platform_device *__init at32_add_device_usart(unsigned int id)
{
1032 1033
	platform_device_register(at32_usarts[id]);
	return at32_usarts[id];
1034 1035
}

1036
struct platform_device *atmel_default_console_device;
1037 1038 1039

void __init at32_setup_serial_console(unsigned int usart_id)
{
1040
	atmel_default_console_device = at32_usarts[usart_id];
1041 1042 1043 1044 1045 1046
}

/* --------------------------------------------------------------------
 *  Ethernet
 * -------------------------------------------------------------------- */

1047
#ifdef CONFIG_CPU_AT32AP7000
1048 1049 1050 1051 1052 1053 1054 1055 1056
static struct eth_platform_data macb0_data;
static struct resource macb0_resource[] = {
	PBMEM(0xfff01800),
	IRQ(25),
};
DEFINE_DEV_DATA(macb, 0);
DEV_CLK(hclk, macb0, hsb, 8);
DEV_CLK(pclk, macb0, pbb, 6);

1057 1058 1059 1060 1061 1062 1063 1064 1065
static struct eth_platform_data macb1_data;
static struct resource macb1_resource[] = {
	PBMEM(0xfff01c00),
	IRQ(26),
};
DEFINE_DEV_DATA(macb, 1);
DEV_CLK(hclk, macb1, hsb, 9);
DEV_CLK(pclk, macb1, pbb, 7);

1066 1067 1068 1069 1070 1071 1072 1073 1074
struct platform_device *__init
at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
{
	struct platform_device *pdev;

	switch (id) {
	case 0:
		pdev = &macb0_device;

1075 1076 1077 1078 1079 1080 1081 1082 1083 1084
		select_peripheral(PC(3),  PERIPH_A, 0);	/* TXD0	*/
		select_peripheral(PC(4),  PERIPH_A, 0);	/* TXD1	*/
		select_peripheral(PC(7),  PERIPH_A, 0);	/* TXEN	*/
		select_peripheral(PC(8),  PERIPH_A, 0);	/* TXCK */
		select_peripheral(PC(9),  PERIPH_A, 0);	/* RXD0	*/
		select_peripheral(PC(10), PERIPH_A, 0);	/* RXD1	*/
		select_peripheral(PC(13), PERIPH_A, 0);	/* RXER	*/
		select_peripheral(PC(15), PERIPH_A, 0);	/* RXDV	*/
		select_peripheral(PC(16), PERIPH_A, 0);	/* MDC	*/
		select_peripheral(PC(17), PERIPH_A, 0);	/* MDIO	*/
1085 1086

		if (!data->is_rmii) {
1087 1088 1089 1090 1091 1092 1093 1094 1095
			select_peripheral(PC(0),  PERIPH_A, 0);	/* COL	*/
			select_peripheral(PC(1),  PERIPH_A, 0);	/* CRS	*/
			select_peripheral(PC(2),  PERIPH_A, 0);	/* TXER	*/
			select_peripheral(PC(5),  PERIPH_A, 0);	/* TXD2	*/
			select_peripheral(PC(6),  PERIPH_A, 0);	/* TXD3 */
			select_peripheral(PC(11), PERIPH_A, 0);	/* RXD2	*/
			select_peripheral(PC(12), PERIPH_A, 0);	/* RXD3	*/
			select_peripheral(PC(14), PERIPH_A, 0);	/* RXCK	*/
			select_peripheral(PC(18), PERIPH_A, 0);	/* SPD	*/
1096 1097 1098
		}
		break;

1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125
	case 1:
		pdev = &macb1_device;

		select_peripheral(PD(13), PERIPH_B, 0);		/* TXD0	*/
		select_peripheral(PD(14), PERIPH_B, 0);		/* TXD1	*/
		select_peripheral(PD(11), PERIPH_B, 0);		/* TXEN	*/
		select_peripheral(PD(12), PERIPH_B, 0);		/* TXCK */
		select_peripheral(PD(10), PERIPH_B, 0);		/* RXD0	*/
		select_peripheral(PD(6),  PERIPH_B, 0);		/* RXD1	*/
		select_peripheral(PD(5),  PERIPH_B, 0);		/* RXER	*/
		select_peripheral(PD(4),  PERIPH_B, 0);		/* RXDV	*/
		select_peripheral(PD(3),  PERIPH_B, 0);		/* MDC	*/
		select_peripheral(PD(2),  PERIPH_B, 0);		/* MDIO	*/

		if (!data->is_rmii) {
			select_peripheral(PC(19), PERIPH_B, 0);	/* COL	*/
			select_peripheral(PC(23), PERIPH_B, 0);	/* CRS	*/
			select_peripheral(PC(26), PERIPH_B, 0);	/* TXER	*/
			select_peripheral(PC(27), PERIPH_B, 0);	/* TXD2	*/
			select_peripheral(PC(28), PERIPH_B, 0);	/* TXD3 */
			select_peripheral(PC(29), PERIPH_B, 0);	/* RXD2	*/
			select_peripheral(PC(30), PERIPH_B, 0);	/* RXD3	*/
			select_peripheral(PC(24), PERIPH_B, 0);	/* RXCK	*/
			select_peripheral(PD(15), PERIPH_B, 0);	/* SPD	*/
		}
		break;

1126 1127 1128 1129 1130 1131 1132 1133 1134
	default:
		return NULL;
	}

	memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
	platform_device_register(pdev);

	return pdev;
}
1135
#endif
1136 1137 1138 1139

/* --------------------------------------------------------------------
 *  SPI
 * -------------------------------------------------------------------- */
1140
static struct resource atmel_spi0_resource[] = {
1141 1142 1143
	PBMEM(0xffe00000),
	IRQ(3),
};
1144 1145 1146 1147 1148 1149 1150 1151 1152
DEFINE_DEV(atmel_spi, 0);
DEV_CLK(spi_clk, atmel_spi0, pba, 0);

static struct resource atmel_spi1_resource[] = {
	PBMEM(0xffe00400),
	IRQ(4),
};
DEFINE_DEV(atmel_spi, 1);
DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1153

1154
static void __init
1155 1156
at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
		      unsigned int n, const u8 *pins)
1157
{
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188
	unsigned int pin, mode;

	for (; n; n--, b++) {
		b->bus_num = bus_num;
		if (b->chip_select >= 4)
			continue;
		pin = (unsigned)b->controller_data;
		if (!pin) {
			pin = pins[b->chip_select];
			b->controller_data = (void *)pin;
		}
		mode = AT32_GPIOF_OUTPUT;
		if (!(b->mode & SPI_CS_HIGH))
			mode |= AT32_GPIOF_HIGH;
		at32_select_gpio(pin, mode);
	}
}

struct platform_device *__init
at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
{
	/*
	 * Manage the chipselects as GPIOs, normally using the same pins
	 * the SPI controller expects; but boards can use other pins.
	 */
	static u8 __initdata spi0_pins[] =
		{ GPIO_PIN_PA(3), GPIO_PIN_PA(4),
		  GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
	static u8 __initdata spi1_pins[] =
		{ GPIO_PIN_PB(2), GPIO_PIN_PB(3),
		  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1189 1190 1191 1192
	struct platform_device *pdev;

	switch (id) {
	case 0:
1193
		pdev = &atmel_spi0_device;
1194 1195
		/* pullup MISO so a level is always defined */
		select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
1196 1197
		select_peripheral(PA(1),  PERIPH_A, 0);	/* MOSI	 */
		select_peripheral(PA(2),  PERIPH_A, 0);	/* SCK	 */
1198
		at32_spi_setup_slaves(0, b, n, spi0_pins);
1199 1200 1201 1202
		break;

	case 1:
		pdev = &atmel_spi1_device;
1203 1204
		/* pullup MISO so a level is always defined */
		select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
1205 1206
		select_peripheral(PB(1),  PERIPH_B, 0);	/* MOSI  */
		select_peripheral(PB(5),  PERIPH_B, 0);	/* SCK   */
1207
		at32_spi_setup_slaves(1, b, n, spi1_pins);
1208 1209 1210 1211 1212 1213
		break;

	default:
		return NULL;
	}

1214
	spi_register_board_info(b, n);
1215 1216 1217 1218
	platform_device_register(pdev);
	return pdev;
}

1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
/* --------------------------------------------------------------------
 *  TWI
 * -------------------------------------------------------------------- */
static struct resource atmel_twi0_resource[] __initdata = {
	PBMEM(0xffe00800),
	IRQ(5),
};
static struct clk atmel_twi0_pclk = {
	.name		= "twi_pclk",
	.parent		= &pba_clk,
	.mode		= pba_clk_mode,
	.get_rate	= pba_clk_get_rate,
	.index		= 2,
};

1234 1235 1236
struct platform_device *__init at32_add_device_twi(unsigned int id,
						    struct i2c_board_info *b,
						    unsigned int n)
1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
{
	struct platform_device *pdev;

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("atmel_twi", id);
	if (!pdev)
		return NULL;

	if (platform_device_add_resources(pdev, atmel_twi0_resource,
				ARRAY_SIZE(atmel_twi0_resource)))
		goto err_add_resources;

	select_peripheral(PA(6),  PERIPH_A, 0);	/* SDA	*/
	select_peripheral(PA(7),  PERIPH_A, 0);	/* SDL	*/

	atmel_twi0_pclk.dev = &pdev->dev;

1256 1257 1258
	if (b)
		i2c_register_board_info(id, b, n);

1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
	platform_device_add(pdev);
	return pdev;

err_add_resources:
	platform_device_put(pdev);
	return NULL;
}

/* --------------------------------------------------------------------
 * MMC
 * -------------------------------------------------------------------- */
static struct resource atmel_mci0_resource[] __initdata = {
	PBMEM(0xfff02400),
	IRQ(28),
};
static struct clk atmel_mci0_pclk = {
	.name		= "mci_clk",
	.parent		= &pbb_clk,
	.mode		= pbb_clk_mode,
	.get_rate	= pbb_clk_get_rate,
	.index		= 9,
};

1282 1283
struct platform_device *__init
at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1284
{
1285 1286 1287
	struct mci_platform_data	_data;
	struct platform_device		*pdev;
	struct dw_dma_slave		*dws;
1288 1289 1290 1291 1292 1293

	if (id != 0)
		return NULL;

	pdev = platform_device_alloc("atmel_mci", id);
	if (!pdev)
1294
		goto fail;
1295 1296 1297

	if (platform_device_add_resources(pdev, atmel_mci0_resource,
				ARRAY_SIZE(atmel_mci0_resource)))
1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
		goto fail;

	if (!data) {
		data = &_data;
		memset(data, 0, sizeof(struct mci_platform_data));
	}

	if (platform_device_add_data(pdev, data,
				sizeof(struct mci_platform_data)))
		goto fail;
1308 1309 1310 1311 1312 1313 1314 1315

	select_peripheral(PA(10), PERIPH_A, 0);	/* CLK	 */
	select_peripheral(PA(11), PERIPH_A, 0);	/* CMD	 */
	select_peripheral(PA(12), PERIPH_A, 0);	/* DATA0 */
	select_peripheral(PA(13), PERIPH_A, 0);	/* DATA1 */
	select_peripheral(PA(14), PERIPH_A, 0);	/* DATA2 */
	select_peripheral(PA(15), PERIPH_A, 0);	/* DATA3 */

1316 1317 1318 1319 1320 1321 1322
	if (data) {
		if (data->detect_pin != GPIO_PIN_NONE)
			at32_select_gpio(data->detect_pin, 0);
		if (data->wp_pin != GPIO_PIN_NONE)
			at32_select_gpio(data->wp_pin, 0);
	}

1323 1324 1325 1326 1327
	atmel_mci0_pclk.dev = &pdev->dev;

	platform_device_add(pdev);
	return pdev;

1328
fail:
1329 1330 1331 1332
	platform_device_put(pdev);
	return NULL;
}

1333 1334 1335
/* --------------------------------------------------------------------
 *  LCDC
 * -------------------------------------------------------------------- */
1336
#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1337 1338
static struct atmel_lcdfb_info atmel_lcdfb0_data;
static struct resource atmel_lcdfb0_resource[] = {
1339 1340 1341 1342 1343 1344
	{
		.start		= 0xff000000,
		.end		= 0xff000fff,
		.flags		= IORESOURCE_MEM,
	},
	IRQ(1),
1345 1346 1347 1348 1349 1350
	{
		/* Placeholder for pre-allocated fb memory */
		.start		= 0x00000000,
		.end		= 0x00000000,
		.flags		= 0,
	},
1351
};
1352 1353 1354 1355 1356
DEFINE_DEV_DATA(atmel_lcdfb, 0);
DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
static struct clk atmel_lcdfb0_pixclk = {
	.name		= "lcdc_clk",
	.dev		= &atmel_lcdfb0_device.dev,
1357 1358 1359 1360 1361 1362 1363 1364
	.mode		= genclk_mode,
	.get_rate	= genclk_get_rate,
	.set_rate	= genclk_set_rate,
	.set_parent	= genclk_set_parent,
	.index		= 7,
};

struct platform_device *__init
1365
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1366 1367
		     unsigned long fbmem_start, unsigned long fbmem_len,
		     unsigned int pin_config)
1368 1369
{
	struct platform_device *pdev;
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389
	struct atmel_lcdfb_info *info;
	struct fb_monspecs *monspecs;
	struct fb_videomode *modedb;
	unsigned int modedb_size;

	/*
	 * Do a deep copy of the fb data, monspecs and modedb. Make
	 * sure all allocations are done before setting up the
	 * portmux.
	 */
	monspecs = kmemdup(data->default_monspecs,
			   sizeof(struct fb_monspecs), GFP_KERNEL);
	if (!monspecs)