hpt366.c 44.8 KB
Newer Older
Linus Torvalds's avatar
Linus Torvalds committed
1
/*
2
 * linux/drivers/ide/pci/hpt366.c		Version 1.01	Dec 23, 2006
Linus Torvalds's avatar
Linus Torvalds committed
3 4 5 6
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
7
 * Portions Copyright (C) 2005-2006	MontaVista Software, Inc.
Linus Torvalds's avatar
Linus Torvalds committed
8 9 10 11 12 13
 *
 * Thanks to HighPoint Technologies for their assistance, and hardware.
 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
 * donation of an ABit BP6 mainboard, processor, and memory acellerated
 * development and support.
 *
14
 *
15 16 17 18 19
 * HighPoint has its own drivers (open source except for the RAID part)
 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
 * This may be useful to anyone wanting to work on this driver, however  do not
 * trust  them too much since the code tends to become less and less meaningful
 * as the time passes... :-/
20
 *
Linus Torvalds's avatar
Linus Torvalds committed
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
 * Note that final HPT370 support was done by force extraction of GPL.
 *
 * - add function for getting/setting power status of drive
 * - the HPT370's state machine can get confused. reset it before each dma 
 *   xfer to prevent that from happening.
 * - reset state engine whenever we get an error.
 * - check for busmaster state at end of dma. 
 * - use new highpoint timings.
 * - detect bus speed using highpoint register.
 * - use pll if we don't have a clock table. added a 66MHz table that's
 *   just 2x the 33MHz table.
 * - removed turnaround. NOTE: we never want to switch between pll and
 *   pci clocks as the chip can glitch in those cases. the highpoint
 *   approved workaround slows everything down too much to be useful. in
 *   addition, we would have to serialize access to each chip.
 * 	Adrian Sun <a.sun@sun.com>
 *
 * add drive timings for 66MHz PCI bus,
 * fix ATA Cable signal detection, fix incorrect /proc info
 * add /proc display for per-drive PIO/DMA/UDMA mode and
 * per-channel ATA-33/66 Cable detect.
 * 	Duncan Laurie <void@sun.com>
 *
 * fixup /proc output for multiple controllers
 *	Tim Hockin <thockin@sun.com>
 *
 * On hpt366: 
 * Reset the hpt366 on error, reset on dma
 * Fix disabling Fast Interrupt hpt366.
 * 	Mike Waychison <crlf@sun.com>
 *
 * Added support for 372N clocking and clock switching. The 372N needs
 * different clocks on read/write. This requires overloading rw_disk and
 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
 * keeping me sane. 
 *		Alan Cox <alan@redhat.com>
 *
58 59 60 61 62
 * - fix the clock turnaround code: it was writing to the wrong ports when
 *   called for the secondary channel, caching the current clock mode per-
 *   channel caused the cached register value to get out of sync with the
 *   actual one, the channels weren't serialized, the turnaround shouldn't
 *   be done on 66 MHz PCI bus
Sergei Shtylyov's avatar
Sergei Shtylyov committed
63 64 65 66
 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
 *   does not allow for this speed anyway
 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
 *   their primary channel is kind of virtual, it isn't tied to any pins)
67 68 69
 * - fix/remove bad/unused timing tables and use one set of tables for the whole
 *   HPT37x chip family; save space by introducing the separate transfer mode
 *   table in which the mode lookup is done
70 71
 * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
 *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
72 73
 * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
 *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 75
 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
 *   they tamper with its fields
Sergei Shtylyov's avatar
Sergei Shtylyov committed
76 77
 * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
 *   since they may tamper with its fields
78 79
 * - prefix the driver startup messages with the real chip name
 * - claim the extra 240 bytes of I/O space for all chips
80
 * - optimize the rate masking/filtering and the drive list lookup code
81
 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov's avatar
Sergei Shtylyov committed
82 83 84 85
 * - cache offset of the channel's misc. control registers (MCRs) being used
 *   throughout the driver
 * - only touch the relevant MCR when detecting the cable type on HPT374's
 *   function 1
86
 * - rename all the register related variables consistently
Sergei Shtylyov's avatar
Sergei Shtylyov committed
87 88 89 90 91 92 93
 * - move all the interrupt twiddling code from the speedproc handlers into
 *   init_hwif_hpt366(), also grouping all the DMA related code together there
 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
 *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
 *   when setting an UltraDMA mode
 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
 *   the best possible one
94
 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov's avatar
Sergei Shtylyov committed
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
 * - switch to using the enumeration type to differ between the numerous chip
 *   variants, matching PCI device/revision ID with the chip type early, at the
 *   init_setup stage
 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
 *   stop duplicating it for each channel by storing the pointer in the pci_dev
 *   structure: first, at the init_setup stage, point it to a static "template"
 *   with only the chip type and its specific base DPLL frequency, the highest
 *   supported DMA mode, and the chip settings table pointer filled, then, at
 *   the init_chipset stage, allocate per-chip instance  and fill it with the
 *   rest of the necessary information
 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 *   frequency
 * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
 *   anything  newer than HPT370/A
110 111
 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
112 113 114
 *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 *   the register setting lists into the table indexed by the clock selected
 *	Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds's avatar
Linus Torvalds committed
115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137
 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>

#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>

/* various tuning parameters */
#define HPT_RESET_STATE_ENGINE
138 139
#undef	HPT_DELAY_INTERRUPT
#define HPT_SERIALIZE_IO	0
Linus Torvalds's avatar
Linus Torvalds committed
140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202

static const char *quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static const char *bad_ata100_5[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220
static u8 xfer_speeds[] = {
	XFER_UDMA_6,
	XFER_UDMA_5,
	XFER_UDMA_4,
	XFER_UDMA_3,
	XFER_UDMA_2,
	XFER_UDMA_1,
	XFER_UDMA_0,

	XFER_MW_DMA_2,
	XFER_MW_DMA_1,
	XFER_MW_DMA_0,

	XFER_PIO_4,
	XFER_PIO_3,
	XFER_PIO_2,
	XFER_PIO_1,
	XFER_PIO_0
Linus Torvalds's avatar
Linus Torvalds committed
221 222
};

223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244
/* Key for bus clock timings
 * 36x   37x
 * bits  bits
 * 0:3	 0:3	data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *		cycles = value + 1
 * 4:7	 4:8	data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *		cycles = value + 1
 * 8:11  9:12	cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *		register access.
 * 12:15 13:17	cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *		register access.
 * 16:18 18:20	udma_cycle_time. Clock cycles for UDMA xfer.
 * -	 21	CLK frequency: 0=ATA clock, 1=dual ATA clock.
 * 19:21 22:24	pre_high_time. Time to initialize the 1st cycle for PIO and
 *		MW DMA xfer.
 * 22:24 25:27	cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 *		task file register access.
 * 28	 28	UDMA enable.
 * 29	 29	DMA  enable.
 * 30	 30	PIO MST enable. If set, the chip is in bus master mode during
 *		PIO xfer.
 * 31	 31	FIFO enable.
Linus Torvalds's avatar
Linus Torvalds committed
245 246
 */

247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264
static u32 forty_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x900fd943,
	/* XFER_UDMA_5 */	0x900fd943,
	/* XFER_UDMA_4 */	0x900fd943,
	/* XFER_UDMA_3 */	0x900ad943,
	/* XFER_UDMA_2 */	0x900bd943,
	/* XFER_UDMA_1 */	0x9008d943,
	/* XFER_UDMA_0 */	0x9008d943,

	/* XFER_MW_DMA_2 */	0xa008d943,
	/* XFER_MW_DMA_1 */	0xa010d955,
	/* XFER_MW_DMA_0 */	0xa010d9fc,

	/* XFER_PIO_4 */	0xc008d963,
	/* XFER_PIO_3 */	0xc010d974,
	/* XFER_PIO_2 */	0xc010d997,
	/* XFER_PIO_1 */	0xc010d9c7,
	/* XFER_PIO_0 */	0xc018d9d9
Linus Torvalds's avatar
Linus Torvalds committed
265 266
};

267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284
static u32 thirty_three_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x90c9a731,
	/* XFER_UDMA_5 */	0x90c9a731,
	/* XFER_UDMA_4 */	0x90c9a731,
	/* XFER_UDMA_3 */	0x90cfa731,
	/* XFER_UDMA_2 */	0x90caa731,
	/* XFER_UDMA_1 */	0x90cba731,
	/* XFER_UDMA_0 */	0x90c8a731,

	/* XFER_MW_DMA_2 */	0xa0c8a731,
	/* XFER_MW_DMA_1 */	0xa0c8a732,	/* 0xa0c8a733 */
	/* XFER_MW_DMA_0 */	0xa0c8a797,

	/* XFER_PIO_4 */	0xc0c8a731,
	/* XFER_PIO_3 */	0xc0c8a742,
	/* XFER_PIO_2 */	0xc0d0a753,
	/* XFER_PIO_1 */	0xc0d0a7a3,	/* 0xc0d0a793 */
	/* XFER_PIO_0 */	0xc0d0a7aa	/* 0xc0d0a7a7 */
Linus Torvalds's avatar
Linus Torvalds committed
285 286
};

287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304
static u32 twenty_five_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x90c98521,
	/* XFER_UDMA_5 */	0x90c98521,
	/* XFER_UDMA_4 */	0x90c98521,
	/* XFER_UDMA_3 */	0x90cf8521,
	/* XFER_UDMA_2 */	0x90cf8521,
	/* XFER_UDMA_1 */	0x90cb8521,
	/* XFER_UDMA_0 */	0x90cb8521,

	/* XFER_MW_DMA_2 */	0xa0ca8521,
	/* XFER_MW_DMA_1 */	0xa0ca8532,
	/* XFER_MW_DMA_0 */	0xa0ca8575,

	/* XFER_PIO_4 */	0xc0ca8521,
	/* XFER_PIO_3 */	0xc0ca8532,
	/* XFER_PIO_2 */	0xc0ca8542,
	/* XFER_PIO_1 */	0xc0d08572,
	/* XFER_PIO_0 */	0xc0d08585
Linus Torvalds's avatar
Linus Torvalds committed
305 306
};

307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324
static u32 thirty_three_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x12446231,	/* 0x12646231 ?? */
	/* XFER_UDMA_5 */	0x12446231,
	/* XFER_UDMA_4 */	0x12446231,
	/* XFER_UDMA_3 */	0x126c6231,
	/* XFER_UDMA_2 */	0x12486231,
	/* XFER_UDMA_1 */	0x124c6233,
	/* XFER_UDMA_0 */	0x12506297,

	/* XFER_MW_DMA_2 */	0x22406c31,
	/* XFER_MW_DMA_1 */	0x22406c33,
	/* XFER_MW_DMA_0 */	0x22406c97,

	/* XFER_PIO_4 */	0x06414e31,
	/* XFER_PIO_3 */	0x06414e42,
	/* XFER_PIO_2 */	0x06414e53,
	/* XFER_PIO_1 */	0x06814e93,
	/* XFER_PIO_0 */	0x06814ea7
Linus Torvalds's avatar
Linus Torvalds committed
325 326
};

327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344
static u32 fifty_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x12848242,
	/* XFER_UDMA_5 */	0x12848242,
	/* XFER_UDMA_4 */	0x12ac8242,
	/* XFER_UDMA_3 */	0x128c8242,
	/* XFER_UDMA_2 */	0x120c8242,
	/* XFER_UDMA_1 */	0x12148254,
	/* XFER_UDMA_0 */	0x121882ea,

	/* XFER_MW_DMA_2 */	0x22808242,
	/* XFER_MW_DMA_1 */	0x22808254,
	/* XFER_MW_DMA_0 */	0x228082ea,

	/* XFER_PIO_4 */	0x0a81f442,
	/* XFER_PIO_3 */	0x0a81f443,
	/* XFER_PIO_2 */	0x0a81f454,
	/* XFER_PIO_1 */	0x0ac1f465,
	/* XFER_PIO_0 */	0x0ac1f48a
Linus Torvalds's avatar
Linus Torvalds committed
345 346
};

347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364
static u32 sixty_six_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x1c869c62,
	/* XFER_UDMA_5 */	0x1cae9c62,	/* 0x1c8a9c62 */
	/* XFER_UDMA_4 */	0x1c8a9c62,
	/* XFER_UDMA_3 */	0x1c8e9c62,
	/* XFER_UDMA_2 */	0x1c929c62,
	/* XFER_UDMA_1 */	0x1c9a9c62,
	/* XFER_UDMA_0 */	0x1c829c62,

	/* XFER_MW_DMA_2 */	0x2c829c62,
	/* XFER_MW_DMA_1 */	0x2c829c66,
	/* XFER_MW_DMA_0 */	0x2c829d2e,

	/* XFER_PIO_4 */	0x0c829c62,
	/* XFER_PIO_3 */	0x0c829c84,
	/* XFER_PIO_2 */	0x0c829ca6,
	/* XFER_PIO_1 */	0x0d029d26,
	/* XFER_PIO_0 */	0x0d029d5e
Linus Torvalds's avatar
Linus Torvalds committed
365 366 367
};

#define HPT366_DEBUG_DRIVE_INFO		0
Sergei Shtylyov's avatar
Sergei Shtylyov committed
368 369 370 371
#define HPT374_ALLOW_ATA133_6		1
#define HPT371_ALLOW_ATA133_6		1
#define HPT302_ALLOW_ATA133_6		1
#define HPT372_ALLOW_ATA133_6		1
372
#define HPT370_ALLOW_ATA100_5		0
Linus Torvalds's avatar
Linus Torvalds committed
373 374 375 376
#define HPT366_ALLOW_ATA66_4		1
#define HPT366_ALLOW_ATA66_3		1
#define HPT366_MAX_DEVS			8

Sergei Shtylyov's avatar
Sergei Shtylyov committed
377 378 379 380 381 382 383 384 385
/* Supported ATA clock frequencies */
enum ata_clock {
	ATA_CLOCK_25MHZ,
	ATA_CLOCK_33MHZ,
	ATA_CLOCK_40MHZ,
	ATA_CLOCK_50MHZ,
	ATA_CLOCK_66MHZ,
	NUM_ATA_CLOCKS
};
Linus Torvalds's avatar
Linus Torvalds committed
386

387
/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
388
 *	Hold all the HighPoint chip information in one place.
389
 */
Linus Torvalds's avatar
Linus Torvalds committed
390

Sergei Shtylyov's avatar
Sergei Shtylyov committed
391 392
struct hpt_info {
	u8 chip_type;		/* Chip type */
393
	u8 max_mode;		/* Speeds allowed */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
394 395 396
	u8 dpll_clk;		/* DPLL clock in MHz */
	u8 pci_clk;		/* PCI  clock in MHz */
	u32 **settings; 	/* Chipset settings table */
397 398
};

Sergei Shtylyov's avatar
Sergei Shtylyov committed
399 400 401 402 403 404 405 406 407 408 409 410 411 412
/* Supported HighPoint chips */
enum {
	HPT36x,
	HPT370,
	HPT370A,
	HPT374,
	HPT372,
	HPT372A,
	HPT302,
	HPT371,
	HPT372N,
	HPT302N,
	HPT371N
};
413

Sergei Shtylyov's avatar
Sergei Shtylyov committed
414 415 416 417 418 419 420
static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
	twenty_five_base_hpt36x,
	thirty_three_base_hpt36x,
	forty_base_hpt36x,
	NULL,
	NULL
};
421

Sergei Shtylyov's avatar
Sergei Shtylyov committed
422 423 424 425 426 427 428
static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
	NULL,
	thirty_three_base_hpt37x,
	NULL,
	fifty_base_hpt37x,
	sixty_six_base_hpt37x
};
Linus Torvalds's avatar
Linus Torvalds committed
429

Sergei Shtylyov's avatar
Sergei Shtylyov committed
430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504
static struct hpt_info hpt36x __devinitdata = {
	.chip_type	= HPT36x,
	.max_mode	= (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
	.dpll_clk	= 0,	/* no DPLL */
	.settings	= hpt36x_settings
};

static struct hpt_info hpt370 __devinitdata = {
	.chip_type	= HPT370,
	.max_mode	= HPT370_ALLOW_ATA100_5 ? 3 : 2,
	.dpll_clk	= 48,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt370a __devinitdata = {
	.chip_type	= HPT370A,
	.max_mode	= HPT370_ALLOW_ATA100_5 ? 3 : 2,
	.dpll_clk	= 48,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt374 __devinitdata = {
	.chip_type	= HPT374,
	.max_mode	= HPT374_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 48,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt372 __devinitdata = {
	.chip_type	= HPT372,
	.max_mode	= HPT372_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 55,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt372a __devinitdata = {
	.chip_type	= HPT372A,
	.max_mode	= HPT372_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 66,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt302 __devinitdata = {
	.chip_type	= HPT302,
	.max_mode	= HPT302_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 66,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt371 __devinitdata = {
	.chip_type	= HPT371,
	.max_mode	= HPT371_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 66,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt372n __devinitdata = {
	.chip_type	= HPT372N,
	.max_mode	= HPT372_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 77,
	.settings	= hpt37x_settings
};

static struct hpt_info hpt302n __devinitdata = {
	.chip_type	= HPT302N,
	.max_mode	= HPT302_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 77,
};

static struct hpt_info hpt371n __devinitdata = {
	.chip_type	= HPT371N,
	.max_mode	= HPT371_ALLOW_ATA133_6 ? 4 : 3,
	.dpll_clk	= 77,
	.settings	= hpt37x_settings
};
Linus Torvalds's avatar
Linus Torvalds committed
505

506 507 508 509 510 511 512 513 514
static int check_in_drive_list(ide_drive_t *drive, const char **list)
{
	struct hd_driveid *id = drive->id;

	while (*list)
		if (!strcmp(*list++,id->model))
			return 1;
	return 0;
}
Linus Torvalds's avatar
Linus Torvalds committed
515

516
static u8 hpt3xx_ratemask(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
517
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
518
	struct hpt_info *info	= pci_get_drvdata(HWIF(drive)->pci_dev);
519 520
	u8 mode			= info->max_mode;

521
	if (!eighty_ninty_three(drive) && mode)
Linus Torvalds's avatar
Linus Torvalds committed
522 523 524 525 526 527 528 529 530
		mode = min(mode, (u8)1);
	return mode;
}

/*
 *	Note for the future; the SATA hpt37x we must set
 *	either PIO or UDMA modes 0,4,5
 */
 
531
static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
Linus Torvalds's avatar
Linus Torvalds committed
532
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
533 534
	struct hpt_info *info	= pci_get_drvdata(HWIF(drive)->pci_dev);
	u8 chip_type		= info->chip_type;
Linus Torvalds's avatar
Linus Torvalds committed
535 536 537 538 539
	u8 mode			= hpt3xx_ratemask(drive);

	if (drive->media != ide_disk)
		return min(speed, (u8)XFER_PIO_4);

540
	switch (mode) {
Linus Torvalds's avatar
Linus Torvalds committed
541
		case 0x04:
Sergei Shtylyov's avatar
Sergei Shtylyov committed
542
			speed = min_t(u8, speed, XFER_UDMA_6);
Linus Torvalds's avatar
Linus Torvalds committed
543 544
			break;
		case 0x03:
Sergei Shtylyov's avatar
Sergei Shtylyov committed
545 546
			speed = min_t(u8, speed, XFER_UDMA_5);
			if (chip_type >= HPT374)
Linus Torvalds's avatar
Linus Torvalds committed
547
				break;
548 549 550
			if (!check_in_drive_list(drive, bad_ata100_5))
				goto check_bad_ata33;
			/* fall thru */
Linus Torvalds's avatar
Linus Torvalds committed
551
		case 0x02:
552
			speed = min_t(u8, speed, XFER_UDMA_4);
Sergei Shtylyov's avatar
Sergei Shtylyov committed
553 554 555 556 557

			/*
			 * CHECK ME, Does this need to be changed to HPT374 ??
			 */
			if (chip_type >= HPT370)
558 559 560 561 562
				goto check_bad_ata33;
			if (HPT366_ALLOW_ATA66_4 &&
			    !check_in_drive_list(drive, bad_ata66_4))
				goto check_bad_ata33;

563
			speed = min_t(u8, speed, XFER_UDMA_3);
564 565 566 567
			if (HPT366_ALLOW_ATA66_3 &&
			    !check_in_drive_list(drive, bad_ata66_3))
				goto check_bad_ata33;
			/* fall thru */
Linus Torvalds's avatar
Linus Torvalds committed
568
		case 0x01:
569
			speed = min_t(u8, speed, XFER_UDMA_2);
570 571

		check_bad_ata33:
Sergei Shtylyov's avatar
Sergei Shtylyov committed
572
			if (chip_type >= HPT370A)
Linus Torvalds's avatar
Linus Torvalds committed
573
				break;
574 575 576
			if (!check_in_drive_list(drive, bad_ata33))
				break;
			/* fall thru */
Linus Torvalds's avatar
Linus Torvalds committed
577 578
		case 0x00:
		default:
579
			speed = min_t(u8, speed, XFER_MW_DMA_2);
Linus Torvalds's avatar
Linus Torvalds committed
580 581 582 583 584
			break;
	}
	return speed;
}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
585
static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds's avatar
Linus Torvalds committed
586
{
587 588 589 590 591 592 593 594 595 596 597
	int i;

	/*
	 * Lookup the transfer mode table to get the index into
	 * the timing table.
	 *
	 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
	 */
	for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
		if (xfer_speeds[i] == speed)
			break;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
598 599 600 601 602
	/*
	 * NOTE: info->settings only points to the pointer
	 * to the list of the actual register values
	 */
	return (*info->settings)[i];
Linus Torvalds's avatar
Linus Torvalds committed
603 604 605 606
}

static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
{
607 608
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev  *dev	= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
609
	struct hpt_info	*info	= pci_get_drvdata(dev);
610 611
	u8  speed		= hpt3xx_ratefilter(drive, xferspeed);
	u8  itr_addr		= drive->dn ? 0x44 : 0x40;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
612 613 614
	u32 itr_mask		= speed < XFER_MW_DMA_0 ? 0x30070000 :
				 (speed < XFER_UDMA_0   ? 0xc0070000 : 0xc03800ff);
	u32 new_itr		= get_speed_setting(speed, info);
615
	u32 old_itr		= 0;
616

Linus Torvalds's avatar
Linus Torvalds committed
617
	/*
618 619
	 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
	 * to avoid problems handling I/O errors later
Linus Torvalds's avatar
Linus Torvalds committed
620
	 */
621 622 623
	pci_read_config_dword(dev, itr_addr, &old_itr);
	new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
	new_itr &= ~0xc0000000;
Linus Torvalds's avatar
Linus Torvalds committed
624

625
	pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds's avatar
Linus Torvalds committed
626 627 628 629

	return ide_config_drive_speed(drive, speed);
}

630
static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
Linus Torvalds's avatar
Linus Torvalds committed
631
{
632 633
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev  *dev	= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
634
	struct hpt_info	*info	= pci_get_drvdata(dev);
635 636
	u8  speed		= hpt3xx_ratefilter(drive, xferspeed);
	u8  itr_addr		= 0x40 + (drive->dn * 4);
Sergei Shtylyov's avatar
Sergei Shtylyov committed
637 638 639
	u32 itr_mask		= speed < XFER_MW_DMA_0 ? 0x303c0000 :
				 (speed < XFER_UDMA_0   ? 0xc03c0000 : 0xc1c001ff);
	u32 new_itr		= get_speed_setting(speed, info);
640
	u32 old_itr		= 0;
Linus Torvalds's avatar
Linus Torvalds committed
641

642 643
	pci_read_config_dword(dev, itr_addr, &old_itr);
	new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
Linus Torvalds's avatar
Linus Torvalds committed
644
	
645
	if (speed < XFER_MW_DMA_0)
646 647
		new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
	pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds's avatar
Linus Torvalds committed
648 649 650 651

	return ide_config_drive_speed(drive, speed);
}

652
static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
Linus Torvalds's avatar
Linus Torvalds committed
653
{
654
	ide_hwif_t *hwif	= HWIF(drive);
Sergei Shtylyov's avatar
Sergei Shtylyov committed
655
	struct hpt_info	*info	= pci_get_drvdata(hwif->pci_dev);
Linus Torvalds's avatar
Linus Torvalds committed
656

Sergei Shtylyov's avatar
Sergei Shtylyov committed
657
	if (info->chip_type >= HPT370)
658
		return hpt37x_tune_chipset(drive, speed);
Linus Torvalds's avatar
Linus Torvalds committed
659 660 661 662
	else	/* hpt368: hpt_minimum_revision(dev, 2) */
		return hpt36x_tune_chipset(drive, speed);
}

663
static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
Linus Torvalds's avatar
Linus Torvalds committed
664
{
665 666
	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	(void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
Linus Torvalds's avatar
Linus Torvalds committed
667 668 669 670 671
}

/*
 * This allows the configuration of ide_pci chipset registers
 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
672
 * after the drive is reported by the OS.  Initially designed for
Linus Torvalds's avatar
Linus Torvalds committed
673 674 675
 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 *
 */
676
static int config_chipset_for_dma(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
677 678 679
{
	u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));

680 681 682
	if (!speed)
		return 0;

Linus Torvalds's avatar
Linus Torvalds committed
683 684 685 686
	(void) hpt3xx_tune_chipset(drive, speed);
	return ide_dma_enable(drive);
}

687
static int hpt3xx_quirkproc(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
688
{
689 690 691 692 693 694 695
	struct hd_driveid *id	= drive->id;
	const  char **list	= quirk_drives;

	while (*list)
		if (strstr(id->model, *list++))
			return 1;
	return 0;
Linus Torvalds's avatar
Linus Torvalds committed
696 697
}

698
static void hpt3xx_intrproc(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
699
{
700
	ide_hwif_t *hwif = HWIF(drive);
Linus Torvalds's avatar
Linus Torvalds committed
701 702 703 704

	if (drive->quirk_list)
		return;
	/* drives in the quirk_list may not like intr setups/cleanups */
705
	hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
Linus Torvalds's avatar
Linus Torvalds committed
706 707
}

708
static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds's avatar
Linus Torvalds committed
709
{
710 711
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev	*dev	= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
712
	struct hpt_info *info	= pci_get_drvdata(dev);
Linus Torvalds's avatar
Linus Torvalds committed
713 714

	if (drive->quirk_list) {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
715
		if (info->chip_type >= HPT370) {
716 717 718 719 720 721 722 723 724 725
			u8 scr1 = 0;

			pci_read_config_byte(dev, 0x5a, &scr1);
			if (((scr1 & 0x10) >> 4) != mask) {
				if (mask)
					scr1 |=  0x10;
				else
					scr1 &= ~0x10;
				pci_write_config_byte(dev, 0x5a, scr1);
			}
Linus Torvalds's avatar
Linus Torvalds committed
726
		} else {
727
			if (mask)
728
				disable_irq(hwif->irq);
729 730
			else
				enable_irq (hwif->irq);
Linus Torvalds's avatar
Linus Torvalds committed
731
		}
732 733 734
	} else
		hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
			   IDE_CONTROL_REG);
Linus Torvalds's avatar
Linus Torvalds committed
735 736
}

737
static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
738
{
739
	ide_hwif_t *hwif	= HWIF(drive);
Linus Torvalds's avatar
Linus Torvalds committed
740 741 742

	drive->init_speed = 0;

743 744
	if (ide_use_dma(drive) && config_chipset_for_dma(drive))
		return hwif->ide_dma_on(drive);
Linus Torvalds's avatar
Linus Torvalds committed
745

746
	if (ide_use_fast_pio(drive)) {
747
		hpt3xx_tune_drive(drive, 255);
Linus Torvalds's avatar
Linus Torvalds committed
748 749 750 751 752 753 754
		return hwif->ide_dma_off_quietly(drive);
	}
	/* IORDY not supported */
	return 0;
}

/*
755
 * This is specific to the HPT366 UDMA chipset
Linus Torvalds's avatar
Linus Torvalds committed
756 757
 * by HighPoint|Triones Technologies, Inc.
 */
758
static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
759
{
760 761 762 763 764 765 766 767 768 769
	struct pci_dev *dev = HWIF(drive)->pci_dev;
	u8 mcr1 = 0, mcr3 = 0, scr1 = 0;

	pci_read_config_byte(dev, 0x50, &mcr1);
	pci_read_config_byte(dev, 0x52, &mcr3);
	pci_read_config_byte(dev, 0x5a, &scr1);
	printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
		drive->name, __FUNCTION__, mcr1, mcr3, scr1);
	if (scr1 & 0x10)
		pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Linus Torvalds's avatar
Linus Torvalds committed
770 771 772
	return __ide_dma_lostirq(drive);
}

773
static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
774
{
775 776 777
	ide_hwif_t *hwif = HWIF(drive);

	pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
Linus Torvalds's avatar
Linus Torvalds committed
778 779 780
	udelay(10);
}

781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796
static void hpt370_irq_timeout(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u16 bfifo		= 0;
	u8  dma_cmd;

	pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
	printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);

	/* get DMA command mode */
	dma_cmd = hwif->INB(hwif->dma_command);
	/* stop DMA */
	hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
	hpt370_clear_engine(drive);
}

Linus Torvalds's avatar
Linus Torvalds committed
797 798 799 800 801 802 803 804
static void hpt370_ide_dma_start(ide_drive_t *drive)
{
#ifdef HPT_RESET_STATE_ENGINE
	hpt370_clear_engine(drive);
#endif
	ide_dma_start(drive);
}

805
static int hpt370_ide_dma_end(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
806 807
{
	ide_hwif_t *hwif	= HWIF(drive);
808
	u8  dma_stat		= hwif->INB(hwif->dma_status);
Linus Torvalds's avatar
Linus Torvalds committed
809 810 811 812 813

	if (dma_stat & 0x01) {
		/* wait a little */
		udelay(20);
		dma_stat = hwif->INB(hwif->dma_status);
814 815
		if (dma_stat & 0x01)
			hpt370_irq_timeout(drive);
Linus Torvalds's avatar
Linus Torvalds committed
816 817 818 819
	}
	return __ide_dma_end(drive);
}

820
static int hpt370_ide_dma_timeout(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
821
{
822
	hpt370_irq_timeout(drive);
Linus Torvalds's avatar
Linus Torvalds committed
823 824 825 826 827 828 829 830
	return __ide_dma_timeout(drive);
}

/* returns 1 if DMA IRQ issued, 0 otherwise */
static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u16 bfifo		= 0;
831
	u8  dma_stat;
Linus Torvalds's avatar
Linus Torvalds committed
832

833
	pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
Linus Torvalds's avatar
Linus Torvalds committed
834 835 836 837 838 839 840
	if (bfifo & 0x1FF) {
//		printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
		return 0;
	}

	dma_stat = hwif->INB(hwif->dma_status);
	/* return 1 if INTR asserted */
841
	if (dma_stat & 4)
Linus Torvalds's avatar
Linus Torvalds committed
842 843 844 845 846 847 848 849
		return 1;

	if (!drive->waiting_for_dma)
		printk(KERN_WARNING "%s: (%s) called while not waiting\n",
				drive->name, __FUNCTION__);
	return 0;
}

850
static int hpt374_ide_dma_end(ide_drive_t *drive)
Linus Torvalds's avatar
Linus Torvalds committed
851 852
{
	ide_hwif_t *hwif	= HWIF(drive);
853 854 855 856 857 858 859 860
	struct pci_dev	*dev	= hwif->pci_dev;
	u8 mcr	= 0, mcr_addr	= hwif->select_data;
	u8 bwsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	pci_read_config_byte(dev, 0x6a, &bwsr);
	pci_read_config_byte(dev, mcr_addr, &mcr);
	if (bwsr & mask)
		pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Linus Torvalds's avatar
Linus Torvalds committed
861 862 863 864
	return __ide_dma_end(drive);
}

/**
865 866 867
 *	hpt3xxn_set_clock	-	perform clock switching dance
 *	@hwif: hwif to switch
 *	@mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds's avatar
Linus Torvalds committed
868
 *
869
 *	Switch the DPLL clock on the HPT3xxN devices. This is a	right mess.
Linus Torvalds's avatar
Linus Torvalds committed
870
 */
871 872

static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds's avatar
Linus Torvalds committed
873
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
874
	u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
875 876 877 878

	if ((scr2 & 0x7f) == mode)
		return;

Linus Torvalds's avatar
Linus Torvalds committed
879
	/* Tristate the bus */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
880
	hwif->OUTB(0x80, hwif->dma_master + 0x73);
881 882
	hwif->OUTB(0x80, hwif->dma_master + 0x77);

Linus Torvalds's avatar
Linus Torvalds committed
883
	/* Switch clock and reset channels */
884 885 886
	hwif->OUTB(mode, hwif->dma_master + 0x7b);
	hwif->OUTB(0xc0, hwif->dma_master + 0x79);

Sergei Shtylyov's avatar
Sergei Shtylyov committed
887 888 889 890 891 892 893 894
	/*
	 * Reset the state machines.
	 * NOTE: avoid accidentally enabling the disabled channels.
	 */
	hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
		   hwif->dma_master + 0x70);
	hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
		   hwif->dma_master + 0x74);
895

Linus Torvalds's avatar
Linus Torvalds committed
896
	/* Complete reset */
897 898
	hwif->OUTB(0x00, hwif->dma_master + 0x79);

Linus Torvalds's avatar
Linus Torvalds committed
899
	/* Reconnect channels to bus */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
900
	hwif->OUTB(0x00, hwif->dma_master + 0x73);
901
	hwif->OUTB(0x00, hwif->dma_master + 0x77);
Linus Torvalds's avatar
Linus Torvalds committed
902 903 904
}

/**
905
 *	hpt3xxn_rw_disk		-	prepare for I/O
Linus Torvalds's avatar
Linus Torvalds committed
906 907 908
 *	@drive: drive for command
 *	@rq: block request structure
 *
909
 *	This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds's avatar
Linus Torvalds committed
910 911 912
 *	We need it because of the clock switching.
 */

913
static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds's avatar
Linus Torvalds committed
914
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
915
	hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds's avatar
Linus Torvalds committed
916 917 918
}

/* 
919
 * Set/get power state for a drive.
920
 * NOTE: affects both drives on each channel.
Linus Torvalds's avatar
Linus Torvalds committed
921
 *
922
 * When we turn the power back on, we need to re-initialize things.
Linus Torvalds's avatar
Linus Torvalds committed
923 924
 */
#define TRISTATE_BIT  0x8000
925 926

static int hpt3xx_busproc(ide_drive_t *drive, int state)
Linus Torvalds's avatar
Linus Torvalds committed
927
{
928
	ide_hwif_t *hwif	= HWIF(drive);
Linus Torvalds's avatar
Linus Torvalds committed
929
	struct pci_dev *dev	= hwif->pci_dev;
930 931 932 933
	u8  mcr_addr		= hwif->select_data + 2;
	u8  resetmask		= hwif->channel ? 0x80 : 0x40;
	u8  bsr2		= 0;
	u16 mcr			= 0;
Linus Torvalds's avatar
Linus Torvalds committed
934 935 936

	hwif->bus_state = state;

937
	/* Grab the status. */
938 939
	pci_read_config_word(dev, mcr_addr, &mcr);
	pci_read_config_byte(dev, 0x59, &bsr2);
Linus Torvalds's avatar
Linus Torvalds committed
940

941 942 943 944
	/*
	 * Set the state. We don't set it if we don't need to do so.
	 * Make sure that the drive knows that it has failed if it's off.
	 */
Linus Torvalds's avatar
Linus Torvalds committed
945 946
	switch (state) {
	case BUSSTATE_ON:
947
		if (!(bsr2 & resetmask))
Linus Torvalds's avatar
Linus Torvalds committed
948
			return 0;
949 950
		hwif->drives[0].failures = hwif->drives[1].failures = 0;

951 952
		pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
		pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
953
		return 0;
Linus Torvalds's avatar
Linus Torvalds committed
954
	case BUSSTATE_OFF:
955
		if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
Linus Torvalds's avatar
Linus Torvalds committed
956
			return 0;
957
		mcr &= ~TRISTATE_BIT;
Linus Torvalds's avatar
Linus Torvalds committed
958 959
		break;
	case BUSSTATE_TRISTATE:
960
		if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
Linus Torvalds's avatar
Linus Torvalds committed
961
			return 0;
962
		mcr |= TRISTATE_BIT;
Linus Torvalds's avatar
Linus Torvalds committed
963
		break;
964 965
	default:
		return -EINVAL;
Linus Torvalds's avatar
Linus Torvalds committed
966 967
	}

968 969 970
	hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
	hwif->drives[1].failures = hwif->drives[1].max_failures + 1;

971 972
	pci_write_config_word(dev, mcr_addr, mcr);
	pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
Linus Torvalds's avatar
Linus Torvalds committed
973 974 975
	return 0;
}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
976 977 978 979 980 981 982 983
/**
 *	hpt37x_calibrate_dpll	-	calibrate the DPLL
 *	@dev: PCI device
 *
 *	Perform a calibration cycle on the DPLL.
 *	Returns 1 if this succeeds
 */
static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds's avatar
Linus Torvalds committed
984
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
985 986 987
	u32 dpll = (f_high << 16) | f_low | 0x100;
	u8  scr2;
	int i;
988

Sergei Shtylyov's avatar
Sergei Shtylyov committed
989
	pci_write_config_dword(dev, 0x5c, dpll);
990

Sergei Shtylyov's avatar
Sergei Shtylyov committed
991 992 993 994 995
	/* Wait for oscillator ready */
	for(i = 0; i < 0x5000; ++i) {
		udelay(50);
		pci_read_config_byte(dev, 0x5b, &scr2);
		if (scr2 & 0x80)
996 997
			break;
	}
Sergei Shtylyov's avatar
Sergei Shtylyov committed
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008
	/* See if it stays ready (we'll just bail out if it's not yet) */
	for(i = 0; i < 0x1000; ++i) {
		pci_read_config_byte(dev, 0x5b, &scr2);
		/* DPLL destabilized? */
		if(!(scr2 & 0x80))
			return 0;
	}
	/* Turn off tuning, we have the DPLL set */
	pci_read_config_dword (dev, 0x5c, &dpll);
	pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
	return 1;
1009 1010
}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1011
static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1012
{
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022
	struct hpt_info *info	= kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
	unsigned long io_base	= pci_resource_start(dev, 4);
	u8 pci_clk,  dpll_clk	= 0;	/* PCI and DPLL clock in MHz */
	enum ata_clock	clock;

	if (info == NULL) {
		printk(KERN_ERR "%s: out of memory!\n", name);
		return -ENOMEM;
	}

Linus Torvalds's avatar
Linus Torvalds committed
1023
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1024 1025
	 * Copy everything from a static "template" structure
	 * to just allocated per-chip hpt_info structure.
Linus Torvalds's avatar
Linus Torvalds committed
1026
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1027
	*info = *(struct hpt_info *)pci_get_drvdata(dev);
Linus Torvalds's avatar
Linus Torvalds committed
1028 1029

	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1030 1031
	 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
	 * We don't seem to be using it.
Linus Torvalds's avatar
Linus Torvalds committed
1032
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1033 1034 1035 1036 1037 1038 1039 1040
	if (dev->resource[PCI_ROM_RESOURCE].start)
		pci_write_config_dword(dev, PCI_ROM_ADDRESS,
			dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1041

Linus Torvalds's avatar
Linus Torvalds committed
1042
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1043
	 * First, try to estimate the PCI clock frequency...
Linus Torvalds's avatar
Linus Torvalds committed
1044
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
	if (info->chip_type >= HPT370) {
		u8  scr1  = 0;
		u16 f_cnt = 0;
		u32 temp  = 0;

		/* Interrupt force enable. */
		pci_read_config_byte(dev, 0x5a, &scr1);
		if (scr1 & 0x10)
			pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);

		/*
		 * HighPoint does this for HPT372A.
		 * NOTE: This register is only writeable via I/O space.
		 */
		if (info->chip_type == HPT372A)
			outb(0x0e, io_base + 0x9c);

		/*
		 * Default to PCI clock. Make sure MA15/16 are set to output
		 * to prevent drives having problems with 40-pin cables.
		 */
		pci_write_config_byte(dev, 0x5b, 0x23);
1067

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109
		/*
		 * We'll have to read f_CNT value in order to determine
		 * the PCI clock frequency according to the following ratio:
		 *
		 * f_CNT = Fpci * 192 / Fdpll
		 *
		 * First try reading the register in which the HighPoint BIOS
		 * saves f_CNT value before  reprogramming the DPLL from its
		 * default setting (which differs for the various chips).
		 * NOTE: This register is only accessible via I/O space.
		 *
		 * In case the signature check fails, we'll have to resort to
		 * reading the f_CNT register itself in hopes that nobody has
		 * touched the DPLL yet...
		 */
		temp = inl(io_base + 0x90);
		if ((temp & 0xFFFFF000) != 0xABCDE000) {
			int i;

			printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
			       name);

			/* Calculate the average value of f_CNT. */
			for (temp = i = 0; i < 128; i++) {
				pci_read_config_word(dev, 0x78, &f_cnt);
				temp += f_cnt & 0x1ff;
				mdelay(1);
			}
			f_cnt = temp / 128;
		} else
			f_cnt = temp & 0x1ff;

		dpll_clk = info->dpll_clk;
		pci_clk  = (f_cnt * dpll_clk) / 192;

		/* Clamp PCI clock to bands. */
		if (pci_clk < 40)
			pci_clk = 33;
		else if(pci_clk < 45)
			pci_clk = 40;
		else if(pci_clk < 55)
			pci_clk = 50;
Linus Torvalds's avatar
Linus Torvalds committed
1110
		else
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1111
			pci_clk = 66;
1112

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1113 1114
		printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
		       "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1115
	} else {
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1116 1117 1118 1119 1120 1121 1122 1123
		u32 itr1 = 0;

		pci_read_config_dword(dev, 0x40, &itr1);

		/* Detect PCI clock by looking at cmd_high_time. */
		switch((itr1 >> 8) & 0x07) {
			case 0x09:
				pci_clk = 40;
1124
				break;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1125 1126
			case 0x05:
				pci_clk = 25;
1127
				break;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1128 1129 1130
			case 0x07:
			default:
				pci_clk = 33;
1131
				break;
Linus Torvalds's avatar
Linus Torvalds committed
1132 1133
		}
	}
1134

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153
	/* Let's assume we'll use PCI clock for the ATA clock... */
	switch (pci_clk) {
		case 25:
			clock = ATA_CLOCK_25MHZ;
			break;
		case 33:
		default:
			clock = ATA_CLOCK_33MHZ;
			break;
		case 40:
			clock = ATA_CLOCK_40MHZ;
			break;
		case 50:
			clock = ATA_CLOCK_50MHZ;
			break;
		case 66:
			clock = ATA_CLOCK_66MHZ;
			break;
	}
1154

Linus Torvalds's avatar
Linus Torvalds committed
1155
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1156 1157
	 * Only try the DPLL if we don't have a table for the PCI clock that
	 * we are running at for HPT370/A, always use it  for anything newer...
1158
	 *
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1159 1160 1161
	 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
	 * We also  don't like using  the DPLL because this causes glitches
	 * on PRST-/SRST- when the state engine gets reset...
Linus Torvalds's avatar
Linus Torvalds committed
1162
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177
	if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
		u16 f_low, delta = pci_clk < 50 ? 2 : 4;
		int adjust;

		 /*
		  * Select 66 MHz DPLL clock only if UltraATA/133 mode is
		  * supported/enabled, use 50 MHz DPLL clock otherwise...
		  */
		if (info->max_mode == 0x04) {
			dpll_clk = 66;
			clock = ATA_CLOCK_66MHZ;
		} else if (dpll_clk) {	/* HPT36x chips don't have DPLL */
			dpll_clk = 50;
			clock = ATA_CLOCK_50MHZ;
		}
1178

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1179 1180 1181 1182
		if (info->settings[clock] == NULL) {
			printk(KERN_ERR "%s: unknown bus timing!\n", name);
			kfree(info);
			return -EIO;
Linus Torvalds's avatar
Linus Torvalds committed
1183 1184
		}

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218
		/* Select the DPLL clock. */
		pci_write_config_byte(dev, 0x5b, 0x21);

		/*
		 * Adjust the DPLL based upon PCI clock, enable it,
		 * and wait for stabilization...
		 */
		f_low = (pci_clk * 48) / dpll_clk;

		for (adjust = 0; adjust < 8; adjust++) {
			if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
				break;

			/*
			 * See if it'll settle at a fractionally different clock
			 */
			if (adjust & 1)
				f_low -= adjust >> 1;
			else
				f_low += adjust >> 1;
		}
		if (adjust == 8) {
			printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
			kfree(info);
			return -EIO;
		}

		printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
	} else {
		/* Mark the fact that we're not using the DPLL. */
		dpll_clk = 0;

		printk("%s: using %d MHz PCI clock\n", name, pci_clk);
	}
1219

1220
	/*
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1221 1222
	 * Advance the table pointer to a slot which points to the list
	 * of the register values settings matching the clock being used.
1223
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1224
	info->settings += clock;
Linus Torvalds's avatar
Linus Torvalds committed
1225

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1226 1227 1228
	/* Store the clock frequencies. */
	info->dpll_clk	= dpll_clk;
	info->pci_clk	= pci_clk;
Linus Torvalds's avatar
Linus Torvalds committed
1229

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1230 1231
	/* Point to this chip's own instance of the hpt_info structure. */
	pci_set_drvdata(dev, info);
1232

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244
	if (info->chip_type >= HPT370) {
		u8  mcr1, mcr4;

		/*
		 * Reset the state engines.
		 * NOTE: Avoid accidentally enabling the disabled channels.
		 */
		pci_read_config_byte (dev, 0x50, &mcr1);
		pci_read_config_byte (dev, 0x54, &mcr4);
		pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
		pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
		udelay(100);
1245
	}
Linus Torvalds's avatar
Linus Torvalds committed
1246

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1247 1248 1249 1250 1251 1252 1253 1254 1255
	/*
	 * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
	 * the MISC. register to stretch the UltraDMA Tss timing.
	 * NOTE: This register is only writeable via I/O space.
	 */
	if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)

		outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);

Linus Torvalds's avatar
Linus Torvalds committed
1256 1257 1258 1259 1260
	return dev->irq;
}

static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
{
1261
	struct pci_dev	*dev		= hwif->pci_dev;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1262
	struct hpt_info *info		= pci_get_drvdata(dev);
1263
	int serialize			= HPT_SERIALIZE_IO;
1264
	u8  scr1 = 0, ata66		= (hwif->channel) ? 0x01 : 0x02;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1265
	u8  chip_type			= info->chip_type;
1266
	u8  new_mcr, old_mcr 		= 0;
1267 1268 1269 1270

	/* Cache the channel's MISC. control registers' offset */
	hwif->select_data		= hwif->channel ? 0x54 : 0x50;

Linus Torvalds's avatar
Linus Torvalds committed
1271 1272 1273 1274 1275
	hwif->tuneproc			= &hpt3xx_tune_drive;
	hwif->speedproc			= &hpt3xx_tune_chipset;
	hwif->quirkproc			= &hpt3xx_quirkproc;
	hwif->intrproc			= &hpt3xx_intrproc;
	hwif->maskproc			= &hpt3xx_maskproc;
1276 1277
	hwif->busproc			= &hpt3xx_busproc;

1278 1279 1280 1281 1282 1283
	/*
	 * HPT3xxN chips have some complications:
	 *
	 * - on 33 MHz PCI we must clock switch
	 * - on 66 MHz PCI we must NOT use the PCI clock
	 */
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1284
	if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1285 1286 1287 1288 1289 1290 1291
		/*
		 * Clock is shared between the channels,
		 * so we'll have to serialize them... :-(
		 */
		serialize = 1;
		hwif->rw_disk = &hpt3xxn_rw_disk;
	}
Linus Torvalds's avatar
Linus Torvalds committed
1292

1293 1294 1295 1296 1297 1298 1299 1300 1301 1302
	/* Serialize access to this device if needed */
	if (serialize && hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;

	/*
	 * Disable the "fast interrupt" prediction.  Don't hold off
	 * on interrupts. (== 0x01 despite what the docs say)
	 */
	pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);

Sergei Shtylyov's avatar
Sergei Shtylyov committed
1303
	if (info->chip_type >= HPT374)
1304
		new_mcr = old_mcr & ~0x07;
Sergei Shtylyov's avatar
Sergei Shtylyov committed
1305
	else if (info->chip_type >= HPT370) {
1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
		new_mcr = old_mcr;
		new_mcr &= ~0x02;

#ifdef HPT_DELAY_INTERRUPT
		new_mcr &= ~0x01;
#else
		new_mcr |=  0x01;
#endif
	} else					/* HPT366 and HPT368  */
		new_mcr = old_mcr & ~0x80;

	if (new_mcr != old_mcr)
		pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = hwif->drives[