Kconfig 30.1 KB
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config SYMBOL_PREFIX
	string
	default "_"

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config MMU
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	def_bool n
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config FPU
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	def_bool n
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config RWSEM_GENERIC_SPINLOCK
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	def_bool y
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config RWSEM_XCHGADD_ALGORITHM
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	def_bool n
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config BLACKFIN
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	def_bool y
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	select HAVE_ARCH_KGDB
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	select HAVE_ARCH_TRACEHOOK
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	select HAVE_DYNAMIC_FTRACE
	select HAVE_FTRACE_MCOUNT_RECORD
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	select HAVE_FUNCTION_GRAPH_TRACER
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	select HAVE_FUNCTION_TRACER
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	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
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	select HAVE_IDE
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	select HAVE_IRQ_WORK
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	select HAVE_KERNEL_GZIP if RAMKERNEL
	select HAVE_KERNEL_BZIP2 if RAMKERNEL
	select HAVE_KERNEL_LZMA if RAMKERNEL
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	select HAVE_KERNEL_LZO if RAMKERNEL
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	select HAVE_OPROFILE
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	select HAVE_PERF_EVENTS
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	select ARCH_HAVE_CUSTOM_GPIO_H
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	select ARCH_WANT_OPTIONAL_GPIOLIB
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	select HAVE_GENERIC_HARDIRQS
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	select GENERIC_ATOMIC64
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	select GENERIC_IRQ_PROBE
	select IRQ_PER_CPU if SMP
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	select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
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config GENERIC_CSUM
	def_bool y

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config GENERIC_BUG
	def_bool y
	depends on BUG

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config ZONE_DMA
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	def_bool y
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config GENERIC_GPIO
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	def_bool y
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config FORCE_MAX_ZONEORDER
	int
	default "14"

config GENERIC_CALIBRATE_DELAY
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	def_bool y
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config LOCKDEP_SUPPORT
	def_bool y

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config STACKTRACE_SUPPORT
	def_bool y

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config TRACE_IRQFLAGS_SUPPORT
	def_bool y
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source "init/Kconfig"
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source "kernel/Kconfig.preempt"

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source "kernel/Kconfig.freezer"

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menu "Blackfin Processor Options"

comment "Processor and Board Settings"

choice
	prompt "CPU"
	default BF533

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config BF512
	bool "BF512"
	help
	  BF512 Processor Support.

config BF514
	bool "BF514"
	help
	  BF514 Processor Support.

config BF516
	bool "BF516"
	help
	  BF516 Processor Support.

config BF518
	bool "BF518"
	help
	  BF518 Processor Support.

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config BF522
	bool "BF522"
	help
	  BF522 Processor Support.

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config BF523
	bool "BF523"
	help
	  BF523 Processor Support.

config BF524
	bool "BF524"
	help
	  BF524 Processor Support.

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config BF525
	bool "BF525"
	help
	  BF525 Processor Support.

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config BF526
	bool "BF526"
	help
	  BF526 Processor Support.

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config BF527
	bool "BF527"
	help
	  BF527 Processor Support.

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config BF531
	bool "BF531"
	help
	  BF531 Processor Support.

config BF532
	bool "BF532"
	help
	  BF532 Processor Support.

config BF533
	bool "BF533"
	help
	  BF533 Processor Support.

config BF534
	bool "BF534"
	help
	  BF534 Processor Support.

config BF536
	bool "BF536"
	help
	  BF536 Processor Support.

config BF537
	bool "BF537"
	help
	  BF537 Processor Support.

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config BF538
	bool "BF538"
	help
	  BF538 Processor Support.

config BF539
	bool "BF539"
	help
	  BF539 Processor Support.

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config BF542_std
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	bool "BF542"
	help
	  BF542 Processor Support.

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config BF542M
	bool "BF542m"
	help
	  BF542 Processor Support.

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config BF544_std
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	bool "BF544"
	help
	  BF544 Processor Support.

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config BF544M
	bool "BF544m"
	help
	  BF544 Processor Support.

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config BF547_std
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	bool "BF547"
	help
	  BF547 Processor Support.

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config BF547M
	bool "BF547m"
	help
	  BF547 Processor Support.

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config BF548_std
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	bool "BF548"
	help
	  BF548 Processor Support.

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config BF548M
	bool "BF548m"
	help
	  BF548 Processor Support.

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config BF549_std
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	bool "BF549"
	help
	  BF549 Processor Support.

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config BF549M
	bool "BF549m"
	help
	  BF549 Processor Support.

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config BF561
	bool "BF561"
	help
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	  BF561 Processor Support.
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endchoice

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config SMP
	depends on BF561
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	select TICKSOURCE_CORETMR
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	bool "Symmetric multi-processing support"
	---help---
	  This enables support for systems with more than one CPU,
	  like the dual core BF561. If you have a system with only one
	  CPU, say N. If you have a system with more than one CPU, say Y.

	  If you don't know what to do here, say N.

config NR_CPUS
	int
	depends on SMP
	default 2 if BF561

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config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	depends on SMP && HOTPLUG
	default y

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config BF_REV_MIN
	int
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	default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
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	default 2 if (BF537 || BF536 || BF534)
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	default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
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	default 4 if (BF538 || BF539)
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config BF_REV_MAX
	int
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	default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
	default 3 if (BF537 || BF536 || BF534 || BF54xM)
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	default 5 if (BF561 || BF538 || BF539)
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	default 6 if (BF533 || BF532 || BF531)

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choice
	prompt "Silicon Rev"
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	default BF_REV_0_0 if (BF51x || BF52x)
	default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
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	default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
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config BF_REV_0_0
	bool "0.0"
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	depends on (BF51x || BF52x || (BF54x && !BF54xM))
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config BF_REV_0_1
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	bool "0.1"
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	depends on (BF51x || BF52x || (BF54x && !BF54xM))
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config BF_REV_0_2
	bool "0.2"
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	depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
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config BF_REV_0_3
	bool "0.3"
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	depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
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config BF_REV_0_4
	bool "0.4"
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	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
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config BF_REV_0_5
	bool "0.5"
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	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
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config BF_REV_0_6
	bool "0.6"
	depends on (BF533 || BF532 || BF531)

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config BF_REV_ANY
	bool "any"

config BF_REV_NONE
	bool "none"

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endchoice

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config BF53x
	bool
	depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
	default y

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config MEM_MT48LC64M4A2FB_7E
	bool
	depends on (BFIN533_STAMP)
	default y

config MEM_MT48LC16M16A2TG_75
	bool
	depends on (BFIN533_EZKIT || BFIN561_EZKIT \
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		|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
		|| BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
		|| BFIN527_BLUETECHNIX_CM)
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	default y

config MEM_MT48LC32M8A2_75
	bool
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	depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
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	default y

config MEM_MT48LC8M32B2B5_7
	bool
	depends on (BFIN561_BLUETECHNIX_CM)
	default y

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config MEM_MT48LC32M16A2TG_75
	bool
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	depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
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	default y

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config MEM_MT48H32M16LFCJ_75
	bool
	depends on (BFIN526_EZBRD)
	default y

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source "arch/blackfin/mach-bf518/Kconfig"
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source "arch/blackfin/mach-bf527/Kconfig"
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source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
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source "arch/blackfin/mach-bf538/Kconfig"
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source "arch/blackfin/mach-bf548/Kconfig"
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menu "Board customizations"

config CMDLINE_BOOL
	bool "Default bootloader kernel arguments"

config CMDLINE
	string "Initial kernel command string"
	depends on CMDLINE_BOOL
	default "console=ttyBF0,57600"
	help
	  If you don't have a boot loader capable of passing a command line string
	  to the kernel, you may specify one here. As a minimum, you should specify
	  the memory size and the root device (e.g., mem=8M, root=/dev/nfs).

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config BOOT_LOAD
	hex "Kernel load address for booting"
	default "0x1000"
	range 0x1000 0x20000000
	help
	  This option allows you to set the load address of the kernel.
	  This can be useful if you are on a board which has a small amount
	  of memory or you wish to reserve some memory at the beginning of
	  the address space.

	  Note that you need to keep this value above 4k (0x1000) as this
	  memory region is used to capture NULL pointer references as well
	  as some core kernel functions.

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config ROM_BASE
	hex "Kernel ROM Base"
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	depends on ROMKERNEL
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	default "0x20040040"
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	range 0x20000000 0x20400000 if !(BF54x || BF561)
	range 0x20000000 0x30000000 if (BF54x || BF561)
	help
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	  Make sure your ROM base does not include any file-header
	  information that is prepended to the kernel.

	  For example, the bootable U-Boot format (created with
	  mkimage) has a 64 byte header (0x40).  So while the image
	  you write to flash might start at say 0x20080000, you have
	  to add 0x40 to get the kernel's ROM base as it will come
	  after the header.
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comment "Clock/PLL Setup"
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config CLKIN_HZ
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	int "Frequency of the crystal on the board in Hz"
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	default "10000000" if BFIN532_IP0X
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	default "11059200" if BFIN533_STAMP
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	default "24576000" if PNAV10
	default "25000000" # most people use this
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	default "27000000" if BFIN533_EZKIT
	default "30000000" if BFIN561_EZKIT
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	default "24000000" if BFIN527_AD7160EVAL
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	help
	  The frequency of CLKIN crystal oscillator on the board in Hz.
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	  Warning: This value should match the crystal on the board. Otherwise,
	  peripherals won't work properly.
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config BFIN_KERNEL_CLOCK
	bool "Re-program Clocks while Kernel boots?"
	default n
	help
	  This option decides if kernel clocks are re-programed from the
	  bootloader settings. If the clocks are not set, the SDRAM settings
	  are also not changed, and the Bootloader does 100% of the hardware
	  configuration.

config PLL_BYPASS
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	bool "Bypass PLL"
	depends on BFIN_KERNEL_CLOCK
	default n
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config CLKIN_HALF
	bool "Half Clock In"
	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
	default n
	help
	  If this is set the clock will be divided by 2, before it goes to the PLL.

config VCO_MULT
	int "VCO Multiplier"
	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
	range 1 64
	default "22" if BFIN533_EZKIT
	default "45" if BFIN533_STAMP
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	default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
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	default "22" if BFIN533_BLUETECHNIX_CM
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	default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
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	default "20" if BFIN561_EZKIT
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	default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
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	default "25" if BFIN527_AD7160EVAL
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	help
	  This controls the frequency of the on-chip PLL. This can be between 1 and 64.
	  PLL Frequency = (Crystal Frequency) * (this setting)

choice
	prompt "Core Clock Divider"
	depends on BFIN_KERNEL_CLOCK
	default CCLK_DIV_1
	help
	  This sets the frequency of the core. It can be 1, 2, 4 or 8
	  Core Frequency = (PLL frequency) / (this setting)

config CCLK_DIV_1
	bool "1"

config CCLK_DIV_2
	bool "2"

config CCLK_DIV_4
	bool "4"

config CCLK_DIV_8
	bool "8"
endchoice

config SCLK_DIV
	int "System Clock Divider"
	depends on BFIN_KERNEL_CLOCK
	range 1 15
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	default 5
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	help
	  This sets the frequency of the system clock (including SDRAM or DDR).
	  This can be between 1 and 15
	  System Clock = (PLL frequency) / (this setting)

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choice
	prompt "DDR SDRAM Chip Type"
	depends on BFIN_KERNEL_CLOCK
	depends on BF54x
	default MEM_MT46V32M16_5B

config MEM_MT46V32M16_6T
	bool "MT46V32M16_6T"

config MEM_MT46V32M16_5B
	bool "MT46V32M16_5B"
endchoice

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choice
	prompt "DDR/SDRAM Timing"
	depends on BFIN_KERNEL_CLOCK
	default BFIN_KERNEL_CLOCK_MEMINIT_CALC
	help
	  This option allows you to specify Blackfin SDRAM/DDR Timing parameters
	  The calculated SDRAM timing parameters may not be 100%
	  accurate - This option is therefore marked experimental.

config BFIN_KERNEL_CLOCK_MEMINIT_CALC
	bool "Calculate Timings (EXPERIMENTAL)"
	depends on EXPERIMENTAL

config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
	bool "Provide accurate Timings based on target SCLK"
	help
	  Please consult the Blackfin Hardware Reference Manuals as well
	  as the memory device datasheet.
	  http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
endchoice

menu "Memory Init Control"
	depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC

config MEM_DDRCTL0
	depends on BF54x
	hex "DDRCTL0"
	default 0x0

config MEM_DDRCTL1
	depends on BF54x
	hex "DDRCTL1"
	default 0x0

config MEM_DDRCTL2
	depends on BF54x
	hex "DDRCTL2"
	default 0x0

config MEM_EBIU_DDRQUE
	depends on BF54x
	hex "DDRQUE"
	default 0x0

config MEM_SDRRC
	depends on !BF54x
	hex "SDRRC"
	default 0x0

config MEM_SDGCTL
	depends on !BF54x
	hex "SDGCTL"
	default 0x0
endmenu

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#
# Max & Min Speeds for various Chips
#
config MAX_VCO_HZ
	int
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	default 400000000 if BF512
	default 400000000 if BF514
	default 400000000 if BF516
	default 400000000 if BF518
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	default 400000000 if BF522
	default 600000000 if BF523
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	default 400000000 if BF524
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	default 600000000 if BF525
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	default 400000000 if BF526
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	default 600000000 if BF527
	default 400000000 if BF531
	default 400000000 if BF532
	default 750000000 if BF533
	default 500000000 if BF534
	default 400000000 if BF536
	default 600000000 if BF537
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	default 533333333 if BF538
	default 533333333 if BF539
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	default 600000000 if BF542
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	default 533333333 if BF544
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	default 600000000 if BF547
	default 600000000 if BF548
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	default 533333333 if BF549
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	default 600000000 if BF561

config MIN_VCO_HZ
	int
	default 50000000

config MAX_SCLK_HZ
	int
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	default 133333333
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config MIN_SCLK_HZ
	int
	default 27000000

comment "Kernel Timer/Scheduler"

source kernel/Kconfig.hz

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config GENERIC_CLOCKEVENTS
	bool "Generic clock events"
	default y

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menu "Clock event device"
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	depends on GENERIC_CLOCKEVENTS
config TICKSOURCE_GPTMR0
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	bool "GPTimer0"
	depends on !SMP
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	select BFIN_GPTIMERS

config TICKSOURCE_CORETMR
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	bool "Core timer"
	default y
endmenu
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menu "Clock souce"
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	depends on GENERIC_CLOCKEVENTS
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config CYCLES_CLOCKSOURCE
	bool "CYCLES"
	default y
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	depends on !BFIN_SCRATCH_REG_CYCLES
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	depends on !SMP
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	help
	  If you say Y here, you will enable support for using the 'cycles'
	  registers as a clock source.  Doing so means you will be unable to
	  safely write to the 'cycles' register during runtime.  You will
	  still be able to read it (such as for performance monitoring), but
	  writing the registers will most likely crash the kernel.

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config GPTMR0_CLOCKSOURCE
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	bool "GPTimer0"
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	select BFIN_GPTIMERS
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	depends on !TICKSOURCE_GPTMR0
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endmenu
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config ARCH_USES_GETTIMEOFFSET
	depends on !GENERIC_CLOCKEVENTS
	def_bool y

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source kernel/time/Kconfig

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comment "Misc"
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choice
	prompt "Blackfin Exception Scratch Register"
	default BFIN_SCRATCH_REG_RETN
	help
	  Select the resource to reserve for the Exception handler:
	    - RETN: Non-Maskable Interrupt (NMI)
	    - RETE: Exception Return (JTAG/ICE)
	    - CYCLES: Performance counter

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_RETN
	bool "RETN"
	help
	  Use the RETN register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use NMI on the Blackfin while running Linux, but
	  you can debug the system with a JTAG ICE and use the
	  CYCLES performance registers.

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_RETE
	bool "RETE"
	help
	  Use the RETE register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use a JTAG ICE while debugging a Blackfin board,
	  but you can safely use the CYCLES performance registers
	  and the NMI.

	  If you are unsure, please select "RETN".

config BFIN_SCRATCH_REG_CYCLES
	bool "CYCLES"
	help
	  Use the CYCLES register in the Blackfin exception handler
	  as a stack scratch register.  This means you cannot
	  safely use the CYCLES performance registers on a Blackfin
	  board at anytime, but you can debug the system with a JTAG
	  ICE and use the NMI.

	  If you are unsure, please select "RETN".

endchoice

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endmenu


menu "Blackfin Kernel Optimizations"

comment "Memory Optimizations"

config I_ENTRY_L1
	bool "Locate interrupt entry code in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
	  into L1 instruction memory. (less latency)
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config EXCPT_IRQ_SYSC_L1
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	bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
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	default y
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	depends on !SMP
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	help
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	  If enabled, the entire ASM lowlevel exception and interrupt entry code
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	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
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	  (less latency)
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config DO_IRQ_L1
	bool "Locate frequently called do_irq dispatcher function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the frequently called do_irq dispatcher function is linked
	  into L1 instruction memory. (less latency)
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config CORE_TIMER_IRQ_L1
	bool "Locate frequently called timer_interrupt() function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the frequently called timer_interrupt() function is linked
	  into L1 instruction memory. (less latency)
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config IDLE_L1
	bool "Locate frequently idle function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the frequently called idle function is linked
	  into L1 instruction memory. (less latency)
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config SCHEDULE_L1
	bool "Locate kernel schedule function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the frequently called kernel schedule is linked
	  into L1 instruction memory. (less latency)
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config ARITHMETIC_OPS_L1
	bool "Locate kernel owned arithmetic functions in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, arithmetic functions are linked
	  into L1 instruction memory. (less latency)
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config ACCESS_OK_L1
	bool "Locate access_ok function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the access_ok function is linked
	  into L1 instruction memory. (less latency)
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config MEMSET_L1
	bool "Locate memset function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the memset function is linked
	  into L1 instruction memory. (less latency)
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config MEMCPY_L1
	bool "Locate memcpy function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, the memcpy function is linked
	  into L1 instruction memory. (less latency)
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config STRCMP_L1
	bool "locate strcmp function in L1 Memory"
	default y
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	depends on !SMP
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	help
	  If enabled, the strcmp function is linked
	  into L1 instruction memory (less latency).

config STRNCMP_L1
	bool "locate strncmp function in L1 Memory"
	default y
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	depends on !SMP
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	help
	  If enabled, the strncmp function is linked
	  into L1 instruction memory (less latency).

config STRCPY_L1
	bool "locate strcpy function in L1 Memory"
	default y
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	depends on !SMP
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	help
	  If enabled, the strcpy function is linked
	  into L1 instruction memory (less latency).

config STRNCPY_L1
	bool "locate strncpy function in L1 Memory"
	default y
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	depends on !SMP
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	help
	  If enabled, the strncpy function is linked
	  into L1 instruction memory (less latency).

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config SYS_BFIN_SPINLOCK_L1
	bool "Locate sys_bfin_spinlock function in L1 Memory"
	default y
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	depends on !SMP
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	help
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	  If enabled, sys_bfin_spinlock function is linked
	  into L1 instruction memory. (less latency)
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config IP_CHECKSUM_L1
	bool "Locate IP Checksum function in L1 Memory"
	default n
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	depends on !SMP
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	help
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	  If enabled, the IP Checksum function is linked
	  into L1 instruction memory. (less latency)
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config CACHELINE_ALIGNED_L1
	bool "Locate cacheline_aligned data to L1 Data Memory"
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	default y if !BF54x
	default n if BF54x
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	depends on !SMP && !BF531 && !CRC32
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	help
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	  If enabled, cacheline_aligned data is linked
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	  into L1 data memory. (less latency)
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config SYSCALL_TAB_L1
	bool "Locate Syscall Table L1 Data Memory"
	default n
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	depends on !SMP && !BF531
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	help
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	  If enabled, the Syscall LUT is linked
	  into L1 data memory. (less latency)
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config CPLB_SWITCH_TAB_L1
	bool "Locate CPLB Switch Tables L1 Data Memory"
	default n
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	depends on !SMP && !BF531
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	help
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	  If enabled, the CPLB Switch Tables are linked
	  into L1 data memory. (less latency)
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config ICACHE_FLUSH_L1
	bool "Locate icache flush funcs in L1 Inst Memory"
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	default y
	help
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	  If enabled, the Blackfin icache flushing functions are linked
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	  into L1 instruction memory.

	  Note that this might be required to address anomalies, but
	  these functions are pretty small, so it shouldn't be too bad.
	  If you are using a processor affected by an anomaly, the build
	  system will double check for you and prevent it.

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config DCACHE_FLUSH_L1
	bool "Locate dcache flush funcs in L1 Inst Memory"
	default y
	depends on !SMP
	help
	  If enabled, the Blackfin dcache flushing functions are linked
	  into L1 instruction memory.

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config APP_STACK_L1
	bool "Support locating application stack in L1 Scratch Memory"
	default y
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	depends on !SMP
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	help
	  If enabled the application stack can be located in L1
	  scratch memory (less latency).

	  Currently only works with FLAT binaries.

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config EXCEPTION_L1_SCRATCH
	bool "Locate exception stack in L1 Scratch Memory"
	default n
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	depends on !SMP && !APP_STACK_L1
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	help
	  Whenever an exception occurs, use the L1 Scratch memory for
	  stack storage.  You cannot place the stacks of FLAT binaries
	  in L1 when using this option.

	  If you don't use L1 Scratch, then you should say Y here.

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comment "Speed Optimizations"
config BFIN_INS_LOWOVERHEAD
	bool "ins[bwl] low overhead, higher interrupt latency"
	default y
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	depends on !SMP
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	help
	  Reads on the Blackfin are speculative. In Blackfin terms, this means
	  they can be interrupted at any time (even after they have been issued
	  on to the external bus), and re-issued after the interrupt occurs.
	  For memory - this is not a big deal, since memory does not change if
	  it sees a read.

	  If a FIFO is sitting on the end of the read, it will see two reads,
	  when the core only sees one since the FIFO receives both the read
	  which is cancelled (and not delivered to the core) and the one which
	  is re-issued (which is delivered to the core).

	  To solve this, interrupts are turned off before reads occur to
	  I/O space. This option controls which the overhead/latency of
	  controlling interrupts during this time
	   "n" turns interrupts off every read
		(higher overhead, but lower interrupt latency)
	   "y" turns interrupts off every loop
		(low overhead, but longer interrupt latency)

	  default behavior is to leave this set to on (type "Y"). If you are experiencing
	  interrupt latency issues, it is safe and OK to turn this off.

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endmenu

choice
	prompt "Kernel executes from"
	help
	  Choose the memory type that the kernel will be running in.

config RAMKERNEL
	bool "RAM"
	help
	  The kernel will be resident in RAM when running.

config ROMKERNEL
	bool "ROM"
	help
	  The kernel will be resident in FLASH/ROM when running.

endchoice

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# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
config XIP_KERNEL
	bool
	default y
	depends on ROMKERNEL

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source "mm/Kconfig"

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config BFIN_GPTIMERS
	tristate "Enable Blackfin General Purpose Timers API"
	default n
	help
	  Enable support for the General Purpose Timers API.  If you
	  are unsure, say N.

	  To compile this driver as a module, choose M here: the module
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	  will be called gptimers.
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config HAVE_PWM
	tristate "Enable PWM API support"
	depends on BFIN_GPTIMERS
	help
	  Enable support for the Pulse Width Modulation framework (as
	  found in linux/pwm.h).

	  To compile this driver as a module, choose M here: the module
	  will be called pwm.

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choice
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	prompt "Uncached DMA region"
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	default DMA_UNCACHED_1M
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config DMA_UNCACHED_4M
	bool "Enable 4M DMA region"
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config DMA_UNCACHED_2M
	bool "Enable 2M DMA region"
config DMA_UNCACHED_1M
	bool "Enable 1M DMA region"
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config DMA_UNCACHED_512K
	bool "Enable 512K DMA region"
config DMA_UNCACHED_256K
	bool "Enable 256K DMA region"
config DMA_UNCACHED_128K
	bool "Enable 128K DMA region"
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config DMA_UNCACHED_NONE
	bool "Disable DMA region"
endchoice


comment "Cache Support"
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config BFIN_ICACHE
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	bool "Enable ICACHE"
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	default y
config BFIN_EXTMEM_ICACHEABLE
	bool "Enable ICACHE for external memory"
	depends on BFIN_ICACHE
	default y
config BFIN_L2_ICACHEABLE
	bool "Enable ICACHE for L2 SRAM"
	depends on BFIN_ICACHE
	depends on BF54x || BF561
	default n

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config BFIN_DCACHE
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	bool "Enable DCACHE"
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	default y
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config BFIN_DCACHE_BANKA
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	bool "Enable only 16k BankA DCACHE - BankB is SRAM"
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	depends on BFIN_DCACHE && !BF531
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	default n
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config BFIN_EXTMEM_DCACHEABLE
	bool "Enable DCACHE for external memory"
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	depends on BFIN_DCACHE
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	default y
choice
	prompt "External memory DCACHE policy"
	depends on BFIN_EXTMEM_DCACHEABLE
	default BFIN_EXTMEM_WRITEBACK if !SMP
	default BFIN_EXTMEM_WRITETHROUGH if SMP
config BFIN_EXTMEM_WRITEBACK
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	bool "Write back"
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	depends on !SMP
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	help
	  Write Back Policy:
	    Cached data will be written back to SDRAM only when needed.
	    This can give a nice increase in performance, but beware of
	    broken drivers that do not properly invalidate/flush their
	    cache.

	  Write Through Policy:
	    Cached data will always be written back to SDRAM when the
	    cache is updated.  This is a completely safe setting, but
	    performance is worse than Write Back.

	  If you are unsure of the options and you want to be safe,
	  then go with Write Through.

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config BFIN_EXTMEM_WRITETHROUGH
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	bool "Write through"
	help
	  Write Back Policy:
	    Cached data will be written back to SDRAM only when needed.
	    This can give a nice increase in performance, but beware of
	    broken drivers that do not properly invalidate/flush their
	    cache.

	  Write Through Policy:
	    Cached data will always be written back to SDRAM when the
	    cache is updated.  This is a completely safe setting, but
	    performance is worse than Write Back.

	  If you are unsure of the options and you want to be safe,
	  then go with Write Through.

endchoice

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config BFIN_L2_DCACHEABLE
	bool "Enable DCACHE for L2 SRAM"
	depends on BFIN_DCACHE
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	depends on (BF54x || BF561) && !SMP
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	default n
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choice
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	prompt "L2 SRAM DCACHE policy"
	depends on BFIN_L2_DCACHEABLE
	default BFIN_L2_WRITEBACK
config BFIN_L2_WRITEBACK
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	bool "Write back"

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config BFIN_L2_WRITETHROUGH
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	bool "Write through"
endchoice
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comment "Memory Protection Unit"
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config MPU
	bool "Enable the memory protection unit (EXPERIMENTAL)"
	default n
	help
	  Use the processor's MPU to protect applications from accessing
	  memory they do not own.  This comes at a performance penalty
	  and is recommended only for debugging.

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comment "Asynchronous Memory Configuration"
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menu "EBIU_AMGCTL Global Control"
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config C_AMCKEN
	bool "Enable CLKOUT"
	default y

config C_CDPRIO
	bool "DMA has priority over core for ext. accesses"
	default n

config C_B0PEN
	depends on BF561
	bool "Bank 0 16 bit packing enable"
	default y

config C_B1PEN
	depends on BF561
	bool "Bank 1 16 bit packing enable"
	default y

config C_B2PEN
	depends on BF561
	bool "Bank 2 16 bit packing enable"
	default y

config C_B3PEN
	depends on BF561
	bool "Bank 3 16 bit packing enable"
	default n

choice
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	prompt "Enable Asynchronous Memory Banks"
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	default C_AMBEN_ALL

config C_AMBEN
	bool "Disable All Banks"

config C_AMBEN_B0
	bool "Enable Bank 0"

config C_AMBEN_B0_B1
	bool "Enable Bank 0 & 1"

config C_AMBEN_B0_B1_B2
	bool "Enable Bank 0 & 1 & 2"

config C_AMBEN_ALL
	bool "Enable All Banks"
endchoice
endmenu

menu "EBIU_AMBCTL Control"
config BANK_0
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	hex "Bank 0 (AMBCTL0.L)"
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	default 0x7BB0
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	help
	  These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
	  used to control the Asynchronous Memory Bank 0 settings.
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config BANK_1
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	hex "Bank 1 (AMBCTL0.H)"
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	default 0x7BB0
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	default 0x5558 if BF54x
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	help
	  These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
	  used to control the Asynchronous Memory Bank 1 settings.
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config BANK_2
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	hex "Bank 2 (AMBCTL1.L)"
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	default 0x7BB0
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	help
	  These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
	  used to control the Asynchronous Memory Bank 2 settings.
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config BANK_3
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	hex "Bank 3 (AMBCTL1.H)"
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	default 0x99B3
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	help
	  These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
	  used to control the Asynchronous Memory Bank 3 settings.

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endmenu

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config EBIU_MBSCTLVAL
	hex "EBIU Bank Select Control Register"
	depends on BF54x
	default 0

config EBIU_MODEVAL
	hex "Flash Memory Mode Control Register"
	depends on BF54x
	default 1

config EBIU_FCTLVAL
	hex "Flash Memory Bank Control Register"
	depends on BF54x
	default 6
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endmenu

#############################################################################
menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"

config PCI
	bool "PCI support"
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	depends on BROKEN
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	help
	  Support for PCI bus.

source "drivers/pci/Kconfig"

source "drivers/pcmcia/Kconfig"

source "drivers/pci/hotplug/Kconfig"

endmenu

menu "Executable file formats"

source "fs/Kconfig.binfmt"

endmenu

menu "Power management options"
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source "kernel/power/Kconfig"

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config ARCH_SUSPEND_POSSIBLE
	def_bool y