main.c 59.5 KB
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/*
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 * Copyright (c) 2008-2011 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
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#include <linux/delay.h>
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#include "ath9k.h"
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#include "btcoex.h"
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static u8 parse_mpdudensity(u8 mpdudensity)
{
	/*
	 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
	 *   0 for no restriction
	 *   1 for 1/4 us
	 *   2 for 1/2 us
	 *   3 for 1 us
	 *   4 for 2 us
	 *   5 for 4 us
	 *   6 for 8 us
	 *   7 for 16 us
	 */
	switch (mpdudensity) {
	case 0:
		return 0;
	case 1:
	case 2:
	case 3:
		/* Our lower layer calculations limit our precision to
		   1 microsecond */
		return 1;
	case 4:
		return 2;
	case 5:
		return 4;
	case 6:
		return 8;
	case 7:
		return 16;
	default:
		return 0;
	}
}

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static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
{
	bool pending = false;

	spin_lock_bh(&txq->axq_lock);

	if (txq->axq_depth || !list_empty(&txq->axq_acq))
		pending = true;

	spin_unlock_bh(&txq->axq_lock);
	return pending;
}

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static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
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{
	unsigned long flags;
	bool ret;

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	spin_lock_irqsave(&sc->sc_pm_lock, flags);
	ret = ath9k_hw_setpower(sc->sc_ah, mode);
	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
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	return ret;
}

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void ath9k_ps_wakeup(struct ath_softc *sc)
{
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	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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	unsigned long flags;
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	enum ath9k_power_mode power_mode;
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	spin_lock_irqsave(&sc->sc_pm_lock, flags);
	if (++sc->ps_usecount != 1)
		goto unlock;

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	power_mode = sc->sc_ah->power_mode;
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	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
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	/*
	 * While the hardware is asleep, the cycle counters contain no
	 * useful data. Better clear them now so that they don't mess up
	 * survey data results.
	 */
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	if (power_mode != ATH9K_PM_AWAKE) {
		spin_lock(&common->cc_lock);
		ath_hw_cycle_counters_update(common);
		memset(&common->cc_survey, 0, sizeof(common->cc_survey));
		spin_unlock(&common->cc_lock);
	}
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 unlock:
	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
}

void ath9k_ps_restore(struct ath_softc *sc)
{
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	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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	unsigned long flags;

	spin_lock_irqsave(&sc->sc_pm_lock, flags);
	if (--sc->ps_usecount != 0)
		goto unlock;

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	spin_lock(&common->cc_lock);
	ath_hw_cycle_counters_update(common);
	spin_unlock(&common->cc_lock);

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	if (sc->ps_idle)
		ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
	else if (sc->ps_enabled &&
		 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
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			      PS_WAIT_FOR_CAB |
			      PS_WAIT_FOR_PSPOLL_DATA |
			      PS_WAIT_FOR_TX_ACK)))
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		ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
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 unlock:
	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
}

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static void ath_start_ani(struct ath_common *common)
{
	struct ath_hw *ah = common->ah;
	unsigned long timestamp = jiffies_to_msecs(jiffies);
	struct ath_softc *sc = (struct ath_softc *) common->priv;

	if (!(sc->sc_flags & SC_OP_ANI_RUN))
		return;

	if (sc->sc_flags & SC_OP_OFFCHANNEL)
		return;

	common->ani.longcal_timer = timestamp;
	common->ani.shortcal_timer = timestamp;
	common->ani.checkani_timer = timestamp;

	mod_timer(&common->ani.timer,
		  jiffies +
			msecs_to_jiffies((u32)ah->config.ani_poll_interval));
}

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static void ath_update_survey_nf(struct ath_softc *sc, int channel)
{
	struct ath_hw *ah = sc->sc_ah;
	struct ath9k_channel *chan = &ah->channels[channel];
	struct survey_info *survey = &sc->survey[channel];

	if (chan->noisefloor) {
		survey->filled |= SURVEY_INFO_NOISE_DBM;
		survey->noise = chan->noisefloor;
	}
}

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/*
 * Updates the survey statistics and returns the busy time since last
 * update in %, if the measurement duration was long enough for the
 * result to be useful, -1 otherwise.
 */
static int ath_update_survey_stats(struct ath_softc *sc)
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{
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	int pos = ah->curchan - &ah->channels[0];
	struct survey_info *survey = &sc->survey[pos];
	struct ath_cycle_counters *cc = &common->cc_survey;
	unsigned int div = common->clockrate * 1000;
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	int ret = 0;
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	if (!ah->curchan)
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		return -1;
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	if (ah->power_mode == ATH9K_PM_AWAKE)
		ath_hw_cycle_counters_update(common);
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	if (cc->cycles > 0) {
		survey->filled |= SURVEY_INFO_CHANNEL_TIME |
			SURVEY_INFO_CHANNEL_TIME_BUSY |
			SURVEY_INFO_CHANNEL_TIME_RX |
			SURVEY_INFO_CHANNEL_TIME_TX;
		survey->channel_time += cc->cycles / div;
		survey->channel_time_busy += cc->rx_busy / div;
		survey->channel_time_rx += cc->rx_frame / div;
		survey->channel_time_tx += cc->tx_frame / div;
	}
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	if (cc->cycles < div)
		return -1;

	if (cc->cycles > 0)
		ret = cc->rx_busy * 100 / cc->cycles;

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	memset(cc, 0, sizeof(*cc));

	ath_update_survey_nf(sc, pos);
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	return ret;
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}

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/*
 * Set/change channels.  If the channel is really being changed, it's done
 * by reseting the chip.  To accomplish this we must first cleanup any pending
 * DMA, then restart stuff.
*/
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int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
		    struct ath9k_channel *hchan)
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{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	struct ieee80211_conf *conf = &common->hw->conf;
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	bool fastcc = true, stopped;
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	struct ieee80211_channel *channel = hw->conf.channel;
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	struct ath9k_hw_cal_data *caldata = NULL;
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	int r;
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	if (sc->sc_flags & SC_OP_INVALID)
		return -EIO;

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	sc->hw_busy_count = 0;

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	del_timer_sync(&common->ani.timer);
	cancel_work_sync(&sc->paprd_work);
	cancel_work_sync(&sc->hw_check_work);
	cancel_delayed_work_sync(&sc->tx_complete_work);
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	cancel_delayed_work_sync(&sc->hw_pll_work);
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	ath9k_ps_wakeup(sc);

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	spin_lock_bh(&sc->sc_pcu_lock);

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	/*
	 * This is only performed if the channel settings have
	 * actually changed.
	 *
	 * To switch channels clear any pending DMA operations;
	 * wait long enough for the RX fifo to drain, reset the
	 * hardware at the new frequency, and then re-enable
	 * the relevant bits of the h/w.
	 */
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	ath9k_hw_disable_interrupts(ah);
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	stopped = ath_drain_all_txq(sc, false);
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	if (!ath_stoprecv(sc))
		stopped = false;
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	if (!ath9k_hw_check_alive(ah))
		stopped = false;

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	/* XXX: do not flush receive queue here. We don't want
	 * to flush data frames already in queue because of
	 * changing channel. */
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	if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
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		fastcc = false;

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	if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
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		caldata = &sc->caldata;
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	ath_dbg(common, ATH_DBG_CONFIG,
		"(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
		sc->sc_ah->curchan->channel,
		channel->center_freq, conf_is_ht40(conf),
		fastcc);
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	r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
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	if (r) {
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		ath_err(common,
			"Unable to reset channel (%u MHz), reset status %d\n",
			channel->center_freq, r);
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		goto ps_restore;
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	}
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	if (ath_startrecv(sc) != 0) {
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		ath_err(common, "Unable to restart recv logic\n");
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		r = -EIO;
		goto ps_restore;
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	}

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	ath9k_cmn_update_txpow(ah, sc->curtxpow,
			       sc->config.txpowlimit, &sc->curtxpow);
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	ath9k_hw_set_interrupts(ah, ah->imask);
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	if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
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		if (sc->sc_flags & SC_OP_BEACONS)
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			ath_set_beacon(sc);
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		ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
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		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
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		ath_start_ani(common);
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	}

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 ps_restore:
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	ieee80211_wake_queues(hw);

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	spin_unlock_bh(&sc->sc_pcu_lock);

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	ath9k_ps_restore(sc);
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	return r;
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}

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static void ath_paprd_activate(struct ath_softc *sc)
{
	struct ath_hw *ah = sc->sc_ah;
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	struct ath9k_hw_cal_data *caldata = ah->caldata;
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	struct ath_common *common = ath9k_hw_common(ah);
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	int chain;

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	if (!caldata || !caldata->paprd_done)
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		return;

	ath9k_ps_wakeup(sc);
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	ar9003_paprd_enable(ah, false);
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	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
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		if (!(common->tx_chainmask & BIT(chain)))
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			continue;

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		ar9003_paprd_populate_single_table(ah, caldata, chain);
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	}

	ar9003_paprd_enable(ah, true);
	ath9k_ps_restore(sc);
}

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static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
{
	struct ieee80211_hw *hw = sc->hw;
	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
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	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
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	struct ath_tx_control txctl;
	int time_left;

	memset(&txctl, 0, sizeof(txctl));
	txctl.txq = sc->tx.txq_map[WME_AC_BE];

	memset(tx_info, 0, sizeof(*tx_info));
	tx_info->band = hw->conf.channel->band;
	tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
	tx_info->control.rates[0].idx = 0;
	tx_info->control.rates[0].count = 1;
	tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
	tx_info->control.rates[1].idx = -1;

	init_completion(&sc->paprd_complete);
	txctl.paprd = BIT(chain);
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	if (ath_tx_start(hw, skb, &txctl) != 0) {
		ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
		dev_kfree_skb_any(skb);
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		return false;
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	}
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	time_left = wait_for_completion_timeout(&sc->paprd_complete,
			msecs_to_jiffies(ATH_PAPRD_TIMEOUT));

	if (!time_left)
		ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
			"Timeout waiting for paprd training on TX chain %d\n",
			chain);

	return !!time_left;
}

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void ath_paprd_calibrate(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
	struct ieee80211_hw *hw = sc->hw;
	struct ath_hw *ah = sc->sc_ah;
	struct ieee80211_hdr *hdr;
	struct sk_buff *skb = NULL;
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	struct ath9k_hw_cal_data *caldata = ah->caldata;
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	struct ath_common *common = ath9k_hw_common(ah);
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	int ftype;
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	int chain_ok = 0;
	int chain;
	int len = 1800;

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	if (!caldata)
		return;

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	if (ar9003_paprd_init_table(ah) < 0)
		return;

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	skb = alloc_skb(len, GFP_KERNEL);
	if (!skb)
		return;

	skb_put(skb, len);
	memset(skb->data, 0, len);
	hdr = (struct ieee80211_hdr *)skb->data;
	ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
	hdr->frame_control = cpu_to_le16(ftype);
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	hdr->duration_id = cpu_to_le16(10);
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	memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
	memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
	memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);

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	ath9k_ps_wakeup(sc);
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	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
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		if (!(common->tx_chainmask & BIT(chain)))
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			continue;

		chain_ok = 0;

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		ath_dbg(common, ATH_DBG_CALIBRATE,
			"Sending PAPRD frame for thermal measurement "
			"on chain %d\n", chain);
		if (!ath_paprd_send_frame(sc, skb, chain))
			goto fail_paprd;
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		ar9003_paprd_setup_gain_table(ah, chain);

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		ath_dbg(common, ATH_DBG_CALIBRATE,
			"Sending PAPRD training frame on chain %d\n", chain);
		if (!ath_paprd_send_frame(sc, skb, chain))
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			goto fail_paprd;
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		if (!ar9003_paprd_is_done(ah))
			break;

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		if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
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			break;

		chain_ok = 1;
	}
	kfree_skb(skb);

	if (chain_ok) {
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		caldata->paprd_done = true;
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		ath_paprd_activate(sc);
	}

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fail_paprd:
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	ath9k_ps_restore(sc);
}

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/*
 *  This routine performs the periodic noise floor calibration function
 *  that is used to adjust and optimize the chip performance.  This
 *  takes environmental changes (location, temperature) into account.
 *  When the task is complete, it reschedules itself depending on the
 *  appropriate interval that was calculated.
 */
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void ath_ani_calibrate(unsigned long data)
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{
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	struct ath_softc *sc = (struct ath_softc *)data;
	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	bool longcal = false;
	bool shortcal = false;
	bool aniflag = false;
	unsigned int timestamp = jiffies_to_msecs(jiffies);
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	u32 cal_interval, short_cal_interval, long_cal_interval;
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	unsigned long flags;
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	if (ah->caldata && ah->caldata->nfcal_interference)
		long_cal_interval = ATH_LONG_CALINTERVAL_INT;
	else
		long_cal_interval = ATH_LONG_CALINTERVAL;
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	short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
		ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
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	/* Only calibrate if awake */
	if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
		goto set_timer;

	ath9k_ps_wakeup(sc);

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	/* Long calibration runs independently of short calibration. */
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	if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
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		longcal = true;
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		ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
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		common->ani.longcal_timer = timestamp;
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	}

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	/* Short calibration applies only while caldone is false */
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	if (!common->ani.caldone) {
		if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
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			shortcal = true;
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			ath_dbg(common, ATH_DBG_ANI,
				"shortcal @%lu\n", jiffies);
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			common->ani.shortcal_timer = timestamp;
			common->ani.resetcal_timer = timestamp;
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		}
	} else {
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		if ((timestamp - common->ani.resetcal_timer) >=
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		    ATH_RESTART_CALINTERVAL) {
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			common->ani.caldone = ath9k_hw_reset_calvalid(ah);
			if (common->ani.caldone)
				common->ani.resetcal_timer = timestamp;
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		}
	}

	/* Verify whether we must check ANI */
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	if ((timestamp - common->ani.checkani_timer) >=
	     ah->config.ani_poll_interval) {
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		aniflag = true;
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		common->ani.checkani_timer = timestamp;
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	}

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	/* Call ANI routine if necessary */
	if (aniflag) {
		spin_lock_irqsave(&common->cc_lock, flags);
		ath9k_hw_ani_monitor(ah, ah->curchan);
		ath_update_survey_stats(sc);
		spin_unlock_irqrestore(&common->cc_lock, flags);
	}
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	/* Perform calibration if necessary */
	if (longcal || shortcal) {
		common->ani.caldone =
			ath9k_hw_calibrate(ah, ah->curchan,
						common->rx_chainmask, longcal);
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	}

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	ath9k_ps_restore(sc);

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set_timer:
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	/*
	* Set timer interval based on previous results.
	* The interval must be the shortest necessary to satisfy ANI,
	* short calibration and long calibration.
	*/
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	cal_interval = ATH_LONG_CALINTERVAL;
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	if (sc->sc_ah->config.enable_ani)
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		cal_interval = min(cal_interval,
				   (u32)ah->config.ani_poll_interval);
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	if (!common->ani.caldone)
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		cal_interval = min(cal_interval, (u32)short_cal_interval);
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	mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
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	if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
		if (!ah->caldata->paprd_done)
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			ieee80211_queue_work(sc->hw, &sc->paprd_work);
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		else if (!ah->paprd_table_write_done)
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			ath_paprd_activate(sc);
	}
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}

static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
{
	struct ath_node *an;
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	struct ath_hw *ah = sc->sc_ah;
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	an = (struct ath_node *)sta->drv_priv;

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#ifdef CONFIG_ATH9K_DEBUGFS
	spin_lock(&sc->nodes_lock);
	list_add(&an->list, &sc->nodes);
	spin_unlock(&sc->nodes_lock);
	an->sta = sta;
#endif
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	if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
		sc->sc_flags |= SC_OP_ENABLE_APM;

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	if (sc->sc_flags & SC_OP_TXAGGR) {
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		ath_tx_node_init(sc, an);
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		an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
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				     sta->ht_cap.ampdu_factor);
		an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
	}
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}

static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
{
	struct ath_node *an = (struct ath_node *)sta->drv_priv;

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#ifdef CONFIG_ATH9K_DEBUGFS
	spin_lock(&sc->nodes_lock);
	list_del(&an->list);
	spin_unlock(&sc->nodes_lock);
	an->sta = NULL;
#endif

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	if (sc->sc_flags & SC_OP_TXAGGR)
		ath_tx_node_cleanup(sc, an);
}

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void ath_hw_check(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
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	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
	unsigned long flags;
	int busy;
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	ath9k_ps_wakeup(sc);
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	if (ath9k_hw_check_alive(sc->sc_ah))
		goto out;
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	spin_lock_irqsave(&common->cc_lock, flags);
	busy = ath_update_survey_stats(sc);
	spin_unlock_irqrestore(&common->cc_lock, flags);
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	ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
		"busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
	if (busy >= 99) {
		if (++sc->hw_busy_count >= 3)
			ath_reset(sc, true);
	} else if (busy >= 0)
		sc->hw_busy_count = 0;
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out:
	ath9k_ps_restore(sc);
}

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static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
{
	static int count;
	struct ath_common *common = ath9k_hw_common(sc->sc_ah);

	if (pll_sqsum >= 0x40000) {
		count++;
		if (count == 3) {
			/* Rx is hung for more than 500ms. Reset it */
			ath_dbg(common, ATH_DBG_RESET,
				"Possible RX hang, resetting");
			ath_reset(sc, true);
			count = 0;
		}
	} else
		count = 0;
}

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void ath_hw_pll_work(struct work_struct *work)
{
	struct ath_softc *sc = container_of(work, struct ath_softc,
					    hw_pll_work.work);
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	u32 pll_sqsum;
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	if (AR_SREV_9485(sc->sc_ah)) {
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		ath9k_ps_wakeup(sc);
		pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
		ath9k_ps_restore(sc);

		ath_hw_pll_rx_hang_check(sc, pll_sqsum);
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		ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
	}
}


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void ath9k_tasklet(unsigned long data)
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{
	struct ath_softc *sc = (struct ath_softc *)data;
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
662

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	u32 status = sc->intrstatus;
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	u32 rxmask;
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	if ((status & ATH9K_INT_FATAL) ||
	    (status & ATH9K_INT_BB_WATCHDOG)) {
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		ath_reset(sc, true);
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		return;
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	}
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	ath9k_ps_wakeup(sc);
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	spin_lock(&sc->sc_pcu_lock);
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	/*
	 * Only run the baseband hang check if beacons stop working in AP or
	 * IBSS mode, because it has a high false positive rate. For station
	 * mode it should not be necessary, since the upper layers will detect
	 * this through a beacon miss automatically and the following channel
	 * change will trigger a hardware reset anyway
	 */
	if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
	    !ath9k_hw_check_alive(ah))
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		ieee80211_queue_work(sc->hw, &sc->hw_check_work);

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	if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
		/*
		 * TSF sync does not look correct; remain awake to sync with
		 * the next Beacon.
		 */
		ath_dbg(common, ATH_DBG_PS,
			"TSFOOR - Sync with next Beacon\n");
		sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
				PS_TSFOOR_SYNC;
	}

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	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
		rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
			  ATH9K_INT_RXORN);
	else
		rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);

	if (status & rxmask) {
		/* Check for high priority Rx first */
		if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
		    (status & ATH9K_INT_RXHP))
			ath_rx_tasklet(sc, 0, true);

		ath_rx_tasklet(sc, 0, false);
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	}

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	if (status & ATH9K_INT_TX) {
		if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
			ath_tx_edma_tasklet(sc);
		else
			ath_tx_tasklet(sc);
	}
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	if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
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		if (status & ATH9K_INT_GENTIMER)
			ath_gen_timer_isr(sc->sc_ah);

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	/* re-enable hardware interrupt */
724
	ath9k_hw_enable_interrupts(ah);
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	spin_unlock(&sc->sc_pcu_lock);
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	ath9k_ps_restore(sc);
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}

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irqreturn_t ath_isr(int irq, void *dev)
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{
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#define SCHED_INTR (				\
		ATH9K_INT_FATAL |		\
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		ATH9K_INT_BB_WATCHDOG |		\
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		ATH9K_INT_RXORN |		\
		ATH9K_INT_RXEOL |		\
		ATH9K_INT_RX |			\
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		ATH9K_INT_RXLP |		\
		ATH9K_INT_RXHP |		\
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		ATH9K_INT_TX |			\
		ATH9K_INT_BMISS |		\
		ATH9K_INT_CST |			\
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		ATH9K_INT_TSFOOR |		\
		ATH9K_INT_GENTIMER)
745

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	struct ath_softc *sc = dev;
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	enum ath9k_int status;
	bool sched = false;

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	/*
	 * The hardware is not ready/present, don't
	 * touch anything. Note this can happen early
	 * on if the IRQ is shared.
	 */
	if (sc->sc_flags & SC_OP_INVALID)
		return IRQ_NONE;
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	/* shared irq, not for us */

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	if (!ath9k_hw_intrpend(ah))
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		return IRQ_NONE;

	/*
	 * Figure out the reason(s) for the interrupt.  Note
	 * that the hal returns a pseudo-ISR that may include
	 * bits we haven't explicitly enabled so we mask the
	 * value to insure we only process bits we requested.
	 */
	ath9k_hw_getisr(ah, &status);	/* NB: clears ISR too */
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	status &= ah->imask;	/* discard unasked-for bits */
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	/*
	 * If there are no status bits set, then this interrupt was not
	 * for me (should have been caught above).
	 */
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	if (!status)
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		return IRQ_NONE;
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	/* Cache the status */
	sc->intrstatus = status;

	if (status & SCHED_INTR)
		sched = true;

	/*
	 * If a FATAL or RXORN interrupt is received, we have to reset the
	 * chip immediately.
	 */
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	if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
	    !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
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		goto chip_reset;

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	if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
	    (status & ATH9K_INT_BB_WATCHDOG)) {
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		spin_lock(&common->cc_lock);
		ath_hw_cycle_counters_update(common);
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		ar9003_hw_bb_watchdog_dbg_info(ah);
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		spin_unlock(&common->cc_lock);

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		goto chip_reset;
	}

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	if (status & ATH9K_INT_SWBA)
		tasklet_schedule(&sc->bcon_tasklet);

	if (status & ATH9K_INT_TXURN)
		ath9k_hw_updatetxtriglevel(ah, true);

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	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
		if (status & ATH9K_INT_RXEOL) {
			ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
			ath9k_hw_set_interrupts(ah, ah->imask);
		}
	}

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	if (status & ATH9K_INT_MIB) {
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		/*
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		 * Disable interrupts until we service the MIB
		 * interrupt; otherwise it will continue to
		 * fire.
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		 */
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		ath9k_hw_disable_interrupts(ah);
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		/*
		 * Let the hal handle the event. We assume
		 * it will clear whatever condition caused
		 * the interrupt.
		 */
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		spin_lock(&common->cc_lock);
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		ath9k_hw_proc_mib_event(ah);
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		spin_unlock(&common->cc_lock);
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		ath9k_hw_enable_interrupts(ah);
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	}
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	if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
		if (status & ATH9K_INT_TIM_TIMER) {
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			if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
				goto chip_reset;
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			/* Clear RxAbort bit so that we can
			 * receive frames */
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			ath9k_setpower(sc, ATH9K_PM_AWAKE);
845
			ath9k_hw_setrxabort(sc->sc_ah, 0);
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			sc->ps_flags |= PS_WAIT_FOR_BEACON;
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		}
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chip_reset:
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	ath_debug_stat_interrupt(sc, status);

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	if (sched) {
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		/* turn off every interrupt */
		ath9k_hw_disable_interrupts(ah);
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		tasklet_schedule(&sc->intr_tq);
	}

	return IRQ_HANDLED;
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#undef SCHED_INTR
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}

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void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
865
{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	struct ieee80211_channel *channel = hw->conf.channel;
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	int r;
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	ath9k_ps_wakeup(sc);
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	spin_lock_bh(&sc->sc_pcu_lock);

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	ath9k_hw_configpcipowersave(ah, 0, 0);
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	if (!ah->curchan)
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		ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
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	r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
880
	if (r) {
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		ath_err(common,
			"Unable to reset channel (%u MHz), reset status %d\n",
			channel->center_freq, r);
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	}

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	ath9k_cmn_update_txpow(ah, sc->curtxpow,
			       sc->config.txpowlimit, &sc->curtxpow);
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	if (ath_startrecv(sc) != 0) {
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		ath_err(common, "Unable to restart recv logic\n");
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		goto out;
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	}
	if (sc->sc_flags & SC_OP_BEACONS)
893
		ath_set_beacon(sc);	/* restart beacons */
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	/* Re-Enable  interrupts */
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	ath9k_hw_set_interrupts(ah, ah->imask);
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	/* Enable LED */
899
	ath9k_hw_cfg_output(ah, ah->led_pin,
900
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
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	ath9k_hw_set_gpio(ah, ah->led_pin, 0);
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	ieee80211_wake_queues(hw);
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	ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);

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out:
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	spin_unlock_bh(&sc->sc_pcu_lock);

909
	ath9k_ps_restore(sc);
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}

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void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
913
{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ieee80211_channel *channel = hw->conf.channel;
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	int r;
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918
	ath9k_ps_wakeup(sc);
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	cancel_delayed_work_sync(&sc->hw_pll_work);

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	spin_lock_bh(&sc->sc_pcu_lock);

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	ieee80211_stop_queues(hw);
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	/*
	 * Keep the LED on when the radio is disabled
	 * during idle unassociated state.
	 */
	if (!sc->ps_idle) {
		ath9k_hw_set_gpio(ah, ah->led_pin, 1);
		ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
	}
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	/* Disable interrupts */
935
	ath9k_hw_disable_interrupts(ah);
936

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	ath_drain_all_txq(sc, false);	/* clear pending tx frames */
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	ath_stoprecv(sc);		/* turn off frame recv */
	ath_flushrecv(sc);		/* flush recv queue */

942
	if (!ah->curchan)
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		ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
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945
	r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
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	if (r) {
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		ath_err(ath9k_hw_common(sc->sc_ah),
			"Unable to reset channel (%u MHz), reset status %d\n",
			channel->center_freq, r);
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	}

	ath9k_hw_phy_disable(ah);
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	ath9k_hw_configpcipowersave(ah, 1, 1);
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	spin_unlock_bh(&sc->sc_pcu_lock);
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	ath9k_ps_restore(sc);
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}

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int ath_reset(struct ath_softc *sc, bool retry_tx)
{
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	struct ath_hw *ah = sc->sc_ah;
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	struct ath_common *common = ath9k_hw_common(ah);
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	struct ieee80211_hw *hw = sc->hw;
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	int r;
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	sc->hw_busy_count = 0;

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	/* Stop ANI */
	del_timer_sync(&common->ani.timer);

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	ath9k_ps_wakeup(sc);
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	spin_lock_bh(&sc->sc_pcu_lock);

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	ieee80211_stop_queues(hw);

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	ath9k_hw_disable_interrupts(ah);
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	ath_drain_all_txq(sc, retry_tx);
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	ath_stoprecv(sc);
	ath_flushrecv(sc);

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	r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
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	if (r)
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		ath_err(common,
			"Unable to reset hardware; reset status %d\n", r);
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	if (ath_startrecv(sc) != 0)
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		ath_err(common, "Unable to start recv logic\n");
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	/*
	 * We may be doing a reset in response to a request
	 * that changes the channel so update any state that
	 * might change as a result.
	 */
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	ath9k_cmn_update_txpow(ah, sc->curtxpow,
			       sc->config.txpowlimit, &sc->curtxpow);
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	if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
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		ath_set_beacon(sc);	/* restart beacons */
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	ath9k_hw_set_interrupts(ah, ah->imask);
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	if (retry_tx) {
		int i;
		for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
			if (ATH_TXQ_SETUP(sc, i)) {
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				spin_lock_bh(&sc->tx.txq[i].axq_lock);
				ath_txq_schedule(sc, &sc->tx.txq[i]);
				spin_unlock_bh(&sc->tx.txq[i].axq_lock);
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			}
		}
	}

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	ieee80211_wake_queues(hw);
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	spin_unlock_bh(&sc->sc_pcu_lock);
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