i915_dma.c 36.4 KB
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/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include "drmP.h"
#include "drm.h"
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#include "drm_crtc_helper.h"
#include "intel_drv.h"
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#include "i915_drm.h"
#include "i915_drv.h"

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#define I915_DRV	"i915_drv"

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/* Really want an OS-independent resettable timer.  Would like to have
 * this loop run for (eg) 3 sec, but have the timer reset every time
 * the head pointer changes, so that EBUSY only happens if the ring
 * actually stalls for (eg) 3 seconds.
 */
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int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
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	u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
	u32 last_acthd = I915_READ(acthd_reg);
	u32 acthd;
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	u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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	int i;

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	for (i = 0; i < 100000; i++) {
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		ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
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		acthd = I915_READ(acthd_reg);
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		ring->space = ring->head - (ring->tail + 8);
		if (ring->space < 0)
			ring->space += ring->Size;
		if (ring->space >= n)
			return 0;

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		if (dev->primary->master) {
			struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
			if (master_priv->sarea_priv)
				master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
		}

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		if (ring->head != last_head)
			i = 0;
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		if (acthd != last_acthd)
			i = 0;
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		last_head = ring->head;
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		last_acthd = acthd;
		msleep_interruptible(10);

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	}

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	return -EBUSY;
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}

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/**
 * Sets up the hardware status page for devices that need a physical address
 * in the register.
 */
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static int i915_init_phys_hws(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	/* Program Hardware Status Page */
	dev_priv->status_page_dmah =
		drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);

	if (!dev_priv->status_page_dmah) {
		DRM_ERROR("Can not allocate hardware status page\n");
		return -ENOMEM;
	}
	dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
	dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;

	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);

	I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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	DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
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	return 0;
}

/**
 * Frees the hardware status page, whether it's a physical address or a virtual
 * address set up by the X Server.
 */
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static void i915_free_hws(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	if (dev_priv->status_page_dmah) {
		drm_pci_free(dev, dev_priv->status_page_dmah);
		dev_priv->status_page_dmah = NULL;
	}

	if (dev_priv->status_gfx_addr) {
		dev_priv->status_gfx_addr = 0;
		drm_core_ioremapfree(&dev_priv->hws_map, dev);
	}

	/* Need to rewrite hardware status page */
	I915_WRITE(HWS_PGA, 0x1ffff000);
}

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void i915_kernel_lost_context(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv;
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	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);

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	/*
	 * We should never lose context on the ring with modesetting
	 * as we don't expose it to userspace
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;

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	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
	ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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	ring->space = ring->head - (ring->tail + 8);
	if (ring->space < 0)
		ring->space += ring->Size;

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	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (ring->head == ring->tail && master_priv->sarea_priv)
		master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
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}

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static int i915_dma_cleanup(struct drm_device * dev)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	/* Make sure interrupts are disabled here because the uninstall ioctl
	 * may not have been called from userspace and after dev_private
	 * is freed, it's too late.
	 */
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	if (dev->irq_enabled)
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		drm_irq_uninstall(dev);
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	if (dev_priv->ring.virtual_start) {
		drm_core_ioremapfree(&dev_priv->ring.map, dev);
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		dev_priv->ring.virtual_start = NULL;
		dev_priv->ring.map.handle = NULL;
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		dev_priv->ring.map.size = 0;
	}
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	/* Clear the HWS virtual address at teardown */
	if (I915_NEED_GFX_HWS(dev))
		i915_free_hws(dev);
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	return 0;
}

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static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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	master_priv->sarea = drm_getsarea(dev);
	if (master_priv->sarea) {
		master_priv->sarea_priv = (drm_i915_sarea_t *)
			((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
	} else {
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		DRM_DEBUG_DRIVER(I915_DRV,
				"sarea not found assuming DRI2 userspace\n");
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	}

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	if (init->ring_size != 0) {
		if (dev_priv->ring.ring_obj != NULL) {
			i915_dma_cleanup(dev);
			DRM_ERROR("Client tried to initialize ringbuffer in "
				  "GEM mode\n");
			return -EINVAL;
		}
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		dev_priv->ring.Size = init->ring_size;
		dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
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		dev_priv->ring.map.offset = init->ring_start;
		dev_priv->ring.map.size = init->ring_size;
		dev_priv->ring.map.type = 0;
		dev_priv->ring.map.flags = 0;
		dev_priv->ring.map.mtrr = 0;
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		drm_core_ioremap_wc(&dev_priv->ring.map, dev);
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		if (dev_priv->ring.map.handle == NULL) {
			i915_dma_cleanup(dev);
			DRM_ERROR("can not ioremap virtual address for"
				  " ring buffer\n");
			return -ENOMEM;
		}
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	}

	dev_priv->ring.virtual_start = dev_priv->ring.map.handle;

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	dev_priv->cpp = init->cpp;
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	dev_priv->back_offset = init->back_offset;
	dev_priv->front_offset = init->front_offset;
	dev_priv->current_page = 0;
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	if (master_priv->sarea_priv)
		master_priv->sarea_priv->pf_current_page = 0;
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	/* Allow hardware batchbuffers unless told otherwise.
	 */
	dev_priv->allow_batchbuffer = 1;

	return 0;
}

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static int i915_dma_resume(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

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	DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
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	if (dev_priv->ring.map.handle == NULL) {
		DRM_ERROR("can not ioremap virtual address for"
			  " ring buffer\n");
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		return -ENOMEM;
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	}

	/* Program Hardware Status Page */
	if (!dev_priv->hw_status_page) {
		DRM_ERROR("Can not find hardware status page\n");
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		return -EINVAL;
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	}
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	DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n",
				dev_priv->hw_status_page);
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	if (dev_priv->status_gfx_addr != 0)
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		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
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	else
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		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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	DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
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	return 0;
}

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static int i915_dma_init(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
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{
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	drm_i915_init_t *init = data;
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	int retcode = 0;

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	switch (init->func) {
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	case I915_INIT_DMA:
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		retcode = i915_initialize(dev, init);
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		break;
	case I915_CLEANUP_DMA:
		retcode = i915_dma_cleanup(dev);
		break;
	case I915_RESUME_DMA:
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		retcode = i915_dma_resume(dev);
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		break;
	default:
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		retcode = -EINVAL;
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		break;
	}

	return retcode;
}

/* Implement basically the same security restrictions as hardware does
 * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 *
 * Most of the calculations below involve calculating the size of a
 * particular instruction.  It's important to get the size right as
 * that tells us where the next instruction to check is.  Any illegal
 * instruction detected will be given a size of zero, which is a
 * signal to abort the rest of the buffer.
 */
static int do_validate_cmd(int cmd)
{
	switch (((cmd >> 29) & 0x7)) {
	case 0x0:
		switch ((cmd >> 23) & 0x3f) {
		case 0x0:
			return 1;	/* MI_NOOP */
		case 0x4:
			return 1;	/* MI_FLUSH */
		default:
			return 0;	/* disallow everything else */
		}
		break;
	case 0x1:
		return 0;	/* reserved */
	case 0x2:
		return (cmd & 0xff) + 2;	/* 2d commands */
	case 0x3:
		if (((cmd >> 24) & 0x1f) <= 0x18)
			return 1;

		switch ((cmd >> 24) & 0x1f) {
		case 0x1c:
			return 1;
		case 0x1d:
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			switch ((cmd >> 16) & 0xff) {
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			case 0x3:
				return (cmd & 0x1f) + 2;
			case 0x4:
				return (cmd & 0xf) + 2;
			default:
				return (cmd & 0xffff) + 2;
			}
		case 0x1e:
			if (cmd & (1 << 23))
				return (cmd & 0xffff) + 1;
			else
				return 1;
		case 0x1f:
			if ((cmd & (1 << 23)) == 0)	/* inline vertices */
				return (cmd & 0x1ffff) + 2;
			else if (cmd & (1 << 17))	/* indirect random */
				if ((cmd & 0xffff) == 0)
					return 0;	/* unknown length, too hard */
				else
					return (((cmd & 0xffff) + 1) / 2) + 1;
			else
				return 2;	/* indirect sequential */
		default:
			return 0;
		}
	default:
		return 0;
	}

	return 0;
}

static int validate_cmd(int cmd)
{
	int ret = do_validate_cmd(cmd);

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/*	printk("validate_cmd( %x ): %d\n", cmd, ret); */
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	return ret;
}

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static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;
	RING_LOCALS;

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	if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
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		return -EINVAL;
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	BEGIN_LP_RING((dwords+1)&~1);
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	for (i = 0; i < dwords;) {
		int cmd, sz;

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		cmd = buffer[i];
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		if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
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			return -EINVAL;
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		OUT_RING(cmd);

		while (++i, --sz) {
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			OUT_RING(buffer[i]);
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		}
	}

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	if (dwords & 1)
		OUT_RING(0);

	ADVANCE_LP_RING();

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	return 0;
}

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int
i915_emit_box(struct drm_device *dev,
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	      struct drm_clip_rect *boxes,
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	      int i, int DR1, int DR4)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_clip_rect box = boxes[i];
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	RING_LOCALS;

	if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
		DRM_ERROR("Bad box %d,%d..%d,%d\n",
			  box.x1, box.y1, box.x2, box.y2);
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		return -EINVAL;
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	}

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	if (IS_I965G(dev)) {
		BEGIN_LP_RING(4);
		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
		OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
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		OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
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		OUT_RING(DR4);
		ADVANCE_LP_RING();
	} else {
		BEGIN_LP_RING(6);
		OUT_RING(GFX_OP_DRAWRECT_INFO);
		OUT_RING(DR1);
		OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
		OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
		OUT_RING(DR4);
		OUT_RING(0);
		ADVANCE_LP_RING();
	}
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	return 0;
}

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/* XXX: Emitting the counter should really be moved to part of the IRQ
 * emit. For now, do it in both places:
 */

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static void i915_emit_breadcrumb(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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	RING_LOCALS;

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	dev_priv->counter++;
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	if (dev_priv->counter > 0x7FFFFFFFUL)
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		dev_priv->counter = 0;
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	if (master_priv->sarea_priv)
		master_priv->sarea_priv->last_enqueue = dev_priv->counter;
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	BEGIN_LP_RING(4);
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	OUT_RING(MI_STORE_DWORD_INDEX);
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	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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	OUT_RING(dev_priv->counter);
	OUT_RING(0);
	ADVANCE_LP_RING();
}

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static int i915_dispatch_cmdbuffer(struct drm_device * dev,
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				   drm_i915_cmdbuffer_t *cmd,
				   struct drm_clip_rect *cliprects,
				   void *cmdbuf)
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{
	int nbox = cmd->num_cliprects;
	int i = 0, count, ret;

	if (cmd->sz & 0x3) {
		DRM_ERROR("alignment");
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		return -EINVAL;
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	}

	i915_kernel_lost_context(dev);

	count = nbox ? nbox : 1;

	for (i = 0; i < count; i++) {
		if (i < nbox) {
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			ret = i915_emit_box(dev, cliprects, i,
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					    cmd->DR1, cmd->DR4);
			if (ret)
				return ret;
		}

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		ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
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		if (ret)
			return ret;
	}

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	i915_emit_breadcrumb(dev);
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	return 0;
}

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static int i915_dispatch_batchbuffer(struct drm_device * dev,
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				     drm_i915_batchbuffer_t * batch,
				     struct drm_clip_rect *cliprects)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int nbox = batch->num_cliprects;
	int i = 0, count;
	RING_LOCALS;

	if ((batch->start | batch->used) & 0x7) {
		DRM_ERROR("alignment");
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		return -EINVAL;
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	}

	i915_kernel_lost_context(dev);

	count = nbox ? nbox : 1;

	for (i = 0; i < count; i++) {
		if (i < nbox) {
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			int ret = i915_emit_box(dev, cliprects, i,
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						batch->DR1, batch->DR4);
			if (ret)
				return ret;
		}

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		if (!IS_I830(dev) && !IS_845G(dev)) {
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			BEGIN_LP_RING(2);
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			if (IS_I965G(dev)) {
				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
				OUT_RING(batch->start);
			} else {
				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
				OUT_RING(batch->start | MI_BATCH_NON_SECURE);
			}
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			ADVANCE_LP_RING();
		} else {
			BEGIN_LP_RING(4);
			OUT_RING(MI_BATCH_BUFFER);
			OUT_RING(batch->start | MI_BATCH_NON_SECURE);
			OUT_RING(batch->start + batch->used - 4);
			OUT_RING(0);
			ADVANCE_LP_RING();
		}
	}

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	i915_emit_breadcrumb(dev);
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	return 0;
}

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static int i915_dispatch_flip(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv =
		dev->primary->master->driver_priv;
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	RING_LOCALS;

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	if (!master_priv->sarea_priv)
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		return -EINVAL;

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	DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n",
			  __func__,
			 dev_priv->current_page,
			 master_priv->sarea_priv->pf_current_page);
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	i915_kernel_lost_context(dev);

	BEGIN_LP_RING(2);
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	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
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	OUT_RING(0);
	ADVANCE_LP_RING();
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	BEGIN_LP_RING(6);
	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
	OUT_RING(0);
	if (dev_priv->current_page == 0) {
		OUT_RING(dev_priv->back_offset);
		dev_priv->current_page = 1;
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	} else {
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		OUT_RING(dev_priv->front_offset);
		dev_priv->current_page = 0;
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	}
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	OUT_RING(0);
	ADVANCE_LP_RING();
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	BEGIN_LP_RING(2);
	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
	OUT_RING(0);
	ADVANCE_LP_RING();
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	master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
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	BEGIN_LP_RING(4);
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	OUT_RING(MI_STORE_DWORD_INDEX);
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	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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	OUT_RING(dev_priv->counter);
	OUT_RING(0);
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	ADVANCE_LP_RING();

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	master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
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	return 0;
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}

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static int i915_quiescent(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;

	i915_kernel_lost_context(dev);
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	return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
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}

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static int i915_flush_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
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{
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	int ret;

	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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	mutex_lock(&dev->struct_mutex);
	ret = i915_quiescent(dev);
	mutex_unlock(&dev->struct_mutex);

	return ret;
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}

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static int i915_batchbuffer(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
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	    master_priv->sarea_priv;
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	drm_i915_batchbuffer_t *batch = data;
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	int ret;
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	struct drm_clip_rect *cliprects = NULL;
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	if (!dev_priv->allow_batchbuffer) {
		DRM_ERROR("Batchbuffer ioctl disabled\n");
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		return -EINVAL;
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	}

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	DRM_DEBUG_DRIVER(I915_DRV,
			"i915 batchbuffer, start %x used %d cliprects %d\n",
			batch->start, batch->used, batch->num_cliprects);
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	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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	if (batch->num_cliprects < 0)
		return -EINVAL;

	if (batch->num_cliprects) {
		cliprects = drm_calloc(batch->num_cliprects,
				       sizeof(struct drm_clip_rect),
				       DRM_MEM_DRIVER);
		if (cliprects == NULL)
			return -ENOMEM;

		ret = copy_from_user(cliprects, batch->cliprects,
				     batch->num_cliprects *
				     sizeof(struct drm_clip_rect));
		if (ret != 0)
			goto fail_free;
	}
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	mutex_lock(&dev->struct_mutex);
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	ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
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	mutex_unlock(&dev->struct_mutex);
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	if (sarea_priv)
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		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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fail_free:
	drm_free(cliprects,
		 batch->num_cliprects * sizeof(struct drm_clip_rect),
		 DRM_MEM_DRIVER);

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	return ret;
}

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static int i915_cmdbuffer(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
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	    master_priv->sarea_priv;
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	drm_i915_cmdbuffer_t *cmdbuf = data;
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	struct drm_clip_rect *cliprects = NULL;
	void *batch_data;
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	int ret;

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	DRM_DEBUG_DRIVER(I915_DRV,
			"i915 cmdbuffer, buf %p sz %d cliprects %d\n",
			cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
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	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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	if (cmdbuf->num_cliprects < 0)
		return -EINVAL;

	batch_data = drm_alloc(cmdbuf->sz, DRM_MEM_DRIVER);
	if (batch_data == NULL)
		return -ENOMEM;

	ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
	if (ret != 0)
		goto fail_batch_free;

	if (cmdbuf->num_cliprects) {
		cliprects = drm_calloc(cmdbuf->num_cliprects,
				       sizeof(struct drm_clip_rect),
				       DRM_MEM_DRIVER);
		if (cliprects == NULL)
			goto fail_batch_free;

		ret = copy_from_user(cliprects, cmdbuf->cliprects,
				     cmdbuf->num_cliprects *
				     sizeof(struct drm_clip_rect));
		if (ret != 0)
			goto fail_clip_free;
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	}

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	mutex_lock(&dev->struct_mutex);
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	ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
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	mutex_unlock(&dev->struct_mutex);
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	if (ret) {
		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
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		goto fail_clip_free;
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	}

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	if (sarea_priv)
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		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
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fail_clip_free:
	drm_free(cliprects,
		 cmdbuf->num_cliprects * sizeof(struct drm_clip_rect),
		 DRM_MEM_DRIVER);
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fail_batch_free:
	drm_free(batch_data, cmdbuf->sz, DRM_MEM_DRIVER);
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	return ret;
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}

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static int i915_flip_bufs(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
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{
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	int ret;

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	DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
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	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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	mutex_lock(&dev->struct_mutex);
	ret = i915_dispatch_flip(dev);
	mutex_unlock(&dev->struct_mutex);

	return ret;
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}

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static int i915_getparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	drm_i915_getparam_t *param = data;
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	int value;

	if (!dev_priv) {
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		DRM_ERROR("called with no initialization\n");
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		return -EINVAL;
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	}

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	switch (param->param) {
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	case I915_PARAM_IRQ_ACTIVE:
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		value = dev->pdev->irq ? 1 : 0;
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		break;
	case I915_PARAM_ALLOW_BATCHBUFFER:
		value = dev_priv->allow_batchbuffer ? 1 : 0;
		break;
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	case I915_PARAM_LAST_DISPATCH:
		value = READ_BREADCRUMB(dev_priv);
		break;
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	case I915_PARAM_CHIPSET_ID:
		value = dev->pci_device;
		break;
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	case I915_PARAM_HAS_GEM:
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		value = dev_priv->has_gem;
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		break;
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	case I915_PARAM_NUM_FENCES_AVAIL:
		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
		break;
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	default:
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		DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n",
					param->param);
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		return -EINVAL;
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	}

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	if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
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		DRM_ERROR("DRM_COPY_TO_USER failed\n");
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		return -EFAULT;
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	}

	return 0;
}

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static int i915_setparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	drm_i915_setparam_t *param = data;
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	if (!dev_priv) {
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		DRM_ERROR("called with no initialization\n");
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		return -EINVAL;
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	}

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	switch (param->param) {
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	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
		break;
	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
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		dev_priv->tex_lru_log_granularity = param->value;
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		break;
	case I915_SETPARAM_ALLOW_BATCHBUFFER:
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		dev_priv->allow_batchbuffer = param->value;
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		break;
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	case I915_SETPARAM_NUM_USED_FENCES:
		if (param->value > dev_priv->num_fence_regs ||
		    param->value < 0)
			return -EINVAL;
		/* Userspace can use first N regs */
		dev_priv->fence_reg_start = param->value;
		break;
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	default:
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		DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n",
					param->param);
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		return -EINVAL;
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	}

	return 0;
}

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static int i915_set_status_page(struct drm_device *dev, void *data,
				struct drm_file *file_priv)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	drm_i915_hws_addr_t *hws = data;
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	if (!I915_NEED_GFX_HWS(dev))
		return -EINVAL;
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	if (!dev_priv) {
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		DRM_ERROR("called with no initialization\n");
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		return -EINVAL;
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	}

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	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		WARN(1, "tried to set status page when mode setting active\n");
		return 0;
	}

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	printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws->addr);

	dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
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	dev_priv->hws_map.offset = dev->agp->base + hws->addr;
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	dev_priv->hws_map.size = 4*1024;
	dev_priv->hws_map.type = 0;
	dev_priv->hws_map.flags = 0;
	dev_priv->hws_map.mtrr = 0;

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	drm_core_ioremap_wc(&dev_priv->hws_map, dev);
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	if (dev_priv->hws_map.handle == NULL) {
		i915_dma_cleanup(dev);
		dev_priv->status_gfx_addr = 0;
		DRM_ERROR("can not ioremap virtual address for"
				" G33 hw status page\n");
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		return -ENOMEM;
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	}
	dev_priv->hw_status_page = dev_priv->hws_map.handle;

	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
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	DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n",
				dev_priv->status_gfx_addr);
	DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n",
				dev_priv->hw_status_page);
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	return 0;
}

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/**
 * i915_probe_agp - get AGP bootup configuration
 * @pdev: PCI device
 * @aperture_size: returns AGP aperture configured size
 * @preallocated_size: returns size of BIOS preallocated AGP space
 *
 * Since Intel integrated graphics are UMA, the BIOS has to set aside
 * some RAM for the framebuffer at early boot.  This code figures out
 * how much was set aside so we can use it for our own purposes.
 */
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static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
			  unsigned long *preallocated_size)
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{
	struct pci_dev *bridge_dev;
	u16 tmp = 0;
	unsigned long overhead;
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	unsigned long stolen;
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	bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
	if (!bridge_dev) {
		DRM_ERROR("bridge device not found\n");
		return -1;
	}

	/* Get the fb aperture size and "stolen" memory amount. */
	pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
	pci_dev_put(bridge_dev);

	*aperture_size = 1024 * 1024;
	*preallocated_size = 1024 * 1024;

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	switch (dev->pdev->device) {
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	case PCI_DEVICE_ID_INTEL_82830_CGC:
	case PCI_DEVICE_ID_INTEL_82845G_IG:
	case PCI_DEVICE_ID_INTEL_82855GM_IG:
	case PCI_DEVICE_ID_INTEL_82865_IG:
		if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
			*aperture_size *= 64;
		else
			*aperture_size *= 128;
		break;
	default:
		/* 9xx supports large sizes, just look at the length */
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		*aperture_size = pci_resource_len(dev->pdev, 2);
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		break;
	}

	/*
	 * Some of the preallocated space is taken by the GTT
	 * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
	 */
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	if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
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		overhead = 4096;
	else
		overhead = (*aperture_size / 1024) + 4096;

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	switch (tmp & INTEL_GMCH_GMS_MASK) {
	case INTEL_855_GMCH_GMS_DISABLED:
		DRM_ERROR("video memory is disabled\n");
		return -1;
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	case INTEL_855_GMCH_GMS_STOLEN_1M:
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		stolen = 1 * 1024 * 1024;
		break;
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	case INTEL_855_GMCH_GMS_STOLEN_4M:
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		stolen = 4 * 1024 * 1024;
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		break;
	case INTEL_855_GMCH_GMS_STOLEN_8M:
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		stolen = 8 * 1024 * 1024;
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		break;
	case INTEL_855_GMCH_GMS_STOLEN_16M:
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		stolen = 16 * 1024 * 1024;
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		break;
	case INTEL_855_GMCH_GMS_STOLEN_32M:
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		stolen = 32 * 1024 * 1024;
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		break;
	case INTEL_915G_GMCH_GMS_STOLEN_48M:
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		stolen = 48 * 1024 * 1024;
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		break;
	case INTEL_915G_GMCH_GMS_STOLEN_64M:
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		stolen = 64 * 1024 * 1024;
		break;
	case INTEL_GMCH_GMS_STOLEN_128M:
		stolen = 128 * 1024 * 1024;
		break;
	case INTEL_GMCH_GMS_STOLEN_256M:
		stolen = 256 * 1024 * 1024;
		break;
	case INTEL_GMCH_GMS_STOLEN_96M:
		stolen = 96 * 1024 * 1024;
		break;
	case INTEL_GMCH_GMS_STOLEN_160M:
		stolen = 160 * 1024 * 1024;
		break;
	case INTEL_GMCH_GMS_STOLEN_224M:
		stolen = 224 * 1024 * 1024;
		break;
	case INTEL_GMCH_GMS_STOLEN_352M:
		stolen = 352 * 1024 * 1024;
981
982
983
		break;
	default:
		DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
984
			tmp & INTEL_GMCH_GMS_MASK);
985
986
		return -1;
	}
987
	*preallocated_size = stolen - overhead;
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001

	return 0;
}

static int i915_load_modeset_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long agp_size, prealloc_size;
	int fb_bar = IS_I9XX(dev) ? 2 : 0;
	int ret = 0;

	dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
		0xff000000;

1002
	if (IS_MOBILE(dev) || IS_I9XX(dev))
1003
1004
1005
1006
		dev_priv->cursor_needs_physical = true;
	else
		dev_priv->cursor_needs_physical = false;

1007
1008
1009
	if (IS_I965G(dev) || IS_G33(dev))
		dev_priv->cursor_needs_physical = false;

1010
1011
	ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
	if (ret)
1012
		goto out;
1013
1014
1015
1016

	/* Basic memrange allocator for stolen space (aka vram) */
	drm_mm_init(&dev_priv->vram, 0, prealloc_size);

1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
	/* Let GEM Manage from end of prealloc space to end of aperture.
	 *
	 * However, leave one page at the end still bound to the scratch page.
	 * There are a number of places where the hardware apparently
	 * prefetches past the end of the object, and we've seen multiple
	 * hangs with the GPU head pointer stuck in a batchbuffer bound
	 * at the last page of the aperture.  One page should be enough to
	 * keep any prefetching inside of the aperture.
	 */
	i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1027
1028
1029

	ret = i915_gem_init_ringbuffer(dev);
	if (ret)
1030
		goto out;
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055

	/* Allow hardware batchbuffers unless told otherwise.
	 */
	dev_priv->allow_batchbuffer = 1;

	ret = intel_init_bios(dev);
	if (ret)
		DRM_INFO("failed to find VBIOS tables\n");

	ret = drm_irq_install(dev);
	if (ret)
		goto destroy_ringbuffer;

	/* Always safe in the mode setting case. */
	/* FIXME: do pre/post-mode set stuff in core KMS code */
	dev->vblank_disable_allowed = 1;

	/*
	 * Initialize the hardware status page IRQ location.
	 */

	I915_WRITE(INSTPM, (1 << 5) | (1 << 21));

	intel_modeset_init(dev);

1056
	drm_helper_initial_config(dev);
1057
1058
1059
1060
1061
1062
1063
1064
1065

	return 0;

destroy_ringbuffer:
	i915_gem_cleanup_ringbuffer(dev);
out:
	return ret;
}

1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
int i915_master_create(struct drm_device *dev, struct drm_master *master)
{
	struct drm_i915_master_private *master_priv;

	master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
	if (!master_priv)
		return -ENOMEM;

	master->driver_priv = master_priv;
	return 0;
}

void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
{
	struct drm_i915_master_private *master_priv = master->driver_priv;

	if (!master_priv)
		return;

	drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);

	master->driver_priv = NULL;
}

1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
/**
 * i915_driver_load - setup chip and create an initial config
 * @dev: DRM device
 * @flags: startup flags
 *
 * The driver load routine has to do several things:
 *   - drive output discovery via intel_modeset_init()
 *   - initialize the memory manager
 *   - allocate initial config memory
 *   - setup the DRM framebuffer with the allocated memory
 */
1101
int i915_driver_load(struct drm_device *dev, unsigned long flags)
1102
{
1103
	struct drm_i915_private *dev_priv = dev->dev_private;
1104
	resource_size_t base, size;
1105
1106
	int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;

1107
1108
1109
1110
1111
1112
1113
	/* i915 has 4 more counters */
	dev->counters += 4;
	dev->types[6] = _DRM_STAT_IRQ;
	dev->types[7] = _DRM_STAT_PRIMARY;
	dev->types[8] = _DRM_STAT_SECONDARY;
	dev->types[9] = _DRM_STAT_DMA;

1114
1115
1116
1117
1118
1119
1120
	dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
	if (dev_priv == NULL)
		return -ENOMEM;

	memset(dev_priv, 0, sizeof(drm_i915_private_t));

	dev->dev_private = (void *)dev_priv;
1121
	dev_priv->dev = dev;
1122
1123
1124
1125
1126

	/* Add register map (needed for suspend/resume) */
	base = drm_get_resource_start(dev, mmio_bar);
	size = drm_get_resource_len(dev, mmio_bar);

1127
	dev_priv->regs = ioremap(base, size);
1128
1129
1130
1131
1132
	if (!dev_priv->regs) {
		DRM_ERROR("failed to map registers\n");
		ret = -EIO;
		goto free_priv;
	}
1133

1134
1135
1136
        dev_priv->mm.gtt_mapping =
		io_mapping_create_wc(dev->agp->base,
				     dev->agp->agp_info.aper_size * 1024*1024);
1137
1138
1139
1140
1141
	if (dev_priv->mm.gtt_mapping == NULL) {
		ret = -EIO;
		goto out_rmmap;
	}

1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
	/* Set up a WC MTRR for non-PAT systems.  This is more common than
	 * one would think, because the kernel disables PAT on first
	 * generation Core chips because WC PAT gets overridden by a UC
	 * MTRR if present.  Even if a UC MTRR isn't present.
	 */
	dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
					 dev->agp->agp_info.aper_size *
					 1024 * 1024,
					 MTRR_TYPE_WRCOMB, 1);
	if (dev_priv->mm.gtt_mtrr < 0) {
1152
		DRM_INFO("MTRR allocation failed.  Graphics "
1153
1154
1155
			 "performance may suffer.\n");
	}

1156
1157
1158
1159
1160
1161
1162
1163
#ifdef CONFIG_HIGHMEM64G
	/* don't enable GEM on PAE - needs agp + set_memory_* interface fixes */
	dev_priv->has_gem = 0;
#else
	/* enable GEM by default */
	dev_priv->has_gem = 1;
#endif

1164
	dev->driver->get_vblank_counter = i915_get_vblank_counter;
1165
	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1166
	if (IS_G4X(dev) || IS_IGDNG(dev)) {
1167
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1168
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1169
	}
1170

1171
1172
	i915_gem_load(dev);

1173
1174
1175
1176
	/* Init HWS */
	if (!I915_NEED_GFX_HWS(dev)) {
		ret = i915_init_phys_hws(dev);
		if (ret != 0)
1177
			goto out_iomapfree;
1178
	}
1179
1180
1181
1182
1183
1184
1185

	/* On the 945G/GM, the chipset reports the MSI capability on the
	 * integrated graphics even though the support isn't actually there
	 * according to the published specs.  It doesn't appear to function
	 * correctly in testing on 945G.
	 * This may be a side effect of MSI having been made available for PEG
	 * and the registers being closely associated.
1186
1187
	 *
	 * According to chipset errata, on the 965GM, MSI interrupts may
1188
1189
	 * be lost or delayed, but we use them anyways to avoid
	 * stuck interrupts on some machines.
1190
	 */
1191
	if (!IS_I945G(dev) && !IS_I945GM(dev))
1192
		pci_enable_msi(dev->pdev);
1193
1194

	spin_lock_init(&dev_priv->user_irq_lock);
1195
	dev_priv->user_irq_refcount = 0;
1196

1197
1198
1199
1200
1201
1202
1203
	ret = drm_vblank_init(dev, I915_NUM_PIPE);

	if (ret) {
		(void) i915_driver_unload(dev);
		return ret;
	}

1204
1205
1206
1207
1208
1209
1210
1211
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		ret = i915_load_modeset_init(dev);
		if (ret < 0) {
			DRM_ERROR("failed to init modeset\n");
			goto out_rmmap;
		}
	}

1212
	/* Must be done after probing outputs */