bnx2x.c 263 KB
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/* bnx2x.c: Broadcom Everest network driver.
 *
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 * Copyright (c) 2007-2008 Broadcom Corporation
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * Written by: Eliezer Tamir <eliezert@broadcom.com>
 * Based on code from Michael Chan's bnx2 driver
 * UDP CSUM errata workaround by Arik Gendelman
 * Slowpath rework by Vladislav Zolotarov
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 * Statistics and Link management by Yitchak Gertner
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 *
 */

/* define this to make the driver freeze on error
 * to allow getting debug info
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 * (you will need to reboot afterwards)
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 */
/*#define BNX2X_STOP_ON_ERROR*/

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>  /* for dev_info() */
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/dma-mapping.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <asm/byteorder.h>
#include <linux/time.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#ifdef NETIF_F_HW_VLAN_TX
	#include <linux/if_vlan.h>
	#define BCM_VLAN 1
#endif
#include <net/ip.h>
#include <net/tcp.h>
#include <net/checksum.h>
#include <linux/workqueue.h>
#include <linux/crc32.h>
#include <linux/prefetch.h>
#include <linux/zlib.h>
#include <linux/version.h>
#include <linux/io.h>

#include "bnx2x_reg.h"
#include "bnx2x_fw_defs.h"
#include "bnx2x_hsi.h"
#include "bnx2x.h"
#include "bnx2x_init.h"

#define DRV_MODULE_VERSION      "0.40.15"
#define DRV_MODULE_RELDATE      "$DateTime: 2007/11/15 07:28:37 $"
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#define BNX2X_BC_VER    	0x040200
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/* Time in jiffies before concluding the transmitter is hung. */
#define TX_TIMEOUT      	(5*HZ)

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static char version[] __devinitdata =
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	"Broadcom NetXtreme II 5771X 10Gigabit Ethernet Driver "
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	DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";

MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>");
MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);
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MODULE_INFO(cvs_version, "$Revision: #404 $");
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static int use_inta;
static int poll;
static int onefunc;
static int nomcp;
static int debug;
static int use_multi;

module_param(use_inta, int, 0);
module_param(poll, int, 0);
module_param(onefunc, int, 0);
module_param(debug, int, 0);
MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
MODULE_PARM_DESC(poll, "use polling (for debug)");
MODULE_PARM_DESC(onefunc, "enable only first function");
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MODULE_PARM_DESC(nomcp, "ignore management CPU (Implies onefunc)");
MODULE_PARM_DESC(debug, "default debug msglevel");
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#ifdef BNX2X_MULTI
module_param(use_multi, int, 0);
MODULE_PARM_DESC(use_multi, "use per-CPU queues");
#endif

enum bnx2x_board_type {
	BCM57710 = 0,
};

/* indexed by board_t, above */
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static struct {
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	char *name;
} board_info[] __devinitdata = {
	{ "Broadcom NetXtreme II BCM57710 XGb" }
};

static const struct pci_device_id bnx2x_pci_tbl[] = {
	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
		PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
	{ 0 }
};

MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);

/****************************************************************************
* General service functions
****************************************************************************/

/* used only at init
 * locking is done by mcp
 */
static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
{
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
	pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
			       PCICFG_VENDOR_ID_OFFSET);
}

#ifdef BNX2X_IND_RD
static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
{
	u32 val;

	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
	pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
	pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
			       PCICFG_VENDOR_ID_OFFSET);

	return val;
}
#endif

static const u32 dmae_reg_go_c[] = {
	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
};

/* copy command into DMAE command memory and set DMAE command go */
static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
			    int idx)
{
	u32 cmd_offset;
	int i;

	cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
	for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
		REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));

/*      	DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
		   idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */
	}
	REG_WR(bp, dmae_reg_go_c[idx], 1);
}

static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
			     u32 dst_addr, u32 len32)
{
	struct dmae_command *dmae = &bp->dmae;
	int port = bp->port;
	u32 *wb_comp = bnx2x_sp(bp, wb_comp);
	int timeout = 200;

	memset(dmae, 0, sizeof(struct dmae_command));

	dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
			DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
			DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
			(port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
	dmae->src_addr_lo = U64_LO(dma_addr);
	dmae->src_addr_hi = U64_HI(dma_addr);
	dmae->dst_addr_lo = dst_addr >> 2;
	dmae->dst_addr_hi = 0;
	dmae->len = len32;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
	dmae->comp_val = BNX2X_WB_COMP_VAL;

/*
	DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
	   DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
		    "dst_addr [%x:%08x (%08x)]\n"
	   DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
	   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
	   dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
	   dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
*/
/*
	DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
	   bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
	   bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
*/

	*wb_comp = 0;

	bnx2x_post_dmae(bp, dmae, port * 8);

	udelay(5);
	/* adjust timeout for emulation/FPGA */
	if (CHIP_REV_IS_SLOW(bp))
		timeout *= 100;
	while (*wb_comp != BNX2X_WB_COMP_VAL) {
/*      	DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */
		udelay(5);
		if (!timeout) {
			BNX2X_ERR("dmae timeout!\n");
			break;
		}
		timeout--;
	}
}

#ifdef BNX2X_DMAE_RD
static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
{
	struct dmae_command *dmae = &bp->dmae;
	int port = bp->port;
	u32 *wb_comp = bnx2x_sp(bp, wb_comp);
	int timeout = 200;

	memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
	memset(dmae, 0, sizeof(struct dmae_command));

	dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
			DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
			DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
#ifdef __BIG_ENDIAN
			DMAE_CMD_ENDIANITY_B_DW_SWAP |
#else
			DMAE_CMD_ENDIANITY_DW_SWAP |
#endif
			(port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
	dmae->src_addr_lo = src_addr >> 2;
	dmae->src_addr_hi = 0;
	dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
	dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
	dmae->len = len32;
	dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
	dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
	dmae->comp_val = BNX2X_WB_COMP_VAL;

/*
	DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
	   DP_LEVEL "src_addr  [%x:%08x]  len [%d *4]  "
		    "dst_addr [%x:%08x (%08x)]\n"
	   DP_LEVEL "comp_addr [%x:%08x]  comp_val 0x%08x\n",
	   dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
	   dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
	   dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
*/

	*wb_comp = 0;

	bnx2x_post_dmae(bp, dmae, port * 8);

	udelay(5);
	while (*wb_comp != BNX2X_WB_COMP_VAL) {
		udelay(5);
		if (!timeout) {
			BNX2X_ERR("dmae timeout!\n");
			break;
		}
		timeout--;
	}
/*
	DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
	   bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
	   bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
*/
}
#endif

static int bnx2x_mc_assert(struct bnx2x *bp)
{
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	int i, j, rc = 0;
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	char last_idx;
	const char storm[] = {"XTCU"};
	const u32 intmem_base[] = {
		BAR_XSTRORM_INTMEM,
		BAR_TSTRORM_INTMEM,
		BAR_CSTRORM_INTMEM,
		BAR_USTRORM_INTMEM
	};

	/* Go through all instances of all SEMIs */
	for (i = 0; i < 4; i++) {
		last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET +
				   intmem_base[i]);
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		if (last_idx)
			BNX2X_LOG("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n",
				  storm[i], last_idx);
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		/* print the asserts */
		for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) {
			u32 row0, row1, row2, row3;

			row0 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) +
				      intmem_base[i]);
			row1 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 4 +
				      intmem_base[i]);
			row2 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 8 +
				      intmem_base[i]);
			row3 = REG_RD(bp, XSTORM_ASSERT_LIST_OFFSET(j) + 12 +
				      intmem_base[i]);

			if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
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				BNX2X_LOG("DATA %cSTORM_ASSERT_INDEX 0x%x ="
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					  " 0x%08x 0x%08x 0x%08x 0x%08x\n",
					  storm[i], j, row3, row2, row1, row0);
				rc++;
			} else {
				break;
			}
		}
	}
	return rc;
}
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static void bnx2x_fw_dump(struct bnx2x *bp)
{
	u32 mark, offset;
	u32 data[9];
	int word;

	mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
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	mark = ((mark + 0x3) & ~0x3);
	printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
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	for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
		for (word = 0; word < 8; word++)
			data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
						  offset + 4*word));
		data[8] = 0x0;
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		printk(KERN_CONT "%s", (char *)data);
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	}
	for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
		for (word = 0; word < 8; word++)
			data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
						  offset + 4*word));
		data[8] = 0x0;
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		printk(KERN_CONT "%s", (char *)data);
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	}
	printk("\n" KERN_ERR PFX "end of fw dump\n");
}

static void bnx2x_panic_dump(struct bnx2x *bp)
{
	int i;
	u16 j, start, end;

	BNX2X_ERR("begin crash dump -----------------\n");

	for_each_queue(bp, i) {
		struct bnx2x_fastpath *fp = &bp->fp[i];
		struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;

		BNX2X_ERR("queue[%d]: tx_pkt_prod(%x)  tx_pkt_cons(%x)"
			  "  tx_bd_prod(%x)  tx_bd_cons(%x)  *tx_cons_sb(%x)"
			  "  *rx_cons_sb(%x)  rx_comp_prod(%x)"
			  "  rx_comp_cons(%x)  fp_c_idx(%x)  fp_u_idx(%x)"
			  "  bd data(%x,%x)\n",
			  i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
			  fp->tx_bd_cons, *fp->tx_cons_sb, *fp->rx_cons_sb,
			  fp->rx_comp_prod, fp->rx_comp_cons, fp->fp_c_idx,
			  fp->fp_u_idx, hw_prods->packets_prod,
			  hw_prods->bds_prod);

		start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
		end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
		for (j = start; j < end; j++) {
			struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];

			BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
				  sw_bd->skb, sw_bd->first_bd);
		}

		start = TX_BD(fp->tx_bd_cons - 10);
		end = TX_BD(fp->tx_bd_cons + 254);
		for (j = start; j < end; j++) {
			u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];

			BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
				  j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
		}

		start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
		end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
		for (j = start; j < end; j++) {
			u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
			struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];

			BNX2X_ERR("rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
				  j, rx_bd[0], rx_bd[1], sw_bd->skb);
		}

		start = RCQ_BD(fp->rx_comp_cons - 10);
		end = RCQ_BD(fp->rx_comp_cons + 503);
		for (j = start; j < end; j++) {
			u32 *cqe = (u32 *)&fp->rx_comp_ring[j];

			BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
				  j, cqe[0], cqe[1], cqe[2], cqe[3]);
		}
	}

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	BNX2X_ERR("def_c_idx(%u)  def_u_idx(%u)  def_x_idx(%u)"
		  "  def_t_idx(%u)  def_att_idx(%u)  attn_state(%u)"
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		  "  spq_prod_idx(%u)\n",
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		  bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
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		  bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);


	bnx2x_mc_assert(bp);
	BNX2X_ERR("end crash dump -----------------\n");

	bp->stats_state = STATS_STATE_DISABLE;
	DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n");
}

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static void bnx2x_int_enable(struct bnx2x *bp)
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{
	int port = bp->port;
	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
	u32 val = REG_RD(bp, addr);
	int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;

	if (msix) {
		val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
		val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
	} else {
		val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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			HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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			HC_CONFIG_0_REG_INT_LINE_EN_0 |
			HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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		/* Errata A0.158 workaround */
		DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
		   val, port, addr, msix);

		REG_WR(bp, addr, val);

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		val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
	}

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	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)  MSI-X %d\n",
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	   val, port, addr, msix);

	REG_WR(bp, addr, val);
}

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static void bnx2x_int_disable(struct bnx2x *bp)
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{
	int port = bp->port;
	u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
	u32 val = REG_RD(bp, addr);

	val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
		 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
		 HC_CONFIG_0_REG_INT_LINE_EN_0 |
		 HC_CONFIG_0_REG_ATTN_BIT_EN_0);

	DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
	   val, port, addr);

	REG_WR(bp, addr, val);
	if (REG_RD(bp, addr) != val)
		BNX2X_ERR("BUG! proper val not read from IGU!\n");
}

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static void bnx2x_int_disable_sync(struct bnx2x *bp)
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{

	int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
	int i;

	atomic_inc(&bp->intr_sem);
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	/* prevent the HW from sending interrupts */
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	bnx2x_int_disable(bp);
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	/* make sure all ISRs are done */
	if (msix) {
		for_each_queue(bp, i)
			synchronize_irq(bp->msix_table[i].vector);

		/* one more for the Slow Path IRQ */
		synchronize_irq(bp->msix_table[i].vector);
	} else
		synchronize_irq(bp->pdev->irq);

	/* make sure sp_task is not running */
	cancel_work_sync(&bp->sp_task);

}

/* fast path code */

/*
 * general service functions
 */

static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 id,
				u8 storm, u16 index, u8 op, u8 update)
{
	u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_PORT_BASE * bp->port) * 8;
	struct igu_ack_register igu_ack;

	igu_ack.status_block_index = index;
	igu_ack.sb_id_and_flags =
			((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
			 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
			 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
			 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));

/*      DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
	   (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr); */
	REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
}

static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
{
	struct host_status_block *fpsb = fp->status_blk;
	u16 rc = 0;

	barrier(); /* status block is written to by the chip */
	if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
		fp->fp_c_idx = fpsb->c_status_block.status_block_index;
		rc |= 1;
	}
	if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
		fp->fp_u_idx = fpsb->u_status_block.status_block_index;
		rc |= 2;
	}
	return rc;
}

static inline int bnx2x_has_work(struct bnx2x_fastpath *fp)
{
	u16 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);

	if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
		rx_cons_sb++;

	if ((rx_cons_sb != fp->rx_comp_cons) ||
	    (le16_to_cpu(*fp->tx_cons_sb) != fp->tx_pkt_cons))
		return 1;

	return 0;
}

static u16 bnx2x_ack_int(struct bnx2x *bp)
{
	u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_PORT_BASE * bp->port) * 8;
	u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);

/*      DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
	   result, BAR_IGU_INTMEM + igu_addr); */

#ifdef IGU_DEBUG
#warning IGU_DEBUG active
	if (result == 0) {
		BNX2X_ERR("read %x from IGU\n", result);
		REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
	}
#endif
	return result;
}


/*
 * fast path service functions
 */

/* free skb in the packet ring at pos idx
 * return idx of last bd freed
 */
static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
			     u16 idx)
{
	struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
	struct eth_tx_bd *tx_bd;
	struct sk_buff *skb = tx_buf->skb;
	u16 bd_idx = tx_buf->first_bd;
	int nbd;

	DP(BNX2X_MSG_OFF, "pkt_idx %d  buff @(%p)->skb %p\n",
	   idx, tx_buf, skb);

	/* unmap first bd */
	DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
	tx_bd = &fp->tx_desc_ring[bd_idx];
	pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
			 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);

	nbd = le16_to_cpu(tx_bd->nbd) - 1;
#ifdef BNX2X_STOP_ON_ERROR
	if (nbd > (MAX_SKB_FRAGS + 2)) {
		BNX2X_ERR("bad nbd!\n");
		bnx2x_panic();
	}
#endif

	/* Skip a parse bd and the TSO split header bd
	   since they have no mapping */
	if (nbd)
		bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));

	if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
					   ETH_TX_BD_FLAGS_TCP_CSUM |
					   ETH_TX_BD_FLAGS_SW_LSO)) {
		if (--nbd)
			bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
		tx_bd = &fp->tx_desc_ring[bd_idx];
		/* is this a TSO split header bd? */
		if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
			if (--nbd)
				bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
		}
	}

	/* now free frags */
	while (nbd > 0) {

		DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
		tx_bd = &fp->tx_desc_ring[bd_idx];
		pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
			       BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
		if (--nbd)
			bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
	}

	/* release skb */
	BUG_TRAP(skb);
	dev_kfree_skb(skb);
	tx_buf->first_bd = 0;
	tx_buf->skb = NULL;

	return bd_idx;
}

static inline u32 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
{
	u16 used;
	u32 prod;
	u32 cons;

	/* Tell compiler that prod and cons can change */
	barrier();
	prod = fp->tx_bd_prod;
	cons = fp->tx_bd_cons;

	used = (NUM_TX_BD - NUM_TX_RINGS + prod - cons +
		(cons / TX_DESC_CNT) - (prod / TX_DESC_CNT));

	if (prod >= cons) {
		/* used = prod - cons - prod/size + cons/size */
		used -= NUM_TX_BD - NUM_TX_RINGS;
	}

	BUG_TRAP(used <= fp->bp->tx_ring_size);
	BUG_TRAP((fp->bp->tx_ring_size - used) <= MAX_TX_AVAIL);

	return (fp->bp->tx_ring_size - used);
}

static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
{
	struct bnx2x *bp = fp->bp;
	u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
	int done = 0;

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return;
#endif

	hw_cons = le16_to_cpu(*fp->tx_cons_sb);
	sw_cons = fp->tx_pkt_cons;

	while (sw_cons != hw_cons) {
		u16 pkt_cons;

		pkt_cons = TX_BD(sw_cons);

		/* prefetch(bp->tx_buf_ring[pkt_cons].skb); */

		DP(NETIF_MSG_TX_DONE, "hw_cons %u  sw_cons %u  pkt_cons %d\n",
		   hw_cons, sw_cons, pkt_cons);

/*      	if (NEXT_TX_IDX(sw_cons) != hw_cons) {
			rmb();
			prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
		}
*/
		bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
		sw_cons++;
		done++;

		if (done == work)
			break;
	}

	fp->tx_pkt_cons = sw_cons;
	fp->tx_bd_cons = bd_cons;

	/* Need to make the tx_cons update visible to start_xmit()
	 * before checking for netif_queue_stopped().  Without the
	 * memory barrier, there is a small possibility that start_xmit()
	 * will miss it and cause the queue to be stopped forever.
	 */
	smp_mb();

	/* TBD need a thresh? */
	if (unlikely(netif_queue_stopped(bp->dev))) {

		netif_tx_lock(bp->dev);

		if (netif_queue_stopped(bp->dev) &&
		    (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
			netif_wake_queue(bp->dev);

		netif_tx_unlock(bp->dev);

	}
}

static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
			   union eth_rx_cqe *rr_cqe)
{
	struct bnx2x *bp = fp->bp;
	int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
	int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);

	DP(NETIF_MSG_RX_STATUS,
	   "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
	   fp->index, cid, command, bp->state, rr_cqe->ramrod_cqe.type);

	bp->spq_left++;

	if (fp->index) {
		switch (command | fp->state) {
		case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
						BNX2X_FP_STATE_OPENING):
			DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
			   cid);
			fp->state = BNX2X_FP_STATE_OPEN;
			break;

		case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
			DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
			   cid);
			fp->state = BNX2X_FP_STATE_HALTED;
			break;

		default:
			BNX2X_ERR("unexpected MC reply(%d)  state is %x\n",
				  command, fp->state);
		}
		mb(); /* force bnx2x_wait_ramrod to see the change */
		return;
	}
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	switch (command | bp->state) {
	case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
		DP(NETIF_MSG_IFUP, "got setup ramrod\n");
		bp->state = BNX2X_STATE_OPEN;
		break;

	case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
		DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
		bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
		fp->state = BNX2X_FP_STATE_HALTED;
		break;

	case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
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		DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n",
		   cid);
		bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
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		break;

	case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
		DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
		break;

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	case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
		DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n");
		break;

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	default:
		BNX2X_ERR("unexpected ramrod (%d)  state is %x\n",
			  command, bp->state);
	}

	mb(); /* force bnx2x_wait_ramrod to see the change */
}

static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
				     struct bnx2x_fastpath *fp, u16 index)
{
	struct sk_buff *skb;
	struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
	struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
	dma_addr_t mapping;

	skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
	if (unlikely(skb == NULL))
		return -ENOMEM;

	mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
				 PCI_DMA_FROMDEVICE);
	if (unlikely(dma_mapping_error(mapping))) {

		dev_kfree_skb(skb);
		return -ENOMEM;
	}

	rx_buf->skb = skb;
	pci_unmap_addr_set(rx_buf, mapping, mapping);

	rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
	rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));

	return 0;
}

/* note that we are not allocating a new skb,
 * we are just moving one from cons to prod
 * we are not creating a new mapping,
 * so there is no need to check for dma_mapping_error().
 */
static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
			       struct sk_buff *skb, u16 cons, u16 prod)
{
	struct bnx2x *bp = fp->bp;
	struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
	struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
	struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
	struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];

	pci_dma_sync_single_for_device(bp->pdev,
				       pci_unmap_addr(cons_rx_buf, mapping),
				       bp->rx_offset + RX_COPY_THRESH,
				       PCI_DMA_FROMDEVICE);

	prod_rx_buf->skb = cons_rx_buf->skb;
	pci_unmap_addr_set(prod_rx_buf, mapping,
			   pci_unmap_addr(cons_rx_buf, mapping));
	*prod_bd = *cons_bd;
}

static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
{
	struct bnx2x *bp = fp->bp;
	u16 bd_cons, bd_prod, comp_ring_cons;
	u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
	int rx_pkt = 0;

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return 0;
#endif

	hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
	if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
		hw_comp_cons++;

	bd_cons = fp->rx_bd_cons;
	bd_prod = fp->rx_bd_prod;
	sw_comp_cons = fp->rx_comp_cons;
	sw_comp_prod = fp->rx_comp_prod;

	/* Memory barrier necessary as speculative reads of the rx
	 * buffer can be ahead of the index in the status block
	 */
	rmb();

	DP(NETIF_MSG_RX_STATUS,
	   "queue[%d]:  hw_comp_cons %u  sw_comp_cons %u\n",
	   fp->index, hw_comp_cons, sw_comp_cons);

	while (sw_comp_cons != hw_comp_cons) {
		unsigned int len, pad;
		struct sw_rx_bd *rx_buf;
		struct sk_buff *skb;
		union eth_rx_cqe *cqe;

		comp_ring_cons = RCQ_BD(sw_comp_cons);
		bd_prod = RX_BD(bd_prod);
		bd_cons = RX_BD(bd_cons);

		cqe = &fp->rx_comp_ring[comp_ring_cons];

		DP(NETIF_MSG_RX_STATUS, "hw_comp_cons %u  sw_comp_cons %u"
		   "  comp_ring (%u)  bd_ring (%u,%u)\n",
		   hw_comp_cons, sw_comp_cons,
		   comp_ring_cons, bd_prod, bd_cons);
		DP(NETIF_MSG_RX_STATUS, "CQE type %x  err %x  status %x"
		   "  queue %x  vlan %x  len %x\n",
		   cqe->fast_path_cqe.type,
		   cqe->fast_path_cqe.error_type_flags,
		   cqe->fast_path_cqe.status_flags,
		   cqe->fast_path_cqe.rss_hash_result,
		   cqe->fast_path_cqe.vlan_tag, cqe->fast_path_cqe.pkt_len);

		/* is this a slowpath msg? */
		if (unlikely(cqe->fast_path_cqe.type)) {
			bnx2x_sp_event(fp, cqe);
			goto next_cqe;

		/* this is an rx packet */
		} else {
			rx_buf = &fp->rx_buf_ring[bd_cons];
			skb = rx_buf->skb;

			len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
			pad = cqe->fast_path_cqe.placement_offset;

			pci_dma_sync_single_for_device(bp->pdev,
					pci_unmap_addr(rx_buf, mapping),
						       pad + RX_COPY_THRESH,
						       PCI_DMA_FROMDEVICE);
			prefetch(skb);
			prefetch(((char *)(skb)) + 128);

			/* is this an error packet? */
			if (unlikely(cqe->fast_path_cqe.error_type_flags &
							ETH_RX_ERROR_FALGS)) {
			/* do we sometimes forward error packets anyway? */
				DP(NETIF_MSG_RX_ERR,
				   "ERROR flags(%u) Rx packet(%u)\n",
				   cqe->fast_path_cqe.error_type_flags,
				   sw_comp_cons);
				/* TBD make sure MC counts this as a drop */
				goto reuse_rx;
			}

			/* Since we don't have a jumbo ring
			 * copy small packets if mtu > 1500
			 */
			if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
			    (len <= RX_COPY_THRESH)) {
				struct sk_buff *new_skb;

				new_skb = netdev_alloc_skb(bp->dev,
							   len + pad);
				if (new_skb == NULL) {
					DP(NETIF_MSG_RX_ERR,
					   "ERROR packet dropped "
					   "because of alloc failure\n");
					/* TBD count this as a drop? */
					goto reuse_rx;
				}

				/* aligned copy */
				skb_copy_from_linear_data_offset(skb, pad,
						    new_skb->data + pad, len);
				skb_reserve(new_skb, pad);
				skb_put(new_skb, len);

				bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);

				skb = new_skb;

			} else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
				pci_unmap_single(bp->pdev,
					pci_unmap_addr(rx_buf, mapping),
						 bp->rx_buf_use_size,
						 PCI_DMA_FROMDEVICE);
				skb_reserve(skb, pad);
				skb_put(skb, len);

			} else {
				DP(NETIF_MSG_RX_ERR,
				   "ERROR packet dropped because "
				   "of alloc failure\n");
reuse_rx:
				bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
				goto next_rx;
			}

			skb->protocol = eth_type_trans(skb, bp->dev);

			skb->ip_summed = CHECKSUM_NONE;
			if (bp->rx_csum && BNX2X_RX_SUM_OK(cqe))
				skb->ip_summed = CHECKSUM_UNNECESSARY;

			/* TBD do we pass bad csum packets in promisc */
		}

#ifdef BCM_VLAN
		if ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags)
				& PARSING_FLAGS_NUMBER_OF_NESTED_VLANS)
		    && (bp->vlgrp != NULL))
			vlan_hwaccel_receive_skb(skb, bp->vlgrp,
				le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
		else
#endif
		netif_receive_skb(skb);

		bp->dev->last_rx = jiffies;

next_rx:
		rx_buf->skb = NULL;

		bd_cons = NEXT_RX_IDX(bd_cons);
		bd_prod = NEXT_RX_IDX(bd_prod);
next_cqe:
		sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
		sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
		rx_pkt++;

		if ((rx_pkt == budget))
			break;
	} /* while */

	fp->rx_bd_cons = bd_cons;
	fp->rx_bd_prod = bd_prod;
	fp->rx_comp_cons = sw_comp_cons;
	fp->rx_comp_prod = sw_comp_prod;

	REG_WR(bp, BAR_TSTRORM_INTMEM +
	       TSTORM_RCQ_PROD_OFFSET(bp->port, fp->index), sw_comp_prod);

	mmiowb(); /* keep prod updates ordered */

	fp->rx_pkt += rx_pkt;
	fp->rx_calls++;

	return rx_pkt;
}

static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
{
	struct bnx2x_fastpath *fp = fp_cookie;
	struct bnx2x *bp = fp->bp;
	struct net_device *dev = bp->dev;
	int index = fp->index;

	DP(NETIF_MSG_INTR, "got an msix interrupt on [%d]\n", index);
	bnx2x_ack_sb(bp, index, USTORM_ID, 0, IGU_INT_DISABLE, 0);

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return IRQ_HANDLED;
#endif

	prefetch(fp->rx_cons_sb);
	prefetch(fp->tx_cons_sb);
	prefetch(&fp->status_blk->c_status_block.status_block_index);
	prefetch(&fp->status_blk->u_status_block.status_block_index);

	netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
	return IRQ_HANDLED;
}

static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
{
	struct net_device *dev = dev_instance;
	struct bnx2x *bp = netdev_priv(dev);
	u16 status = bnx2x_ack_int(bp);

	if (unlikely(status == 0)) {
		DP(NETIF_MSG_INTR, "not our interrupt!\n");
		return IRQ_NONE;
	}

	DP(NETIF_MSG_INTR, "got an interrupt status is %u\n", status);

#ifdef BNX2X_STOP_ON_ERROR
	if (unlikely(bp->panic))
		return IRQ_HANDLED;
#endif

	/* Return here if interrupt is shared and is disabled */
	if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
		DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
		return IRQ_HANDLED;
	}

	if (status & 0x2) {
		struct bnx2x_fastpath *fp = &bp->fp[0];

		prefetch(fp->rx_cons_sb);
		prefetch(fp->tx_cons_sb);
		prefetch(&fp->status_blk->c_status_block.status_block_index);
		prefetch(&fp->status_blk->u_status_block.status_block_index);

		netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));

		status &= ~0x2;
		if (!status)
			return IRQ_HANDLED;
	}

	if (unlikely(status & 0x1)) {

		schedule_work(&bp->sp_task);

		status &= ~0x1;
		if (!status)
			return IRQ_HANDLED;
	}

	DP(NETIF_MSG_INTR, "got an unknown interrupt! (status is %u)\n",
	   status);

	return IRQ_HANDLED;
}

/* end of fast path */

/* PHY/MAC */

/*
 * General service functions
 */

static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
{
	int port = bp->port;

	NIG_WR(NIG_REG_LED_MODE_P0 + port*4,
	       ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
		SHARED_HW_CFG_LED_MODE_SHIFT));
	NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);

	/* Set blinking rate to ~15.9Hz */
	NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
	       LED_BLINK_RATE_VAL);
	NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);

	/* On Ax chip versions for speeds less than 10G
	   LED scheme is different */
	if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) {
		NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1);
		NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0);
		NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1);
	}
}

static void bnx2x_leds_unset(struct bnx2x *bp)
{
	int port = bp->port;

	NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0);
	NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
}

static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
{
	u32 val = REG_RD(bp, reg);

	val |= bits;
	REG_WR(bp, reg, val);
	return val;
}

static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
{
	u32 val = REG_RD(bp, reg);

	val &= ~bits;
	REG_WR(bp, reg, val);
	return val;
}

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static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
{
	u32 cnt;
	u32 lock_status;
	u32 resource_bit = (1 << resource);
	u8 func = bp->port;

	/* Validating that the resource is within range */
	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
		DP(NETIF_MSG_HW,
		   "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
		   resource, HW_LOCK_MAX_RESOURCE_VALUE);
		return -EINVAL;
	}

	/* Validating that the resource is not already taken */
	lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
	if (lock_status & resource_bit) {
		DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
		   lock_status, resource_bit);
		return -EEXIST;
	}

	/* Try for 1 second every 5ms */
	for (cnt = 0; cnt < 200; cnt++) {
		/* Try to acquire the lock */
		REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8 + 4,
		       resource_bit);
		lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
		if (lock_status & resource_bit)
			return 0;

		msleep(5);
	}
	DP(NETIF_MSG_HW, "Timeout\n");
	return -EAGAIN;
}

static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
{
	u32 lock_status;
	u32 resource_bit = (1 << resource);
	u8 func = bp->port;

	/* Validating that the resource is within range */
	if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
		DP(NETIF_MSG_HW,
		   "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
		   resource, HW_LOCK_MAX_RESOURCE_VALUE);
		return -EINVAL;
	}

	/* Validating that the resource is currently taken */
	lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8);
	if (!(lock_status & resource_bit)) {
		DP(NETIF_MSG_HW, "lock_status 0x%x  resource_bit 0x%x\n",
		   lock_status, resource_bit);
		return -EFAULT;
	}

	REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8, resource_bit);
	return 0;
}

static int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
{
	/* The GPIO should be swapped if swap register is set and active */
	int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
			 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ bp->port;
	int gpio_shift = gpio_num +
			(gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
	u32 gpio_mask = (1 << gpio_shift);
	u32 gpio_reg;

	if (gpio_num > MISC_REGISTERS_GPIO_3) {
		BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
		return -EINVAL;
	}

	bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
	/* read GPIO and mask except the float bits */
	gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);

	switch (mode) {
	case MISC_REGISTERS_GPIO_OUTPUT_LOW:
		DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
		   gpio_num, gpio_shift);
		/* clear FLOAT and set CLR */
		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
		break;

	case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
		DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
		   gpio_num, gpio_shift);
		/* clear FLOAT and set SET */
		gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
		gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
		break;

	case MISC_REGISTERS_GPIO_INPUT_HI_Z :
		DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
		   gpio_num, gpio_shift);
		/* set FLOAT */
		gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
		break;

	default:
		break;
	}

	REG_WR(bp, MISC_REG_GPIO, gpio_reg);
	bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO);

	return 0;
}

static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
{
	u32 spio_mask = (1 << spio_num);
	u32 spio_reg;

	if ((spio_num < MISC_REGISTERS_SPIO_4) ||
	    (spio_num > MISC_REGISTERS_SPIO_7)) {
		BNX2X_ERR("Invalid SPIO %d\n", spio_num);
		return -EINVAL;
	}

	bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
	/* read SPIO and mask except the float bits */
	spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);

	switch (mode) {
	case MISC_REGISTERS_SPIO_OUTPUT_LOW :
		DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
		/* clear FLOAT and set CLR */
		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
		break;

	case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
		DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
		/* clear FLOAT and set SET */
		spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
		spio_reg |=  (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
		break;

	case MISC_REGISTERS_SPIO_INPUT_HI_Z:
		DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
		/* set FLOAT */
		spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
		break;

	default:
		break;
	}

	REG_WR(bp, MISC_REG_SPIO, spio_reg);
	bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO);

	return 0;
}

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static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val)
{
	int port = bp->port;
	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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	u32 tmp;
	int i, rc;
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/*      DP(NETIF_MSG_HW, "phy_addr 0x%x  reg 0x%x  val 0x%08x\n",
	   bp->phy_addr, reg, val); */

	if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {

		tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
		tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
		EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
		REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
		udelay(40);
	}

	tmp = ((bp->phy_addr << 21) | (reg << 16) |
	       (val & EMAC_MDIO_COMM_DATA) |
	       EMAC_MDIO_COMM_COMMAND_WRITE_22 |
	       EMAC_MDIO_COMM_START_BUSY);
	EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);

	for (i = 0; i < 50; i++) {
		udelay(10);

		tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
		if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}

	if (tmp & EMAC_MDIO_COMM_START_BUSY) {
		BNX2X_ERR("write phy register failed\n");

		rc = -EBUSY;
	} else {
		rc = 0;
	}

	if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {

		tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
		tmp |= EMAC_MDIO_MODE_AUTO_POLL;
		EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
	}

	return rc;
}

static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
{
	int port = bp->port;
	u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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	u32 val;
	int i, rc;
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	if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {

		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
		val &= ~EMAC_MDIO_MODE_AUTO_POLL;
		EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
		REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
		udelay(40);
	}

	val = ((bp->phy_addr << 21) | (reg << 16) |
	       EMAC_MDIO_COMM_COMMAND_READ_22 |
	       EMAC_MDIO_COMM_START_BUSY);
	EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);

	for (i = 0; i < 50; i++) {
		udelay(10);

		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
		if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
			val &= EMAC_MDIO_COMM_DATA;
			break;
		}
	}

	if (val & EMAC_MDIO_COMM_START_BUSY) {
		BNX2X_ERR("read phy register failed\n");

		*ret_val = 0x0;
		rc = -EBUSY;
	} else {
		*ret_val = val;
		rc = 0;
	}

	if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {

		val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
		val |= EMAC_MDIO_MODE_AUTO_POLL;
		EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
	}

/*      DP(NETIF_MSG_HW, "phy_addr 0x%x  reg 0x%x  ret_val 0x%08x\n",
	   bp->phy_addr, reg, *ret_val); */

	return rc;
}

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static int bnx2x_mdio45_ctrl_write(struct bnx2x *bp, u32 mdio_ctrl,
				   u32 phy_addr, u32 reg, u32 addr, u32 val)
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{
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	u32 tmp;
	int i, rc = 0;
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	/* set clause 45 mode, slow down the MDIO clock to 2.5MHz
	 * (a value of 49==0x31) and make sure that the AUTO poll is off
	 */
	tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	tmp &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
	tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
		(49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
	REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
	REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	udelay(40);
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	/* address */
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	tmp = ((phy_addr << 21) | (reg << 16) | addr |
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	       EMAC_MDIO_COMM_COMMAND_ADDRESS |
	       EMAC_MDIO_COMM_START_BUSY);
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	REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
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	for (i = 0; i < 50; i++) {
		udelay(10);

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		tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
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		if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}
	if (tmp & EMAC_MDIO_COMM_START_BUSY) {
		BNX2X_ERR("write phy register failed\n");

		rc = -EBUSY;
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	} else {
		/* data */
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		tmp = ((phy_addr << 21) | (reg << 16) | val |
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		       EMAC_MDIO_COMM_COMMAND_WRITE_45 |
		       EMAC_MDIO_COMM_START_BUSY);
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		REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
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		for (i = 0; i < 50; i++) {
			udelay(10);

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			tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
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			if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
				udelay(5);
				break;
			}
		}

		if (tmp & EMAC_MDIO_COMM_START_BUSY) {
			BNX2X_ERR("write phy register failed\n");

			rc = -EBUSY;
		}
	}

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	/* unset clause 45 mode, set the MDIO clock to a faster value
	 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
	 */
	tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	tmp &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
	tmp |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
	if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
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		tmp |= EMAC_MDIO_MODE_AUTO_POLL;
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	REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
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	return rc;
}

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static int bnx2x_mdio45_write(struct bnx2x *bp, u32 phy_addr, u32 reg,
			      u32 addr, u32 val)
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{
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	u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
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	return bnx2x_mdio45_ctrl_write(bp, emac_base, phy_addr,
				       reg, addr, val);
}
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static int bnx2x_mdio45_ctrl_read(struct bnx2x *bp, u32 mdio_ctrl,
				  u32 phy_addr, u32 reg, u32 addr,
				  u32 *ret_val)
{
	u32 val;
	int i, rc = 0;
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	/* set clause 45 mode, slow down the MDIO clock to 2.5MHz
	 * (a value of 49==0x31) and make sure that the AUTO poll is off
	 */
	val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	val &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
	val |= (EMAC_MDIO_MODE_CLAUSE_45 |
		(49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
	REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
	REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	udelay(40);
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	/* address */
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	val = ((phy_addr << 21) | (reg << 16) | addr |
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	       EMAC_MDIO_COMM_COMMAND_ADDRESS |
	       EMAC_MDIO_COMM_START_BUSY);
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	REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
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	for (i = 0; i < 50; i++) {
		udelay(10);

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		val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
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		if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
			udelay(5);
			break;
		}
	}
	if (val & EMAC_MDIO_COMM_START_BUSY) {
		BNX2X_ERR("read phy register failed\n");

		*ret_val = 0;
		rc = -EBUSY;
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	} else {
		/* data */
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		val = ((phy_addr << 21) | (reg << 16) |
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		       EMAC_MDIO_COMM_COMMAND_READ_45 |
		       EMAC_MDIO_COMM_START_BUSY);
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		REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
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		for (i = 0; i < 50; i++) {
			udelay(10);

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			val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
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			if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
				val &= EMAC_MDIO_COMM_DATA;
				break;
			}
		}

		if (val & EMAC_MDIO_COMM_START_BUSY) {
			BNX2X_ERR("read phy register failed\n");

			val = 0;
			rc = -EBUSY;
		}

		*ret_val = val;
	}

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	/* unset clause 45 mode, set the MDIO clock to a faster value
	 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
	 */
	val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
	val &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
	val |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
	if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
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		val |= EMAC_MDIO_MODE_AUTO_POLL;
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	REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
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	return rc;
}

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static int bnx2x_mdio45_read(struct bnx2x *bp, u32 phy_addr, u32 reg,
			     u32 addr, u32 *ret_val)
{
	u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;

	return bnx2x_mdio45_ctrl_read(bp, emac_base, phy_addr,
				      reg, addr, ret_val);
}

static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 phy_addr, u32 reg,
			       u32 addr, u32 val)
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{
	int i;
	u32 rd_val;

	might_sleep();
	for (i = 0; i < 10; i++) {
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		bnx2x_mdio45_write(bp, phy_addr, reg, addr, val);
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		msleep(5);
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		bnx2x_mdio45_read(bp, phy_addr, reg, addr, &rd_val);
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		/* if the read value is not the same as the value we wrote,
		   we should write it again */
		if (rd_val == val)
			return 0;
	}
	BNX2X_ERR("MDIO write in CL45 failed\n");
	return -EBUSY;
}

/*
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 * link management
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 */

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static void bnx2x_pause_resolve(struct bnx2x *bp, u32 pause_result)
{
	switch (pause_result) {			/* ASYM P ASYM P */
	case 0xb:				/*   1  0   1  1 */
		bp->flow_ctrl = FLOW_CTRL_TX;
		break;

	case 0xe:				/*   1  1   1  0 */
		bp->flow_ctrl = FLOW_CTRL_RX;
		break;

	case 0x5:				/*   0  1   0  1 */
	case 0x7:				/*   0  1   1  1 */
	case 0xd:				/*   1  1   0  1 */
	case 0xf:				/*   1  1   1  1 */
		bp->flow_ctrl = FLOW_CTRL_BOTH;
		break;

	default:
		break;
	}
}

static u8 bnx2x_ext_phy_resove_fc(struct bnx2x *bp)
{
	u32 ext_phy_addr;
	u32 ld_pause;	/* local */
	u32 lp_pause;	/* link partner */
	u32 an_complete; /* AN complete */
	u32 pause_result;
	u8 ret = 0;

	ext_phy_addr = ((bp->ext_phy_config &
			 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
					PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);

	/* read twice */
	bnx2x_mdio45_read(bp, ext_phy_addr,
			  EXT_PHY_KR_AUTO_NEG_DEVAD,
			  EXT_PHY_KR_STATUS, &an_complete);
	bnx2x_mdio45_read(bp, ext_phy_addr,
			  EXT_PHY_KR_AUTO_NEG_DEVAD,
			  EXT_PHY_KR_STATUS, &an_complete);

	if (an_complete & EXT_PHY_KR_AUTO_NEG_COMPLETE) {
		ret = 1;
		bnx2x_mdio45_read(bp, ext_phy_addr,
				  EXT_PHY_KR_AUTO_NEG_DEVAD,
				  EXT_PHY_KR_AUTO_NEG_ADVERT, &ld_pause);
		bnx2x_mdio45_read(bp, ext_phy_addr,
				  EXT_PHY_KR_AUTO_NEG_DEVAD,
				  EXT_PHY_KR_LP_AUTO_NEG, &lp_pause);
		pause_result = (ld_pause &
				EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 8;
		pause_result |= (lp_pause &
				 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 10;
		DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
		   pause_result);
		bnx2x_pause_resolve(bp, pause_result);
	}
	return ret;
}

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static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
{
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	u32 ld_pause;	/* local driver */
	u32 lp_pause;	/* link partner */
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	u32 pause_result;

	bp->flow_ctrl = 0;

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	/* resolve from gp_status in case of AN complete and not sgmii */
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	if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
	    (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
	    (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
	    (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {

		MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
		bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
				  &ld_pause);
		bnx2x_mdio22_read(bp,
			MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
				  &lp_pause);
		pause_result = (ld_pause &
				MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
		pause_result |= (lp_pause &
				 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
		DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
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		bnx2x_pause_resolve(bp, pause_result);
	} else if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) ||
		   !(bnx2x_ext_phy_resove_fc(bp))) {
		/* forced speed */
		if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
			switch (bp->req_flow_ctrl) {
			case FLOW_CTRL_AUTO:
				if (bp->dev->mtu <= 4500)
					bp->flow_ctrl = FLOW_CTRL_BOTH;
				else
					bp->flow_ctrl = FLOW_CTRL_TX;
				break;
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			case FLOW_CTRL_TX:
				bp->flow_ctrl = FLOW_CTRL_TX;
				break;
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			case FLOW_CTRL_RX:
				if (bp->dev->mtu <= 4500)
					bp->flow_ctrl = FLOW_CTRL_RX;
				break;
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			case FLOW_CTRL_BOTH:
				if (bp->dev->mtu <= 4500)
					bp->flow_ctrl = FLOW_CTRL_BOTH;
				else
					bp->flow_ctrl = FLOW_CTRL_TX;
				break;
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			case FLOW_CTRL_NONE:
			default:
				break;
			}
		} else { /* forced mode */
			switch (bp->req_flow_ctrl) {
			case FLOW_CTRL_AUTO:
				DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
						   " req_autoneg 0x%x\n",
				   bp->req_flow_ctrl, bp->req_autoneg);
				break;
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			case FLOW_CTRL_TX:
			case FLOW_CTRL_RX:
			case FLOW_CTRL_BOTH:
				bp->flow_ctrl = bp->req_flow_ctrl;
				break;
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			case FLOW_CTRL_NONE:
			default:
				break;
			}
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		}
	}
	DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
}

static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
{
	bp->link_status = 0;

	if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
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		DP(NETIF_MSG_LINK, "phy link up\n");
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		bp->phy_link_up = 1;
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		bp->link_status |= LINK_STATUS_LINK_UP;

		if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
			bp->duplex = DUPLEX_FULL;
		else
			bp->duplex = DUPLEX_HALF;

		bnx2x_flow_ctrl_resolve(bp, gp_status);

		switch (gp_status & GP_STATUS_SPEED_MASK) {
		case GP_STATUS_10M:
			bp->line_speed = SPEED_10;
			if (bp->duplex == DUPLEX_FULL)
				bp->link_status |= LINK_10TFD;
			else
				bp->link_status |= LINK_10THD;
			break;

		case GP_STATUS_100M:
			bp->line_speed = SPEED_100;
			if (bp->duplex == DUPLEX_FULL)
				bp->link_status |= LINK_100TXFD;
			else
				bp->link_status |= LINK_100TXHD;
			break;

		case GP_STATUS_1G:
		case GP_STATUS_1G_KX:
			bp->line_speed = SPEED_1000;
			if (bp->duplex == DUPLEX_FULL)
				bp->link_status |= LINK_1000TFD;
			else
				bp->link_status |= LINK_1000THD;
			break;

		case GP_STATUS_2_5G:
			bp->line_speed = SPEED_2500;
			if (bp->duplex == DUPLEX_FULL)
				bp->link_status |= LINK_2500TFD;
			else
				bp->link_status |= LINK_2500THD;
			break;

		case GP_STATUS_5G:
		case GP_STATUS_6G:
			BNX2X_ERR("link speed unsupported  gp_status 0x%x\n",
				  gp_status);
			break;

		case GP_STATUS_10G_KX4:
		case GP_STATUS_10G_HIG:
		case GP_STATUS_10G_CX4:
			bp->line_speed = SPEED_10000;
			bp->link_status |= LINK_10GTFD;
			break;

		case GP_STATUS_12G_HIG:
			bp->line_speed = SPEED_12000;
			bp->link_status |= LINK_12GTFD;
			break;

		case GP_STATUS_12_5G:
			bp->line_speed = SPEED_12500;
			bp->link_status |= LINK_12_5GTFD;
			break;

		case GP_STATUS_13G:
			bp->line_speed = SPEED_13000;
			bp->link_status |= LINK_13GTFD;
			break;

		case GP_STATUS_15G:
			bp->line_speed = SPEED_15000;
			bp->link_status |= LINK_15GTFD;
			break;

		case GP_STATUS_16G:
			bp->line_speed = SPEED_16000;
			bp->link_status |= LINK_16GTFD;
			break;

		default:
			BNX2X_ERR("link speed unsupported  gp_status 0x%x\n",
				  gp_status);
			break;
		}

		bp->link_status |= LINK_STATUS_SERDES_LINK;

		if (bp->req_autoneg & AUTONEG_SPEED) {
			bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;

			if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
				bp->link_status |=
					LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;

			if (bp->autoneg & AUTONEG_PARALLEL)
				bp->link_status |=
					LINK_STATUS_PARALLEL_DETECTION_USED;
		}

		if (bp->flow_ctrl & FLOW_CTRL_TX)
		       bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;

		if (bp->flow_ctrl & FLOW_CTRL_RX)
		       bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;

	} else { /* link_down */
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		DP(NETIF_MSG_LINK, "phy link down\n");
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		bp->phy_link_up = 0;
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		bp->line_speed = 0;
		bp->duplex = DUPLEX_FULL;
		bp->flow_ctrl = 0;
	}

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	DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %d\n"
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	   DP_LEVEL "  line_speed %d  duplex %d  flow_ctrl 0x%x"
		    "  link_status 0x%x\n",
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	   gp_status, bp->phy_link_up, bp->line_speed, bp->duplex,
	   bp->flow_ctrl, bp->link_status);
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}

static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
{
	int port = bp->port;

	/* first reset all status
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	 * we assume only one line will be change at a time */
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	bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
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		       (NIG_STATUS_XGXS0_LINK10G |
			NIG_STATUS_XGXS0_LINK_STATUS |
			NIG_STATUS_SERDES0_LINK_STATUS));
	if (bp->phy_link_up) {
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		if (is_10g) {
			/* Disable the 10G link interrupt
			 * by writing 1 to the status register
			 */
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			DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
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			bnx2x_bits_en(bp,
				      NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
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				      NIG_STATUS_XGXS0_LINK10G);
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		} else if (bp->phy_flags & PHY_XGXS_FLAG) {
			/* Disable the link interrupt
			 * by writing 1 to the relevant lane
			 * in the status register
			 */
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			DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
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			bnx2x_bits_en(bp,
				      NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
				      ((1 << bp->ser_lane) <<
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				       NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
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		} else { /* SerDes */
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			DP(NETIF_MSG_LINK, "SerDes phy link up\n");
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			/* Disable the link interrupt
			 * by writing 1 to the status register
			 */
			bnx2x_bits_en(bp,
				      NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
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				      NIG_STATUS_SERDES0_LINK_STATUS);
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		}

	} else { /* link_down */
	}
}

static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
{
	u32 ext_phy_type;
	u32 ext_phy_addr;
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	u32 val1 = 0, val2;
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	u32 rx_sd, pcs_status;

	if (bp->phy_flags & PHY_XGXS_FLAG) {
		ext_phy_addr = ((bp->ext_phy_config &
				 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
				PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);

		ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
		switch (ext_phy_type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
			DP(NETIF_MSG_LINK, "XGXS Direct\n");
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			val1 = 1;
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			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
			DP(NETIF_MSG_LINK, "XGXS 8705\n");
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			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_WIS_DEVAD,
					  EXT_PHY_OPT_LASI_STATUS, &val1);
			DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);

			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_WIS_DEVAD,
					  EXT_PHY_OPT_LASI_STATUS, &val1);
			DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);

			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
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					  EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
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			DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
			val1 = (rx_sd & 0x1);
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			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
			DP(NETIF_MSG_LINK, "XGXS 8706\n");
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			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_OPT_LASI_STATUS, &val1);
			DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);

			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_OPT_LASI_STATUS, &val1);
			DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);

			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
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					  EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
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			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PCS_DEVAD,
					  EXT_PHY_OPT_PCS_STATUS, &pcs_status);
			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_AUTO_NEG_DEVAD,
					  EXT_PHY_OPT_AN_LINK_STATUS, &val2);

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			DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
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			   "  pcs_status 0x%x 1Gbps link_status 0x%x 0x%x\n",
			   rx_sd, pcs_status, val2, (val2 & (1<<1)));
			/* link is up if both bit 0 of pmd_rx_sd and
			 * bit 0 of pcs_status are set, or if the autoneg bit
			   1 is set
			 */
			val1 = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
			bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);

			/* clear the interrupt LASI status register */
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					       ext_phy_addr,
					       EXT_PHY_KR_PCS_DEVAD,
					       EXT_PHY_KR_LASI_STATUS, &val2);
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					       ext_phy_addr,
					       EXT_PHY_KR_PCS_DEVAD,
					       EXT_PHY_KR_LASI_STATUS, &val1);
			DP(NETIF_MSG_LINK, "KR LASI status 0x%x->0x%x\n",
			   val2, val1);
			/* Check the LASI */
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					       ext_phy_addr,
					       EXT_PHY_KR_PMA_PMD_DEVAD,
					       0x9003, &val2);
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					       ext_phy_addr,
					       EXT_PHY_KR_PMA_PMD_DEVAD,
					       0x9003, &val1);
			DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
			   val2, val1);
			/* Check the link status */
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					       ext_phy_addr,
					       EXT_PHY_KR_PCS_DEVAD,
					       EXT_PHY_KR_PCS_STATUS, &val2);
			DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
			/* Check the link status on 1.1.2 */
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					  ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_KR_STATUS, &val2);
			bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
					  ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_KR_STATUS, &val1);
			DP(NETIF_MSG_LINK,
			   "KR PMA status 0x%x->0x%x\n", val2, val1);
			val1 = ((val1 & 4) == 4);
			/* If 1G was requested assume the link is up */
			if (!(bp->req_autoneg & AUTONEG_SPEED) &&
			    (bp->req_line_speed == SPEED_1000))
				val1 = 1;
			bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
			break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_OPT_LASI_STATUS, &val2);
			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_OPT_LASI_STATUS, &val1);
			DP(NETIF_MSG_LINK,
			   "10G-base-T LASI status 0x%x->0x%x\n", val2, val1);
			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_KR_STATUS, &val2);
			bnx2x_mdio45_read(bp, ext_phy_addr,
					  EXT_PHY_OPT_PMA_PMD_DEVAD,
					  EXT_PHY_KR_STATUS, &val1);
			DP(NETIF_MSG_LINK,
			   "10G-base-T PMA status 0x%x->0x%x\n", val2, val1);
			val1 = ((val1 & 4) == 4);
			/* if link is up
			 * print the AN outcome of the SFX7101 PHY
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			 */
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			if (val1) {
				bnx2x_mdio45_read(bp, ext_phy_addr,
						  EXT_PHY_KR_AUTO_NEG_DEVAD,
						  0x21, &val2);
				DP(NETIF_MSG_LINK,
				   "SFX7101 AN status 0x%x->%s\n", val2,
				   (val2 & (1<<14)) ? "Master" : "Slave");
			}
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			break;

		default:
			DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
			   bp->ext_phy_config);
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			val1 = 0;
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