at91_mci.c 29.3 KB
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/*
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 *  linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
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 *
 *  Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
 *
 *  Copyright (C) 2006 Malcolm Noyes
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
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   This is the AT91 MCI driver that has been tested with both MMC cards
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   and SD-cards.  Boards that support write protect are now supported.
   The CCAT91SBC001 board does not support SD cards.

   The three entry points are at91_mci_request, at91_mci_set_ios
   and at91_mci_get_ro.

   SET IOS
     This configures the device to put it into the correct mode and clock speed
     required.

   MCI REQUEST
     MCI request processes the commands sent in the mmc_request structure. This
     can consist of a processing command and a stop command in the case of
     multiple block transfers.

     There are three main types of request, commands, reads and writes.

     Commands are straight forward. The command is submitted to the controller and
     the request function returns. When the controller generates an interrupt to indicate
     the command is finished, the response to the command are read and the mmc_request_done
     function called to end the request.

     Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
     controller to manage the transfers.

     A read is done from the controller directly to the scatterlist passed in from the request.
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     Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
     swapped in the scatterlist buffers.  AT91SAM926x are not affected by this bug.
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     The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY

     A write is slightly different in that the bytes to write are read from the scatterlist
     into a dma memory buffer (this is in case the source buffer should be read only). The
     entire write buffer is then done from this single dma memory buffer.

     The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY

   GET RO
     Gets the status of the write protect pin, if available.
*/

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
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#include <linux/atmel_pdc.h>
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#include <linux/mmc/host.h>

#include <asm/io.h>
#include <asm/irq.h>
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#include <asm/gpio.h>

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#include <asm/mach/mmc.h>
#include <asm/arch/board.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/at91_mci.h>
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#define DRIVER_NAME "at91_mci"

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#define FL_SENT_COMMAND	(1 << 0)
#define FL_SENT_STOP	(1 << 1)
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#define AT91_MCI_ERRORS	(AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE	\
		| AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE		\
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		| AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
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#define at91_mci_read(host, reg)	__raw_readl((host)->baseaddr + (reg))
#define at91_mci_write(host, reg, val)	__raw_writel((val), (host)->baseaddr + (reg))
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/*
 * Low level type for this driver
 */
struct at91mci_host
{
	struct mmc_host *mmc;
	struct mmc_command *cmd;
	struct mmc_request *request;

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	void __iomem *baseaddr;
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	int irq;
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	struct at91_mmc_data *board;
	int present;

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	struct clk *mci_clk;

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	/*
	 * Flag indicating when the command has been sent. This is used to
	 * work out whether or not to send the stop
	 */
	unsigned int flags;
	/* flag for current bus settings */
	u32 bus_mode;

	/* DMA buffer used for transmitting */
	unsigned int* buffer;
	dma_addr_t physical_address;
	unsigned int total_length;

	/* Latest in the scatterlist that has been enabled for transfer, but not freed */
	int in_use_index;

	/* Latest in the scatterlist that has been enabled for transfer */
	int transfer_index;
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	/* Timer for timeouts */
	struct timer_list timer;
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};

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/*
 * Reset the controller and restore most of the state
 */
static void at91_reset_host(struct at91mci_host *host)
{
	unsigned long flags;
	u32 mr;
	u32 sdcr;
	u32 dtor;
	u32 imr;

	local_irq_save(flags);
	imr = at91_mci_read(host, AT91_MCI_IMR);

	at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);

	/* save current state */
	mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
	sdcr = at91_mci_read(host, AT91_MCI_SDCR);
	dtor = at91_mci_read(host, AT91_MCI_DTOR);

	/* reset the controller */
	at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);

	/* restore state */
	at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
	at91_mci_write(host, AT91_MCI_MR, mr);
	at91_mci_write(host, AT91_MCI_SDCR, sdcr);
	at91_mci_write(host, AT91_MCI_DTOR, dtor);
	at91_mci_write(host, AT91_MCI_IER, imr);

	/* make sure sdio interrupts will fire */
	at91_mci_read(host, AT91_MCI_SR);

	local_irq_restore(flags);
}

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static void at91_timeout_timer(unsigned long data)
{
	struct at91mci_host *host;

	host = (struct at91mci_host *)data;

	if (host->request) {
		dev_err(host->mmc->parent, "Timeout waiting end of packet\n");

		if (host->cmd && host->cmd->data) {
			host->cmd->data->error = -ETIMEDOUT;
		} else {
			if (host->cmd)
				host->cmd->error = -ETIMEDOUT;
			else
				host->request->cmd->error = -ETIMEDOUT;
		}

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		at91_reset_host(host);
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		mmc_request_done(host->mmc, host->request);
	}
}

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/*
 * Copy from sg to a dma block - used for transfers
 */
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static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
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{
	unsigned int len, i, size;
	unsigned *dmabuf = host->buffer;

	size = host->total_length;
	len = data->sg_len;

	/*
	 * Just loop through all entries. Size might not
	 * be the entire list though so make sure that
	 * we do not transfer too much.
	 */
	for (i = 0; i < len; i++) {
		struct scatterlist *sg;
		int amount;
		unsigned int *sgbuffer;

		sg = &data->sg[i];

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		sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
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		amount = min(size, sg->length);
		size -= amount;

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		if (cpu_is_at91rm9200()) {	/* AT91RM9200 errata */
			int index;

			for (index = 0; index < (amount / 4); index++)
				*dmabuf++ = swab32(sgbuffer[index]);
		}
		else
			memcpy(dmabuf, sgbuffer, amount);
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		kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);

		if (size == 0)
			break;
	}

	/*
	 * Check that we didn't get a request to transfer
	 * more data than can fit into the SG list.
	 */
	BUG_ON(size != 0);
}

/*
 * Prepare a dma read
 */
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static void at91_mci_pre_dma_read(struct at91mci_host *host)
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{
	int i;
	struct scatterlist *sg;
	struct mmc_command *cmd;
	struct mmc_data *data;

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	pr_debug("pre dma read\n");
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	cmd = host->cmd;
	if (!cmd) {
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		pr_debug("no command\n");
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		return;
	}

	data = cmd->data;
	if (!data) {
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		pr_debug("no data\n");
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		return;
	}

	for (i = 0; i < 2; i++) {
		/* nothing left to transfer */
		if (host->transfer_index >= data->sg_len) {
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			pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index);
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			break;
		}

		/* Check to see if this needs filling */
		if (i == 0) {
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			if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) {
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				pr_debug("Transfer active in current\n");
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				continue;
			}
		}
		else {
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			if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) {
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				pr_debug("Transfer active in next\n");
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				continue;
			}
		}

		/* Setup the next transfer */
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		pr_debug("Using transfer index %d\n", host->transfer_index);
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		sg = &data->sg[host->transfer_index++];
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		pr_debug("sg = %p\n", sg);
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		sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE);
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		pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
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		if (i == 0) {
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			at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address);
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			at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4);
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		}
		else {
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			at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address);
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			at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4);
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		}
	}

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	pr_debug("pre dma read done\n");
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}

/*
 * Handle after a dma read
 */
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static void at91_mci_post_dma_read(struct at91mci_host *host)
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{
	struct mmc_command *cmd;
	struct mmc_data *data;

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	pr_debug("post dma read\n");
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	cmd = host->cmd;
	if (!cmd) {
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		pr_debug("no command\n");
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		return;
	}

	data = cmd->data;
	if (!data) {
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		pr_debug("no data\n");
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		return;
	}

	while (host->in_use_index < host->transfer_index) {
		struct scatterlist *sg;

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		pr_debug("finishing index %d\n", host->in_use_index);
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		sg = &data->sg[host->in_use_index++];

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		pr_debug("Unmapping page %08X\n", sg->dma_address);
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		dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);

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		if (cpu_is_at91rm9200()) {	/* AT91RM9200 errata */
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			unsigned int *buffer;
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			int index;
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			/* Swap the contents of the buffer */
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			buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
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			pr_debug("buffer = %p, length = %d\n", buffer, sg->length);

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			for (index = 0; index < (sg->length / 4); index++)
				buffer[index] = swab32(buffer[index]);
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			kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
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		}
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		flush_dcache_page(sg_page(sg));
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		data->bytes_xfered += sg->length;
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	}

	/* Is there another transfer to trigger? */
	if (host->transfer_index < data->sg_len)
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		at91_mci_pre_dma_read(host);
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	else {
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		at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
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		at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
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	}

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	pr_debug("post dma read done\n");
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}

/*
 * Handle transmitted data
 */
static void at91_mci_handle_transmitted(struct at91mci_host *host)
{
	struct mmc_command *cmd;
	struct mmc_data *data;

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	pr_debug("Handling the transmit\n");
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	/* Disable the transfer */
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	at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
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	/* Now wait for cmd ready */
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	at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
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	cmd = host->cmd;
	if (!cmd) return;

	data = cmd->data;
	if (!data) return;

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	if (cmd->data->blocks > 1) {
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		pr_debug("multiple write : wait for BLKE...\n");
		at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
	} else
		at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
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}

/*
 * Update bytes tranfered count during a write operation
 */
static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
{
	struct mmc_data *data;
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	/* always deal with the effective request (and not the current cmd) */

	if (host->request->cmd && host->request->cmd->error != 0)
		return;

	if (host->request->data) {
		data = host->request->data;
		if (data->flags & MMC_DATA_WRITE) {
			/* card is in IDLE mode now */
			pr_debug("-> bytes_xfered %d, total_length = %d\n",
				data->bytes_xfered, host->total_length);
			data->bytes_xfered = host->total_length;
		}
	}
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}

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/*Handle after command sent ready*/
static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
{
	if (!host->cmd)
		return 1;
	else if (!host->cmd->data) {
		if (host->flags & FL_SENT_STOP) {
			/*After multi block write, we must wait for NOTBUSY*/
			at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
		} else return 1;
	} else if (host->cmd->data->flags & MMC_DATA_WRITE) {
		/*After sendding multi-block-write command, start DMA transfer*/
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		at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
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		at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
	}

	/* command not completed, have to wait */
	return 0;
}


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/*
 * Enable the controller
 */
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static void at91_mci_enable(struct at91mci_host *host)
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{
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	unsigned int mr;

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	at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
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	at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
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	at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
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	mr = AT91_MCI_PDCMODE | 0x34a;

	if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
		mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;

	at91_mci_write(host, AT91_MCI_MR, mr);
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	/* use Slot A or B (only one at same time) */
	at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
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}

/*
 * Disable the controller
 */
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static void at91_mci_disable(struct at91mci_host *host)
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{
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	at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
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}

/*
 * Send a command
 */
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static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
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{
	unsigned int cmdr, mr;
	unsigned int block_length;
	struct mmc_data *data = cmd->data;

	unsigned int blocks;
	unsigned int ier = 0;

	host->cmd = cmd;

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	/* Needed for leaving busy state before CMD1 */
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	if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
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		pr_debug("Clearing timeout\n");
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		at91_mci_write(host, AT91_MCI_ARGR, 0);
		at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
		while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
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			/* spin */
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			pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
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		}
	}
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	cmdr = cmd->opcode;

	if (mmc_resp_type(cmd) == MMC_RSP_NONE)
		cmdr |= AT91_MCI_RSPTYP_NONE;
	else {
		/* if a response is expected then allow maximum response latancy */
		cmdr |= AT91_MCI_MAXLAT;
		/* set 136 bit response for R2, 48 bit response otherwise */
		if (mmc_resp_type(cmd) == MMC_RSP_R2)
			cmdr |= AT91_MCI_RSPTYP_136;
		else
			cmdr |= AT91_MCI_RSPTYP_48;
	}

	if (data) {
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		if ( cpu_is_at91rm9200() && (data->blksz & 0x3) ) {
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			pr_debug("Unsupported block size\n");
			cmd->error = -EINVAL;
			mmc_request_done(host->mmc, host->request);
			return;
		}

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		block_length = data->blksz;
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		blocks = data->blocks;

		/* always set data start - also set direction flag for read */
		if (data->flags & MMC_DATA_READ)
			cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
		else if (data->flags & MMC_DATA_WRITE)
			cmdr |= AT91_MCI_TRCMD_START;

		if (data->flags & MMC_DATA_STREAM)
			cmdr |= AT91_MCI_TRTYP_STREAM;
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		if (data->blocks > 1)
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			cmdr |= AT91_MCI_TRTYP_MULTIPLE;
	}
	else {
		block_length = 0;
		blocks = 0;
	}

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	if (host->flags & FL_SENT_STOP)
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		cmdr |= AT91_MCI_TRCMD_STOP;

	if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
		cmdr |= AT91_MCI_OPDCMD;

	/*
	 * Set the arguments and send the command
	 */
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	pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
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		cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
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	if (!data) {
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		at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
		at91_mci_write(host, ATMEL_PDC_RPR, 0);
		at91_mci_write(host, ATMEL_PDC_RCR, 0);
		at91_mci_write(host, ATMEL_PDC_RNPR, 0);
		at91_mci_write(host, ATMEL_PDC_RNCR, 0);
		at91_mci_write(host, ATMEL_PDC_TPR, 0);
		at91_mci_write(host, ATMEL_PDC_TCR, 0);
		at91_mci_write(host, ATMEL_PDC_TNPR, 0);
		at91_mci_write(host, ATMEL_PDC_TNCR, 0);
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		ier = AT91_MCI_CMDRDY;
	} else {
		/* zero block length and PDC mode */
		mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
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		mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
		mr |= (block_length << 16);
		mr |= AT91_MCI_PDCMODE;
		at91_mci_write(host, AT91_MCI_MR, mr);
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		if (!cpu_is_at91rm9200())
			at91_mci_write(host, AT91_MCI_BLKR,
				AT91_MCI_BLKR_BCNT(blocks) |
				AT91_MCI_BLKR_BLKLEN(block_length));

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		/*
		 * Disable the PDC controller
		 */
		at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
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		if (cmdr & AT91_MCI_TRCMD_START) {
			data->bytes_xfered = 0;
			host->transfer_index = 0;
			host->in_use_index = 0;
			if (cmdr & AT91_MCI_TRDIR) {
				/*
				 * Handle a read
				 */
				host->buffer = NULL;
				host->total_length = 0;

				at91_mci_pre_dma_read(host);
				ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
			}
			else {
				/*
				 * Handle a write
				 */
				host->total_length = block_length * blocks;
				host->buffer = dma_alloc_coherent(NULL,
						host->total_length,
						&host->physical_address, GFP_KERNEL);

				at91_mci_sg_to_dma(host, data);

				pr_debug("Transmitting %d bytes\n", host->total_length);

				at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
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				at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
						host->total_length : host->total_length / 4);

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				ier = AT91_MCI_CMDRDY;
			}
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		}
	}

	/*
	 * Send the command and then enable the PDC - not the other way round as
	 * the data sheet says
	 */

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	at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
	at91_mci_write(host, AT91_MCI_CMDR, cmdr);
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	if (cmdr & AT91_MCI_TRCMD_START) {
		if (cmdr & AT91_MCI_TRDIR)
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			at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
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	}

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	/* Enable selected interrupts */
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	at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
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}

/*
 * Process the next step in the request
 */
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static void at91_mci_process_next(struct at91mci_host *host)
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{
	if (!(host->flags & FL_SENT_COMMAND)) {
		host->flags |= FL_SENT_COMMAND;
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		at91_mci_send_command(host, host->request->cmd);
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	}
	else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
		host->flags |= FL_SENT_STOP;
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		at91_mci_send_command(host, host->request->stop);
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	} else {
		del_timer(&host->timer);
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		/* the at91rm9200 mci controller hangs after some transfers,
		 * and the workaround is to reset it after each transfer.
		 */
		if (cpu_is_at91rm9200())
			at91_reset_host(host);
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		mmc_request_done(host->mmc, host->request);
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	}
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}

/*
 * Handle a command that has been completed
 */
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static void at91_mci_completed_command(struct at91mci_host *host)
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{
	struct mmc_command *cmd = host->cmd;
	unsigned int status;

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	at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
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	cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
	cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
	cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
	cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
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	if (host->buffer) {
		dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
		host->buffer = NULL;
	}

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	status = at91_mci_read(host, AT91_MCI_SR);
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	pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
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		 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);

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	if (status & AT91_MCI_ERRORS) {
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		if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
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			cmd->error = 0;
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		}
		else {
			if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE))
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				cmd->error = -ETIMEDOUT;
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			else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE))
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				cmd->error = -EILSEQ;
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			else
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				cmd->error = -EIO;
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			pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n",
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				 cmd->error, cmd->opcode, cmd->retries);
		}
	}
	else
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		cmd->error = 0;
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	at91_mci_process_next(host);
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}

/*
 * Handle an MMC request
 */
static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct at91mci_host *host = mmc_priv(mmc);
	host->request = mrq;
	host->flags = 0;

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	mod_timer(&host->timer, jiffies +  HZ);

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	at91_mci_process_next(host);
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}

/*
 * Set the IOS
 */
static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	int clkdiv;
	struct at91mci_host *host = mmc_priv(mmc);
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	unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
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	host->bus_mode = ios->bus_mode;
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	if (ios->clock == 0) {
		/* Disable the MCI controller */
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		at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
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		clkdiv = 0;
	}
	else {
		/* Enable the MCI controller */
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		at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
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		if ((at91_master_clock % (ios->clock * 2)) == 0)
			clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
		else
			clkdiv = (at91_master_clock / ios->clock) / 2;

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		pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
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			at91_master_clock / (2 * (clkdiv + 1)));
	}
	if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
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		pr_debug("MMC: Setting controller bus width to 4\n");
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		at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
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	}
	else {
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		pr_debug("MMC: Setting controller bus width to 1\n");
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		at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
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	}

	/* Set the clock divider */
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	at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
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	/* maybe switch power to the card */
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	if (host->board->vcc_pin) {
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		switch (ios->power_mode) {
			case MMC_POWER_OFF:
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				gpio_set_value(host->board->vcc_pin, 0);
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				break;
			case MMC_POWER_UP:
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				gpio_set_value(host->board->vcc_pin, 1);
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				break;
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			case MMC_POWER_ON:
				break;
			default:
				WARN_ON(1);
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		}
	}
}

/*
 * Handle an interrupt
 */
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static irqreturn_t at91_mci_irq(int irq, void *devid)
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{
	struct at91mci_host *host = devid;
	int completed = 0;
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	unsigned int int_status, int_mask;
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	int_status = at91_mci_read(host, AT91_MCI_SR);
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	int_mask = at91_mci_read(host, AT91_MCI_IMR);
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	pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
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		int_status & int_mask);
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	int_status = int_status & int_mask;

	if (int_status & AT91_MCI_ERRORS) {
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		completed = 1;
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		if (int_status & AT91_MCI_UNRE)
			pr_debug("MMC: Underrun error\n");
		if (int_status & AT91_MCI_OVRE)
			pr_debug("MMC: Overrun error\n");
		if (int_status & AT91_MCI_DTOE)
			pr_debug("MMC: Data timeout\n");
		if (int_status & AT91_MCI_DCRCE)
			pr_debug("MMC: CRC error in data\n");
		if (int_status & AT91_MCI_RTOE)
			pr_debug("MMC: Response timeout\n");
		if (int_status & AT91_MCI_RENDE)
			pr_debug("MMC: Response end bit error\n");
		if (int_status & AT91_MCI_RCRCE)
			pr_debug("MMC: Response CRC error\n");
		if (int_status & AT91_MCI_RDIRE)
			pr_debug("MMC: Response direction error\n");
		if (int_status & AT91_MCI_RINDE)
			pr_debug("MMC: Response index error\n");
	} else {
		/* Only continue processing if no errors */
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		if (int_status & AT91_MCI_TXBUFE) {
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			pr_debug("TX buffer empty\n");
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			at91_mci_handle_transmitted(host);
		}

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		if (int_status & AT91_MCI_ENDRX) {
			pr_debug("ENDRX\n");
			at91_mci_post_dma_read(host);
		}

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		if (int_status & AT91_MCI_RXBUFF) {
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			pr_debug("RX buffer full\n");
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			at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
			at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
			completed = 1;
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		}

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		if (int_status & AT91_MCI_ENDTX)
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			pr_debug("Transmit has ended\n");
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		if (int_status & AT91_MCI_NOTBUSY) {
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			pr_debug("Card is ready\n");
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			at91_mci_update_bytes_xfered(host);
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			completed = 1;
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		}

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		if (int_status & AT91_MCI_DTIP)
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			pr_debug("Data transfer in progress\n");
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		if (int_status & AT91_MCI_BLKE) {
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			pr_debug("Block transfer has ended\n");
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			if (host->request->data && host->request->data->blocks > 1) {
				/* multi block write : complete multi write
				 * command and send stop */
				completed = 1;
			} else {
				at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
			}
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		}
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		if (int_status & AT91_MCI_TXRDY)
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			pr_debug("Ready to transmit\n");
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		if (int_status & AT91_MCI_RXRDY)
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			pr_debug("Ready to receive\n");
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		if (int_status & AT91_MCI_CMDRDY) {
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			pr_debug("Command ready\n");
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			completed = at91_mci_handle_cmdrdy(host);
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		}
	}

	if (completed) {
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		pr_debug("Completed command\n");
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		at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
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		at91_mci_completed_command(host);
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	} else
		at91_mci_write(host, AT91_MCI_IDR, int_status);
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	return IRQ_HANDLED;
}

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static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
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{
	struct at91mci_host *host = _host;
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	int present = !gpio_get_value(irq_to_gpio(irq));
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	/*
	 * we expect this irq on both insert and remove,
	 * and use a short delay to debounce.
	 */
	if (present != host->present) {
		host->present = present;
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		pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
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			present ? "insert" : "remove");
		if (!present) {
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			pr_debug("****** Resetting SD-card bus width ******\n");
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			at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
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		}
		mmc_detect_change(host->mmc, msecs_to_jiffies(100));
	}
	return IRQ_HANDLED;
}

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static int at91_mci_get_ro(struct mmc_host *mmc)
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{
	struct at91mci_host *host = mmc_priv(mmc);

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	if (host->board->wp_pin)
		return !!gpio_get_value(host->board->wp_pin);
	/*
	 * Board doesn't support read only detection; let the mmc core
	 * decide what to do.
	 */
	return -ENOSYS;
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}

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static const struct mmc_host_ops at91_mci_ops = {
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	.request	= at91_mci_request,
	.set_ios	= at91_mci_set_ios,
	.get_ro		= at91_mci_get_ro,
};

/*
 * Probe for the device
 */
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static int __init at91_mci_probe(struct platform_device *pdev)
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{
	struct mmc_host *mmc;
	struct at91mci_host *host;
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	struct resource *res;
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	int ret;

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	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENXIO;

	if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME))
		return -EBUSY;

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	mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
	if (!mmc) {
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		ret = -ENOMEM;
		dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
		goto fail6;
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	}

	mmc->ops = &at91_mci_ops;
	mmc->f_min = 375000;
	mmc->f_max = 25000000;
	mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;

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	mmc->max_blk_size = 4095;
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	mmc->max_blk_count = mmc->max_req_size;
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	host = mmc_priv(mmc);
	host->mmc = mmc;
	host->buffer = NULL;
	host->bus_mode = 0;
	host->board = pdev->dev.platform_data;
	if (host->board->wire4) {
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		if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
			mmc->caps |= MMC_CAP_4_BIT_DATA;
		else
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			dev_warn(&pdev->dev, "4 wire bus mode not supported"
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				" - using 1 wire\n");
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	}

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	/*
	 * Reserve GPIOs ... board init code makes sure these pins are set
	 * up as GPIOs with the right direction (input, except for vcc)
	 */
	if (host->board->det_pin) {
		ret = gpio_request(host->board->det_pin, "mmc_detect");
		if (ret < 0) {
			dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
			goto fail5;
		}
	}
	if (host->board->wp_pin) {
		ret = gpio_request(host->board->wp_pin, "mmc_wp");
		if (ret < 0) {
			dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
			goto fail4;
		}
	}
	if (host->board->vcc_pin) {
		ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
		if (ret < 0) {
			dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
			goto fail3;
		}
	}

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	/*
	 * Get Clock
	 */
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	host->mci_clk = clk_get(&pdev->dev, "mci_clk");
	if (IS_ERR(host->mci_clk)) {
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		ret = -ENODEV;
		dev_dbg(&pdev->dev, "no mci_clk?\n");
		goto fail2;
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	}

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	/*
	 * Map I/O region
	 */
	host->baseaddr = ioremap(res->start, res->end - res->start + 1);
	if (!host->baseaddr) {
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		ret = -ENOMEM;
		goto fail1;
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	}
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	/*
	 * Reset hardware
	 */
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	clk_enable(host->mci_clk);		/* Enable the peripheral clock */
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	at91_mci_disable(host);
	at91_mci_enable(host);

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	/*
	 * Allocate the MCI interrupt
	 */
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	host->irq = platform_get_irq(pdev, 0);
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	ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
			mmc_hostname(mmc), host);
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	if (ret) {
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		dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
		goto fail0;
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	}

	platform_set_drvdata(pdev, mmc);

	/*
	 * Add host to MMC layer
	 */
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	if (host->board->det_pin) {
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		host->present = !gpio_get_value(host->board->det_pin);
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	}
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	else
		host->present = -1;

	mmc_add_host(mmc);

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	setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);

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	/*
	 * monitor card insertion/removal if we can
	 */
	if (host->board->det_pin) {
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		ret = request_irq(gpio_to_irq(host->board->det_pin),
				at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
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		if (ret)
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			dev_warn(&pdev->dev, "request MMC detect irq failed\n");
		else
			device_init_wakeup(&pdev->dev, 1);
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	}

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	pr_debug("Added MCI driver\n");
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	return 0;
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fail0:
	clk_disable(host->mci_clk);
	iounmap(host->baseaddr);
fail1:
	clk_put(host->mci_clk);
fail2:
	if (host->board->vcc_pin)
		gpio_free(host->board->vcc_pin);
fail3:
	if (host->board->wp_pin)
		gpio_free(host->board->wp_pin);
fail4:
	if (host->board->det_pin)
		gpio_free(host->board->det_pin);
fail5:
	mmc_free_host(mmc);
fail6:
	release_mem_region(res->start, res->end - res->start + 1);
	dev_err(&pdev->dev, "probe failed, err %d\n", ret);
	return ret;
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}

/*
 * Remove a device
 */
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static int __exit at91_mci_remove(struct platform_device *pdev)
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{
	struct mmc_host *mmc = platform_get_drvdata(pdev);
	struct at91mci_host *host;
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	struct resource *res;
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	if (!mmc)
		return -1;

	host = mmc_priv(mmc);

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	if (host->board->det_pin) {
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		if (device_can_wakeup(&pdev->dev))
			free_irq(gpio_to_irq(host->board->det_pin), host);
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		device_init_wakeup(&pdev->dev, 0);
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		gpio_free(host->board->det_pin);
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	}

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	at91_mci_disable(host);
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	del_timer_sync(&host->timer);
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	mmc_remove_host(mmc);
	free_irq(host->irq, host);
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	clk_disable(host->mci_clk);			/* Disable the peripheral clock */
	clk_put(host->mci_clk);
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	if (host->board->vcc_pin)
		gpio_free(host->board->vcc_pin);
	if (host->board->wp_pin)
		gpio_free(host->board->wp_pin);

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	iounmap(host->baseaddr);
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(res->start, res->end - res->start + 1);
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	mmc_free_host(mmc);
	platform_set_drvdata(pdev, NULL);
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	pr_debug("MCI Removed\n");
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