dme1737.c 77.9 KB
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/*
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 * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x, SCH5027,
 *             and SCH5127 Super-I/O chips integrated hardware monitoring
 *             features.
 * Copyright (c) 2007, 2008, 2009, 2010 Juerg Haefliger <juergh@gmail.com>
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 *
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 * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access
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 * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus
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 * if a SCH311x or SCH5127 chip is found. Both types of chips have very
 * similar hardware monitoring capabilities but differ in the way they can be
 * accessed.
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/hwmon-vid.h>
#include <linux/err.h>
#include <linux/mutex.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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/* ISA device, if found */
static struct platform_device *pdev;

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/* Module load parameters */
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static bool force_start;
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module_param(force_start, bool, 0);
MODULE_PARM_DESC(force_start, "Force the chip to start monitoring inputs");

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static unsigned short force_id;
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");

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static bool probe_all_addr;
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module_param(probe_all_addr, bool, 0);
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MODULE_PARM_DESC(probe_all_addr,
		 "Include probing of non-standard LPC addresses");
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/* Addresses to scan */
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static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END};
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enum chips { dme1737, sch5027, sch311x, sch5127 };
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#define	DO_REPORT "Please report to the driver maintainer."

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/* ---------------------------------------------------------------------
 * Registers
 *
 * The sensors are defined as follows:
 *
 * Voltages                          Temperatures
 * --------                          ------------
 * in0   +5VTR (+5V stdby)           temp1   Remote diode 1
 * in1   Vccp  (proc core)           temp2   Internal temp
 * in2   VCC   (internal +3.3V)      temp3   Remote diode 2
 * in3   +5V
 * in4   +12V
 * in5   VTR   (+3.3V stby)
 * in6   Vbat
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 * in7   Vtrip (sch5127 only)
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 *
 * --------------------------------------------------------------------- */

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/* Voltages (in) numbered 0-7 (ix) */
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#define DME1737_REG_IN(ix)		((ix) < 5 ? 0x20 + (ix) : \
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					 (ix) < 7 ? 0x94 + (ix) : \
						    0x1f)
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#define DME1737_REG_IN_MIN(ix)		((ix) < 5 ? 0x44 + (ix) * 2 \
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						  : 0x91 + (ix) * 2)
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#define DME1737_REG_IN_MAX(ix)		((ix) < 5 ? 0x45 + (ix) * 2 \
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						  : 0x92 + (ix) * 2)

/* Temperatures (temp) numbered 0-2 (ix) */
#define DME1737_REG_TEMP(ix)		(0x25 + (ix))
#define DME1737_REG_TEMP_MIN(ix)	(0x4e + (ix) * 2)
#define DME1737_REG_TEMP_MAX(ix)	(0x4f + (ix) * 2)
#define DME1737_REG_TEMP_OFFSET(ix)	((ix) == 0 ? 0x1f \
						   : 0x1c + (ix))

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/*
 * Voltage and temperature LSBs
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 * The LSBs (4 bits each) are stored in 5 registers with the following layouts:
 *    IN_TEMP_LSB(0) = [in5, in6]
 *    IN_TEMP_LSB(1) = [temp3, temp1]
 *    IN_TEMP_LSB(2) = [in4, temp2]
 *    IN_TEMP_LSB(3) = [in3, in0]
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 *    IN_TEMP_LSB(4) = [in2, in1]
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 *    IN_TEMP_LSB(5) = [res, in7]
 */
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#define DME1737_REG_IN_TEMP_LSB(ix)	(0x84 + (ix))
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static const u8 DME1737_REG_IN_LSB[] = {3, 4, 4, 3, 2, 0, 0, 5};
static const u8 DME1737_REG_IN_LSB_SHL[] = {4, 4, 0, 0, 0, 0, 4, 4};
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static const u8 DME1737_REG_TEMP_LSB[] = {1, 2, 1};
static const u8 DME1737_REG_TEMP_LSB_SHL[] = {4, 4, 0};

/* Fans numbered 0-5 (ix) */
#define DME1737_REG_FAN(ix)		((ix) < 4 ? 0x28 + (ix) * 2 \
						  : 0xa1 + (ix) * 2)
#define DME1737_REG_FAN_MIN(ix)		((ix) < 4 ? 0x54 + (ix) * 2 \
						  : 0xa5 + (ix) * 2)
#define DME1737_REG_FAN_OPT(ix)		((ix) < 4 ? 0x90 + (ix) \
						  : 0xb2 + (ix))
#define DME1737_REG_FAN_MAX(ix)		(0xb4 + (ix)) /* only for fan[4-5] */

/* PWMs numbered 0-2, 4-5 (ix) */
#define DME1737_REG_PWM(ix)		((ix) < 3 ? 0x30 + (ix) \
						  : 0xa1 + (ix))
#define DME1737_REG_PWM_CONFIG(ix)	(0x5c + (ix)) /* only for pwm[0-2] */
#define DME1737_REG_PWM_MIN(ix)		(0x64 + (ix)) /* only for pwm[0-2] */
#define DME1737_REG_PWM_FREQ(ix)	((ix) < 3 ? 0x5f + (ix) \
						  : 0xa3 + (ix))
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/*
 * The layout of the ramp rate registers is different from the other pwm
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 * registers. The bits for the 3 PWMs are stored in 2 registers:
 *    PWM_RR(0) = [OFF3, OFF2,  OFF1,  RES,   RR1E, RR1-2, RR1-1, RR1-0]
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 *    PWM_RR(1) = [RR2E, RR2-2, RR2-1, RR2-0, RR3E, RR3-2, RR3-1, RR3-0]
 */
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#define DME1737_REG_PWM_RR(ix)		(0x62 + (ix)) /* only for pwm[0-2] */

/* Thermal zones 0-2 */
#define DME1737_REG_ZONE_LOW(ix)	(0x67 + (ix))
#define DME1737_REG_ZONE_ABS(ix)	(0x6a + (ix))
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/*
 * The layout of the hysteresis registers is different from the other zone
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 * registers. The bits for the 3 zones are stored in 2 registers:
 *    ZONE_HYST(0) = [H1-3,  H1-2,  H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
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 *    ZONE_HYST(1) = [H3-3,  H3-2,  H3-1, H3-0, RES,  RES,  RES,  RES]
 */
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#define DME1737_REG_ZONE_HYST(ix)	(0x6d + (ix))

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/*
 * Alarm registers and bit mapping
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 * The 3 8-bit alarm registers will be concatenated to a single 32-bit
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 * alarm value [0, ALARM3, ALARM2, ALARM1].
 */
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#define DME1737_REG_ALARM1		0x41
#define DME1737_REG_ALARM2		0x42
#define DME1737_REG_ALARM3		0x83
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static const u8 DME1737_BIT_ALARM_IN[] = {0, 1, 2, 3, 8, 16, 17, 18};
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static const u8 DME1737_BIT_ALARM_TEMP[] = {4, 5, 6};
static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23};

/* Miscellaneous registers */
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#define DME1737_REG_DEVICE		0x3d
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#define DME1737_REG_COMPANY		0x3e
#define DME1737_REG_VERSTEP		0x3f
#define DME1737_REG_CONFIG		0x40
#define DME1737_REG_CONFIG2		0x7f
#define DME1737_REG_VID			0x43
#define DME1737_REG_TACH_PWM		0x81

/* ---------------------------------------------------------------------
 * Misc defines
 * --------------------------------------------------------------------- */

/* Chip identification */
#define DME1737_COMPANY_SMSC	0x5c
#define DME1737_VERSTEP		0x88
#define DME1737_VERSTEP_MASK	0xf8
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#define SCH311X_DEVICE		0x8c
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#define SCH5027_VERSTEP		0x69
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#define SCH5127_DEVICE		0x8e

/* Device ID values (global configuration register index 0x20) */
#define DME1737_ID_1	0x77
#define DME1737_ID_2	0x78
#define SCH3112_ID	0x7c
#define SCH3114_ID	0x7d
#define SCH3116_ID	0x7f
#define SCH5027_ID	0x89
#define SCH5127_ID	0x86
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/* Length of ISA address segment */
#define DME1737_EXTENT	2
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/* chip-dependent features */
#define HAS_TEMP_OFFSET		(1 << 0)		/* bit 0 */
#define HAS_VID			(1 << 1)		/* bit 1 */
#define HAS_ZONE3		(1 << 2)		/* bit 2 */
#define HAS_ZONE_HYST		(1 << 3)		/* bit 3 */
#define HAS_PWM_MIN		(1 << 4)		/* bit 4 */
#define HAS_FAN(ix)		(1 << ((ix) + 5))	/* bits 5-10 */
#define HAS_PWM(ix)		(1 << ((ix) + 11))	/* bits 11-16 */
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#define HAS_IN7			(1 << 17)		/* bit 17 */
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/* ---------------------------------------------------------------------
 * Data structures and manipulation thereof
 * --------------------------------------------------------------------- */

struct dme1737_data {
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	struct i2c_client *client;	/* for I2C devices only */
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	struct device *hwmon_dev;
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	const char *name;
	unsigned int addr;		/* for ISA devices only */
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	struct mutex update_lock;
	int valid;			/* !=0 if following fields are valid */
	unsigned long last_update;	/* in jiffies */
	unsigned long last_vbat;	/* in jiffies */
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	enum chips type;
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	const int *in_nominal;		/* pointer to IN_NOMINAL array */
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	u8 vid;
	u8 pwm_rr_en;
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	u32 has_features;
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	/* Register values */
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	u16 in[8];
	u8  in_min[8];
	u8  in_max[8];
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	s16 temp[3];
	s8  temp_min[3];
	s8  temp_max[3];
	s8  temp_offset[3];
	u8  config;
	u8  config2;
	u8  vrm;
	u16 fan[6];
	u16 fan_min[6];
	u8  fan_max[2];
	u8  fan_opt[6];
	u8  pwm[6];
	u8  pwm_min[3];
	u8  pwm_config[3];
	u8  pwm_acz[3];
	u8  pwm_freq[6];
	u8  pwm_rr[2];
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	s8  zone_low[3];
	s8  zone_abs[3];
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	u8  zone_hyst[2];
	u32 alarms;
};

/* Nominal voltage values */
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static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300,
					 3300};
static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300,
					 3300};
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static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300,
					 3300};
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static const int IN_NOMINAL_SCH5127[] = {2500, 2250, 3300, 1125, 1125, 3300,
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					 3300, 1500};
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#define IN_NOMINAL(type)	((type) == sch311x ? IN_NOMINAL_SCH311x : \
				 (type) == sch5027 ? IN_NOMINAL_SCH5027 : \
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				 (type) == sch5127 ? IN_NOMINAL_SCH5127 : \
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				 IN_NOMINAL_DME1737)
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/*
 * Voltage input
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 * Voltage inputs have 16 bits resolution, limit values have 8 bits
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 * resolution.
 */
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static inline int IN_FROM_REG(int reg, int nominal, int res)
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{
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	return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2));
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}

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static inline int IN_TO_REG(long val, int nominal)
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{
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	return clamp_val((val * 192 + nominal / 2) / nominal, 0, 255);
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}

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/*
 * Temperature input
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 * The register values represent temperatures in 2's complement notation from
 * -127 degrees C to +127 degrees C. Temp inputs have 16 bits resolution, limit
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 * values have 8 bits resolution.
 */
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static inline int TEMP_FROM_REG(int reg, int res)
{
	return (reg * 1000) >> (res - 8);
}

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static inline int TEMP_TO_REG(long val)
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{
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	return clamp_val((val < 0 ? val - 500 : val + 500) / 1000, -128, 127);
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}

/* Temperature range */
static const int TEMP_RANGE[] = {2000, 2500, 3333, 4000, 5000, 6666, 8000,
				 10000, 13333, 16000, 20000, 26666, 32000,
				 40000, 53333, 80000};

static inline int TEMP_RANGE_FROM_REG(int reg)
{
	return TEMP_RANGE[(reg >> 4) & 0x0f];
}

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static int TEMP_RANGE_TO_REG(long val, int reg)
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{
	int i;

	for (i = 15; i > 0; i--) {
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		if (val > (TEMP_RANGE[i] + TEMP_RANGE[i - 1] + 1) / 2)
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			break;
	}

	return (reg & 0x0f) | (i << 4);
}

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/*
 * Temperature hysteresis
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 * Register layout:
 *    reg[0] = [H1-3, H1-2, H1-1, H1-0, H2-3, H2-2, H2-1, H2-0]
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 *    reg[1] = [H3-3, H3-2, H3-1, H3-0, xxxx, xxxx, xxxx, xxxx]
 */
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static inline int TEMP_HYST_FROM_REG(int reg, int ix)
{
	return (((ix == 1) ? reg : reg >> 4) & 0x0f) * 1000;
}

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static inline int TEMP_HYST_TO_REG(long val, int ix, int reg)
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{
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	int hyst = clamp_val((val + 500) / 1000, 0, 15);
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	return (ix == 1) ? (reg & 0xf0) | hyst : (reg & 0x0f) | (hyst << 4);
}

/* Fan input RPM */
static inline int FAN_FROM_REG(int reg, int tpc)
{
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	if (tpc)
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		return tpc * reg;
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	else
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		return (reg == 0 || reg == 0xffff) ? 0 : 90000 * 60 / reg;
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}

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static inline int FAN_TO_REG(long val, int tpc)
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{
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	if (tpc) {
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		return clamp_val(val / tpc, 0, 0xffff);
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	} else {
		return (val <= 0) ? 0xffff :
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			clamp_val(90000 * 60 / val, 0, 0xfffe);
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	}
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}

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/*
 * Fan TPC (tach pulse count)
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 * Converts a register value to a TPC multiplier or returns 0 if the tachometer
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 * is configured in legacy (non-tpc) mode
 */
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static inline int FAN_TPC_FROM_REG(int reg)
{
	return (reg & 0x20) ? 0 : 60 >> (reg & 0x03);
}

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/*
 * Fan type
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 * The type of a fan is expressed in number of pulses-per-revolution that it
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 * emits
 */
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static inline int FAN_TYPE_FROM_REG(int reg)
{
	int edge = (reg >> 1) & 0x03;

	return (edge > 0) ? 1 << (edge - 1) : 0;
}

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static inline int FAN_TYPE_TO_REG(long val, int reg)
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{
	int edge = (val == 4) ? 3 : val;

	return (reg & 0xf9) | (edge << 1);
}

/* Fan max RPM */
static const int FAN_MAX[] = {0x54, 0x38, 0x2a, 0x21, 0x1c, 0x18, 0x15, 0x12,
			      0x11, 0x0f, 0x0e};

static int FAN_MAX_FROM_REG(int reg)
{
	int i;

	for (i = 10; i > 0; i--) {
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		if (reg == FAN_MAX[i])
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			break;
	}

	return 1000 + i * 500;
}

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static int FAN_MAX_TO_REG(long val)
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{
	int i;

	for (i = 10; i > 0; i--) {
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		if (val > (1000 + (i - 1) * 500))
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			break;
	}

	return FAN_MAX[i];
}

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/*
 * PWM enable
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 * Register to enable mapping:
 * 000:  2  fan on zone 1 auto
 * 001:  2  fan on zone 2 auto
 * 010:  2  fan on zone 3 auto
 * 011:  0  fan full on
 * 100: -1  fan disabled
 * 101:  2  fan on hottest of zones 2,3 auto
 * 110:  2  fan on hottest of zones 1,2,3 auto
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 * 111:  1  fan in manual mode
 */
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static inline int PWM_EN_FROM_REG(int reg)
{
	static const int en[] = {2, 2, 2, 0, -1, 2, 2, 1};

	return en[(reg >> 5) & 0x07];
}

static inline int PWM_EN_TO_REG(int val, int reg)
{
	int en = (val == 1) ? 7 : 3;

	return (reg & 0x1f) | ((en & 0x07) << 5);
}

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/*
 * PWM auto channels zone
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 * Register to auto channels zone mapping (ACZ is a bitfield with bit x
 * corresponding to zone x+1):
 * 000: 001  fan on zone 1 auto
 * 001: 010  fan on zone 2 auto
 * 010: 100  fan on zone 3 auto
 * 011: 000  fan full on
 * 100: 000  fan disabled
 * 101: 110  fan on hottest of zones 2,3 auto
 * 110: 111  fan on hottest of zones 1,2,3 auto
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 * 111: 000  fan in manual mode
 */
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static inline int PWM_ACZ_FROM_REG(int reg)
{
	static const int acz[] = {1, 2, 4, 0, 0, 6, 7, 0};

	return acz[(reg >> 5) & 0x07];
}

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static inline int PWM_ACZ_TO_REG(long val, int reg)
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{
	int acz = (val == 4) ? 2 : val - 1;

	return (reg & 0x1f) | ((acz & 0x07) << 5);
}

/* PWM frequency */
static const int PWM_FREQ[] = {11, 15, 22, 29, 35, 44, 59, 88,
			       15000, 20000, 30000, 25000, 0, 0, 0, 0};

static inline int PWM_FREQ_FROM_REG(int reg)
{
	return PWM_FREQ[reg & 0x0f];
}

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static int PWM_FREQ_TO_REG(long val, int reg)
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{
	int i;

	/* the first two cases are special - stupid chip design! */
	if (val > 27500) {
		i = 10;
	} else if (val > 22500) {
		i = 11;
	} else {
		for (i = 9; i > 0; i--) {
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			if (val > (PWM_FREQ[i] + PWM_FREQ[i - 1] + 1) / 2)
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				break;
		}
	}

	return (reg & 0xf0) | i;
}

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/*
 * PWM ramp rate
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 * Register layout:
 *    reg[0] = [OFF3,  OFF2,  OFF1,  RES,   RR1-E, RR1-2, RR1-1, RR1-0]
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 *    reg[1] = [RR2-E, RR2-2, RR2-1, RR2-0, RR3-E, RR3-2, RR3-1, RR3-0]
 */
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static const u8 PWM_RR[] = {206, 104, 69, 41, 26, 18, 10, 5};

static inline int PWM_RR_FROM_REG(int reg, int ix)
{
	int rr = (ix == 1) ? reg >> 4 : reg;

	return (rr & 0x08) ? PWM_RR[rr & 0x07] : 0;
}

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static int PWM_RR_TO_REG(long val, int ix, int reg)
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{
	int i;

	for (i = 0; i < 7; i++) {
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		if (val > (PWM_RR[i] + PWM_RR[i + 1] + 1) / 2)
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			break;
	}

	return (ix == 1) ? (reg & 0x8f) | (i << 4) : (reg & 0xf8) | i;
}

/* PWM ramp rate enable */
static inline int PWM_RR_EN_FROM_REG(int reg, int ix)
{
	return PWM_RR_FROM_REG(reg, ix) ? 1 : 0;
}

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static inline int PWM_RR_EN_TO_REG(long val, int ix, int reg)
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{
	int en = (ix == 1) ? 0x80 : 0x08;

	return val ? reg | en : reg & ~en;
}

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/*
 * PWM min/off
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 * The PWM min/off bits are part of the PMW ramp rate register 0 (see above for
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 * the register layout).
 */
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static inline int PWM_OFF_FROM_REG(int reg, int ix)
{
	return (reg >> (ix + 5)) & 0x01;
}

static inline int PWM_OFF_TO_REG(int val, int ix, int reg)
{
	return (reg & ~(1 << (ix + 5))) | ((val & 0x01) << (ix + 5));
}

/* ---------------------------------------------------------------------
 * Device I/O access
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 *
 * ISA access is performed through an index/data register pair and needs to
 * be protected by a mutex during runtime (not required for initialization).
 * We use data->update_lock for this and need to ensure that we acquire it
 * before calling dme1737_read or dme1737_write.
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 * --------------------------------------------------------------------- */

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static u8 dme1737_read(const struct dme1737_data *data, u8 reg)
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{
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	struct i2c_client *client = data->client;
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	s32 val;
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	if (client) { /* I2C device */
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		val = i2c_smbus_read_byte_data(client, reg);

		if (val < 0) {
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			dev_warn(&client->dev,
				 "Read from register 0x%02x failed! %s\n",
				 reg, DO_REPORT);
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		}
	} else { /* ISA device */
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		outb(reg, data->addr);
		val = inb(data->addr + 1);
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	}

	return val;
}

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static s32 dme1737_write(const struct dme1737_data *data, u8 reg, u8 val)
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{
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	struct i2c_client *client = data->client;
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	s32 res = 0;

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	if (client) { /* I2C device */
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		res = i2c_smbus_write_byte_data(client, reg, val);
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		if (res < 0) {
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			dev_warn(&client->dev,
				 "Write to register 0x%02x failed! %s\n",
				 reg, DO_REPORT);
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		}
	} else { /* ISA device */
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		outb(reg, data->addr);
		outb(val, data->addr + 1);
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	}

	return res;
}

static struct dme1737_data *dme1737_update_device(struct device *dev)
{
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	struct dme1737_data *data = dev_get_drvdata(dev);
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	int ix;
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	u8 lsb[6];
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	mutex_lock(&data->update_lock);

	/* Enable a Vbat monitoring cycle every 10 mins */
	if (time_after(jiffies, data->last_vbat + 600 * HZ) || !data->valid) {
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		dme1737_write(data, DME1737_REG_CONFIG, dme1737_read(data,
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						DME1737_REG_CONFIG) | 0x10);
		data->last_vbat = jiffies;
	}

	/* Sample register contents every 1 sec */
	if (time_after(jiffies, data->last_update + HZ) || !data->valid) {
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		if (data->has_features & HAS_VID) {
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			data->vid = dme1737_read(data, DME1737_REG_VID) &
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				0x3f;
		}
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		/* In (voltage) registers */
		for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
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			/*
			 * Voltage inputs are stored as 16 bit values even
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			 * though they have only 12 bits resolution. This is
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			 * to make it consistent with the temp inputs.
			 */
			if (ix == 7 && !(data->has_features & HAS_IN7))
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				continue;
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			data->in[ix] = dme1737_read(data,
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					DME1737_REG_IN(ix)) << 8;
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			data->in_min[ix] = dme1737_read(data,
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					DME1737_REG_IN_MIN(ix));
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			data->in_max[ix] = dme1737_read(data,
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					DME1737_REG_IN_MAX(ix));
		}

		/* Temp registers */
		for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
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			/*
			 * Temp inputs are stored as 16 bit values even
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			 * though they have only 12 bits resolution. This is
			 * to take advantage of implicit conversions between
			 * register values (2's complement) and temp values
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			 * (signed decimal).
			 */
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			data->temp[ix] = dme1737_read(data,
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					DME1737_REG_TEMP(ix)) << 8;
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			data->temp_min[ix] = dme1737_read(data,
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					DME1737_REG_TEMP_MIN(ix));
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			data->temp_max[ix] = dme1737_read(data,
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					DME1737_REG_TEMP_MAX(ix));
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			if (data->has_features & HAS_TEMP_OFFSET) {
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				data->temp_offset[ix] = dme1737_read(data,
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						DME1737_REG_TEMP_OFFSET(ix));
			}
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		}

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		/*
		 * In and temp LSB registers
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		 * The LSBs are latched when the MSBs are read, so the order in
		 * which the registers are read (MSB first, then LSB) is
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		 * important!
		 */
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		for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) {
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			if (ix == 5 && !(data->has_features & HAS_IN7))
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				continue;
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			lsb[ix] = dme1737_read(data,
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					DME1737_REG_IN_TEMP_LSB(ix));
		}
		for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) {
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			if (ix == 7 && !(data->has_features & HAS_IN7))
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				continue;
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			data->in[ix] |= (lsb[DME1737_REG_IN_LSB[ix]] <<
					DME1737_REG_IN_LSB_SHL[ix]) & 0xf0;
		}
		for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) {
			data->temp[ix] |= (lsb[DME1737_REG_TEMP_LSB[ix]] <<
					DME1737_REG_TEMP_LSB_SHL[ix]) & 0xf0;
		}

		/* Fan registers */
		for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) {
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			/*
			 * Skip reading registers if optional fans are not
			 * present
			 */
			if (!(data->has_features & HAS_FAN(ix)))
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				continue;
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			data->fan[ix] = dme1737_read(data,
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					DME1737_REG_FAN(ix));
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			data->fan[ix] |= dme1737_read(data,
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					DME1737_REG_FAN(ix) + 1) << 8;
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			data->fan_min[ix] = dme1737_read(data,
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					DME1737_REG_FAN_MIN(ix));
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			data->fan_min[ix] |= dme1737_read(data,
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					DME1737_REG_FAN_MIN(ix) + 1) << 8;
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			data->fan_opt[ix] = dme1737_read(data,
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					DME1737_REG_FAN_OPT(ix));
			/* fan_max exists only for fan[5-6] */
			if (ix > 3) {
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				data->fan_max[ix - 4] = dme1737_read(data,
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					DME1737_REG_FAN_MAX(ix));
			}
		}

		/* PWM registers */
		for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) {
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			/*
			 * Skip reading registers if optional PWMs are not
			 * present
			 */
			if (!(data->has_features & HAS_PWM(ix)))
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				continue;
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			data->pwm[ix] = dme1737_read(data,
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					DME1737_REG_PWM(ix));
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			data->pwm_freq[ix] = dme1737_read(data,
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					DME1737_REG_PWM_FREQ(ix));
			/* pwm_config and pwm_min exist only for pwm[1-3] */
			if (ix < 3) {
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				data->pwm_config[ix] = dme1737_read(data,
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						DME1737_REG_PWM_CONFIG(ix));
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				data->pwm_min[ix] = dme1737_read(data,
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						DME1737_REG_PWM_MIN(ix));
			}
		}
		for (ix = 0; ix < ARRAY_SIZE(data->pwm_rr); ix++) {
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			data->pwm_rr[ix] = dme1737_read(data,
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						DME1737_REG_PWM_RR(ix));
		}

		/* Thermal zone registers */
		for (ix = 0; ix < ARRAY_SIZE(data->zone_low); ix++) {
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			/* Skip reading registers if zone3 is not present */
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			if ((ix == 2) && !(data->has_features & HAS_ZONE3))
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				continue;
			/* sch5127 zone2 registers are special */
			if ((ix == 1) && (data->type == sch5127)) {
				data->zone_low[1] = dme1737_read(data,
						DME1737_REG_ZONE_LOW(2));
				data->zone_abs[1] = dme1737_read(data,
						DME1737_REG_ZONE_ABS(2));
			} else {
				data->zone_low[ix] = dme1737_read(data,
						DME1737_REG_ZONE_LOW(ix));
				data->zone_abs[ix] = dme1737_read(data,
						DME1737_REG_ZONE_ABS(ix));
			}
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		}
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		if (data->has_features & HAS_ZONE_HYST) {
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			for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) {
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				data->zone_hyst[ix] = dme1737_read(data,
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						DME1737_REG_ZONE_HYST(ix));
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			}
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		}

		/* Alarm registers */
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		data->alarms = dme1737_read(data,
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						DME1737_REG_ALARM1);
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		/*
		 * Bit 7 tells us if the other alarm registers are non-zero and
		 * therefore also need to be read
		 */
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		if (data->alarms & 0x80) {
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			data->alarms |= dme1737_read(data,
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						DME1737_REG_ALARM2) << 8;
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			data->alarms |= dme1737_read(data,
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						DME1737_REG_ALARM3) << 16;
		}

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		/*
		 * The ISA chips require explicit clearing of alarm bits.
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		 * Don't worry, an alarm will come back if the condition
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		 * that causes it still exists
		 */
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		if (!data->client) {
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			if (data->alarms & 0xff0000)
				dme1737_write(data, DME1737_REG_ALARM3, 0xff);
			if (data->alarms & 0xff00)
				dme1737_write(data, DME1737_REG_ALARM2, 0xff);
			if (data->alarms & 0xff)
				dme1737_write(data, DME1737_REG_ALARM1, 0xff);
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		}

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		data->last_update = jiffies;
		data->valid = 1;
	}

	mutex_unlock(&data->update_lock);

	return data;
}

/* ---------------------------------------------------------------------
 * Voltage sysfs attributes
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 * ix = [0-7]
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 * --------------------------------------------------------------------- */

#define SYS_IN_INPUT	0
#define SYS_IN_MIN	1
#define SYS_IN_MAX	2
#define SYS_IN_ALARM	3

static ssize_t show_in(struct device *dev, struct device_attribute *attr,
		       char *buf)
{
	struct dme1737_data *data = dme1737_update_device(dev);
	struct sensor_device_attribute_2
		*sensor_attr_2 = to_sensor_dev_attr_2(attr);
	int ix = sensor_attr_2->index;
	int fn = sensor_attr_2->nr;
	int res;

	switch (fn) {
	case SYS_IN_INPUT:
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		res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16);
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		break;
	case SYS_IN_MIN:
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		res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8);
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		break;
	case SYS_IN_MAX:
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		res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8);
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		break;
	case SYS_IN_ALARM:
		res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01;
		break;
	default:
		res = 0;
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		dev_dbg(dev, "Unknown function %d.\n", fn);
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	}

	return sprintf(buf, "%d\n", res);
}

static ssize_t set_in(struct device *dev, struct device_attribute *attr,
		      const char *buf, size_t count)
{
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	struct dme1737_data *data = dev_get_drvdata(dev);
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	struct sensor_device_attribute_2
		*sensor_attr_2 = to_sensor_dev_attr_2(attr);
	int ix = sensor_attr_2->index;
	int fn = sensor_attr_2->nr;
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	long val;
	int err;

	err = kstrtol(buf, 10, &val);
	if (err)
		return err;
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	mutex_lock(&data->update_lock);
	switch (fn) {
	case SYS_IN_MIN:
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		data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]);
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		dme1737_write(data, DME1737_REG_IN_MIN(ix),
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			      data->in_min[ix]);
		break;
	case SYS_IN_MAX:
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		data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]);
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		dme1737_write(data, DME1737_REG_IN_MAX(ix),
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			      data->in_max[ix]);
		break;
	default:
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		dev_dbg(dev, "Unknown function %d.\n", fn);
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	}
	mutex_unlock(&data->update_lock);

	return count;
}

/* ---------------------------------------------------------------------
 * Temperature sysfs attributes
 * ix = [0-2]
 * --------------------------------------------------------------------- */

#define SYS_TEMP_INPUT			0
#define SYS_TEMP_MIN			1
#define SYS_TEMP_MAX			2
#define SYS_TEMP_OFFSET			3
#define SYS_TEMP_ALARM			4
#define SYS_TEMP_FAULT			5

static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
			 char *buf)
{
	struct dme1737_data *data = dme1737_update_device(dev);
	struct sensor_device_attribute_2
		*sensor_attr_2 = to_sensor_dev_attr_2(attr);
	int ix = sensor_attr_2->index;
	int fn = sensor_attr_2->nr;
	int res;

	switch (fn) {
	case SYS_TEMP_INPUT:
		res = TEMP_FROM_REG(data->temp[ix], 16);
		break;
	case SYS_TEMP_MIN:
		res = TEMP_FROM_REG(data->temp_min[ix], 8);
		break;
	case SYS_TEMP_MAX:
		res = TEMP_FROM_REG(data->temp_max[ix], 8);
		break;
	case SYS_TEMP_OFFSET:
		res = TEMP_FROM_REG(data->temp_offset[ix], 8);
		break;
	case SYS_TEMP_ALARM:
		res = (data->alarms >> DME1737_BIT_ALARM_TEMP[ix]) & 0x01;
		break;
	case SYS_TEMP_FAULT:
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		res = (((u16)data->temp[ix] & 0xff00) == 0x8000);
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		break;
	default:
		res = 0;
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		dev_dbg(dev, "Unknown function %d.\n", fn);
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	}

	return sprintf(buf, "%d\n", res);
}

static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
			const char *buf, size_t count)
{
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	struct dme1737_data *data = dev_get_drvdata(dev);
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	struct sensor_device_attribute_2
		*sensor_attr_2 = to_sensor_dev_attr_2(attr);
	int ix = sensor_attr_2->index;
	int fn = sensor_attr_2->nr;
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	long val;
	int err;

	err = kstrtol(buf, 10, &val);
	if (err)
		return err;
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	mutex_lock(&data->update_lock);
	switch (fn) {
	case SYS_TEMP_MIN:
		data->temp_min[ix] = TEMP_TO_REG(val);
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		dme1737_write(data, DME1737_REG_TEMP_MIN(ix),
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			      data->temp_min[ix]);
		break;
	case SYS_TEMP_MAX:
		data->temp_max[ix] = TEMP_TO_REG(val);
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		dme1737_write(data, DME1737_REG_TEMP_MAX(ix),
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			      data->temp_max[ix]);
		break;
	case SYS_TEMP_OFFSET:
		data->temp_offset[ix] = TEMP_TO_REG(val);
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		dme1737_write(data, DME1737_REG_TEMP_OFFSET(ix),
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			      data->temp_offset[ix]);
		break;
	default:
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		dev_dbg(dev, "Unknown function %d.\n", fn);
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	}
	mutex_unlock(&data->update_lock);

	return count;
}

/* ---------------------------------------------------------------------
 * Zone sysfs attributes
 * ix = [0-2]
 * --------------------------------------------------------------------- */

#define SYS_ZONE_AUTO_CHANNELS_TEMP	0
#define SYS_ZONE_AUTO_POINT1_TEMP_HYST	1
#define SYS_ZONE_AUTO_POINT1_TEMP	2
#define SYS_ZONE_AUTO_POINT2_TEMP	3
#define SYS_ZONE_AUTO_POINT3_TEMP	4

static ssize_t show_zone(struct device *dev, struct device_attribute *attr,
			 char *buf)
{
	struct dme1737_data *data = dme1737_update_device(dev);
	struct sensor_device_attribute_2
		*sensor_attr_2 = to_sensor_dev_attr_2(attr);
	int ix = sensor_attr_2->index;
	int fn = sensor_attr_2->nr;
	int res;

	switch (fn) {
	case SYS_ZONE_AUTO_CHANNELS_TEMP:
		/* check config2 for non-standard temp-to-zone mapping */
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		if ((ix == 1) && (data->config2 & 0x02))
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			res = 4;
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		else
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			res = 1 << ix;
		break;
	case SYS_ZONE_AUTO_POINT1_TEMP_HYST:
		res = TEMP_FROM_REG(data->zone_low[ix], 8) -
		      TEMP_HYST_FROM_REG(data->zone_hyst[ix == 2], ix);
		break;
	case SYS_ZONE_AUTO_POINT1_TEMP:
		res = TEMP_FROM_REG(data->zone_low[ix], 8);
		break;
	case SYS_ZONE_AUTO_POINT2_TEMP:
		/* pwm_freq holds the temp range bits in the upper nibble */
		res = TEMP_FROM_REG(data->zone_low[ix], 8) +
		      TEMP_RANGE_FROM_REG(data->pwm_freq[ix]);
		break;
	case SYS_ZONE_AUTO_POINT3_TEMP:
		res = TEMP_FROM_REG(data->zone_abs[ix], 8);
		break;
	default:
		res = 0;
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		dev_dbg(dev, "Unknown function %d.\n", fn);
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	}

	return sprintf(buf, "%d\n", res);
}

static ssize_t set_zone(struct device *dev, struct device_attribute *attr,
			const char *buf, size_t count)
{
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	struct dme1737_data *data = dev_get_drvdata(