head_64.S 20.6 KB
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/*
 *  PowerPC version
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
 *  Adapted for Power Macintosh by Paul Mackerras.
 *  Low-level exception handlers and MMU support
 *  rewritten by Paul Mackerras.
 *    Copyright (C) 1996 Paul Mackerras.
 *
 *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
 *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
 *
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 *  This file contains the entry point for the 64-bit kernel along
 *  with some early initialization code common to all 64-bit powerpc
 *  variants.
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 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/threads.h>
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#include <asm/reg.h>
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#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/bug.h>
#include <asm/cputable.h>
#include <asm/setup.h>
#include <asm/hvcall.h>
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#include <asm/thread_info.h>
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#include <asm/firmware.h>
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#include <asm/page_64.h>
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#include <asm/irqflags.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/ptrace.h>
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#include <asm/hw_irq.h>
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/* The physical memory is laid out such that the secondary processor
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 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
 * using the layout described in exceptions-64s.S
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 */

/*
 * Entering into this code we make the following assumptions:
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 *
 *  For pSeries or server processors:
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 *   1. The MMU is off & open firmware is running in real mode.
 *   2. The kernel is entered at __start
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 * -or- For OPAL entry:
 *   1. The MMU is off, processor in HV mode, primary CPU enters at 0
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 *      with device-tree in gpr3. We also get OPAL base in r8 and
 *	entry in r9 for debugging purposes
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 *   2. Secondary processors enter at 0x60 with PIR in gpr3
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 *
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 *  For Book3E processors:
 *   1. The MMU is on running in AS0 in a state defined in ePAPR
 *   2. The kernel is entered at __start
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 */

	.text
	.globl  _stext
_stext:
_GLOBAL(__start)
	/* NOP this out unconditionally */
BEGIN_FTR_SECTION
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	b	.__start_initialization_multiplatform
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END_FTR_SECTION(0, 1)

	/* Catch branch to 0 in real mode */
	trap

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	/* Secondary processors spin on this value until it becomes nonzero.
	 * When it does it contains the real address of the descriptor
	 * of the function that the cpu should jump to to continue
	 * initialization.
	 */
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	.globl  __secondary_hold_spinloop
__secondary_hold_spinloop:
	.llong	0x0

	/* Secondary processors write this value with their cpu # */
	/* after they enter the spin loop immediately below.	  */
	.globl	__secondary_hold_acknowledge
__secondary_hold_acknowledge:
	.llong	0x0

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#ifdef CONFIG_RELOCATABLE
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	/* This flag is set to 1 by a loader if the kernel should run
	 * at the loaded address instead of the linked address.  This
	 * is used by kexec-tools to keep the the kdump kernel in the
	 * crash_kernel region.  The loader is responsible for
	 * observing the alignment requirement.
	 */
	/* Do not move this variable as kexec-tools knows about it. */
	. = 0x5c
	.globl	__run_at_load
__run_at_load:
	.long	0x72756e30	/* "run0" -- relocate to 0 by default */
#endif

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	. = 0x60
/*
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 * The following code is used to hold secondary processors
 * in a spin loop after they have entered the kernel, but
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 * before the bulk of the kernel has been relocated.  This code
 * is relocated to physical address 0x60 before prom_init is run.
 * All of it must fit below the first exception vector at 0x100.
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 * Use .globl here not _GLOBAL because we want __secondary_hold
 * to be the actual text address, not a descriptor.
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 */
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	.globl	__secondary_hold
__secondary_hold:
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#ifndef CONFIG_PPC_BOOK3E
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	mfmsr	r24
	ori	r24,r24,MSR_RI
	mtmsrd	r24			/* RI on */
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#endif
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	/* Grab our physical cpu number */
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	mr	r24,r3
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	/* stash r4 for book3e */
	mr	r25,r4
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	/* Tell the master cpu we're here */
	/* Relocation is off & we are located at an address less */
	/* than 0x100, so only need to grab low order offset.    */
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	std	r24,__secondary_hold_acknowledge-_stext(0)
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	sync

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	li	r26,0
#ifdef CONFIG_PPC_BOOK3E
	tovirt(r26,r26)
#endif
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	/* All secondary cpus wait here until told to start. */
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100:	ld	r4,__secondary_hold_spinloop-_stext(r26)
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	cmpdi	0,r4,0
	beq	100b
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
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#ifdef CONFIG_PPC_BOOK3E
	tovirt(r4,r4)
#endif
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	ld	r4,0(r4)		/* deref function descriptor */
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	mtctr	r4
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	mr	r3,r24
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	/*
	 * it may be the case that other platforms have r4 right to
	 * begin with, this gives us some safety in case it is not
	 */
#ifdef CONFIG_PPC_BOOK3E
	mr	r4,r25
#else
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	li	r4,0
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#endif
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	/* Make sure that patched code is visible */
	isync
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	bctr
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#else
	BUG_OPCODE
#endif

/* This value is used to mark exception frames on the stack. */
	.section ".toc","aw"
exception_marker:
	.tc	ID_72656773_68657265[TC],0x7265677368657265
	.text

/*
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 * On server, we include the exception vectors code here as it
 * relies on absolute addressing which is only possible within
 * this compilation unit
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 */
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#ifdef CONFIG_PPC_BOOK3S
#include "exceptions-64s.S"
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#endif
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_GLOBAL(generic_secondary_thread_init)
	mr	r24,r3

	/* turn on 64-bit mode */
	bl	.enable_64b_mode

	/* get a valid TOC pointer, wherever we're mapped at */
	bl	.relative_toc
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	tovirt(r2,r2)
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#ifdef CONFIG_PPC_BOOK3E
	/* Book3E initialization */
	mr	r3,r24
	bl	.book3e_secondary_thread_init
#endif
	b	generic_secondary_common_init
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/*
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 * On pSeries and most other platforms, secondary processors spin
 * in the following code.
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 * At entry, r3 = this processor's number (physical cpu id)
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 *
 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
 * this core already exists (setup via some other mechanism such
 * as SCOM before entry).
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 */
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_GLOBAL(generic_secondary_smp_init)
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	mr	r24,r3
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	mr	r25,r4

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	/* turn on 64-bit mode */
	bl	.enable_64b_mode

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	/* get a valid TOC pointer, wherever we're mapped at */
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	bl	.relative_toc
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	tovirt(r2,r2)
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#ifdef CONFIG_PPC_BOOK3E
	/* Book3E initialization */
	mr	r3,r24
	mr	r4,r25
	bl	.book3e_secondary_core_init
#endif

generic_secondary_common_init:
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	/* Set up a paca value for this processor. Since we have the
	 * physical cpu id in r24, we need to search the pacas to find
	 * which logical id maps to our physical one.
	 */
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	LOAD_REG_ADDR(r13, paca)	/* Load paca pointer		 */
	ld	r13,0(r13)		/* Get base vaddr of paca array	 */
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#ifndef CONFIG_SMP
	addi	r13,r13,PACA_SIZE	/* know r13 if used accidentally */
	b	.kexec_wait		/* wait for next kernel if !SMP	 */
#else
	LOAD_REG_ADDR(r7, nr_cpu_ids)	/* Load nr_cpu_ids address       */
	lwz	r7,0(r7)		/* also the max paca allocated 	 */
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	li	r5,0			/* logical cpu id                */
1:	lhz	r6,PACAHWCPUID(r13)	/* Load HW procid from paca      */
	cmpw	r6,r24			/* Compare to our id             */
	beq	2f
	addi	r13,r13,PACA_SIZE	/* Loop to next PACA on miss     */
	addi	r5,r5,1
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	cmpw	r5,r7			/* Check if more pacas exist     */
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	blt	1b

	mr	r3,r24			/* not found, copy phys to r3	 */
	b	.kexec_wait		/* next kernel might do better	 */

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2:	SET_PACA(r13)
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#ifdef CONFIG_PPC_BOOK3E
	addi	r12,r13,PACA_EXTLB	/* and TLB exc frame in another  */
	mtspr	SPRN_SPRG_TLB_EXFRAME,r12
#endif

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	/* From now on, r24 is expected to be logical cpuid */
	mr	r24,r5
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	/* See if we need to call a cpu state restore handler */
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	LOAD_REG_ADDR(r23, cur_cpu_spec)
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	ld	r23,0(r23)
	ld	r23,CPU_SPEC_RESTORE(r23)
	cmpdi	0,r23,0
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	beq	3f
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	ld	r23,0(r23)
	mtctr	r23
	bctrl

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3:	LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
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	lwarx	r4,0,r3
	subi	r4,r4,1
	stwcx.	r4,0,r3
	bne	3b
	isync

4:	HMT_LOW
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	lbz	r23,PACAPROCSTART(r13)	/* Test if this processor should */
					/* start.			 */
	cmpwi	0,r23,0
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	beq	4b			/* Loop until told to go	 */
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	sync				/* order paca.run and cur_cpu_spec */
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	isync				/* In case code patching happened */
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	/* Create a temp kernel stack for use before relocation is on.	*/
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	ld	r1,PACAEMERGSP(r13)
	subi	r1,r1,STACK_FRAME_OVERHEAD

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	b	__secondary_start
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#endif /* SMP */
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/*
 * Turn the MMU off.
 * Assumes we're mapped EA == RA if the MMU is on.
 */
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#ifdef CONFIG_PPC_BOOK3S
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_STATIC(__mmu_off)
	mfmsr	r3
	andi.	r0,r3,MSR_IR|MSR_DR
	beqlr
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	mflr	r4
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	andc	r3,r3,r0
	mtspr	SPRN_SRR0,r4
	mtspr	SPRN_SRR1,r3
	sync
	rfid
	b	.	/* prevent speculative execution */
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#endif
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/*
 * Here is our main kernel entry point. We support currently 2 kind of entries
 * depending on the value of r5.
 *
 *   r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
 *                 in r3...r7
 *   
 *   r5 == NULL -> kexec style entry. r3 is a physical pointer to the
 *                 DT block, r4 is a physical pointer to the kernel itself
 *
 */
_GLOBAL(__start_initialization_multiplatform)
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	/* Make sure we are running in 64 bits mode */
	bl	.enable_64b_mode

	/* Get TOC pointer (current runtime address) */
	bl	.relative_toc

	/* find out where we are now */
	bcl	20,31,$+4
0:	mflr	r26			/* r26 = runtime addr here */
	addis	r26,r26,(_stext - 0b)@ha
	addi	r26,r26,(_stext - 0b)@l	/* current runtime base addr */

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	/*
	 * Are we booted from a PROM Of-type client-interface ?
	 */
	cmpldi	cr0,r5,0
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	beq	1f
	b	.__boot_from_prom		/* yes -> prom */
1:
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	/* Save parameters */
	mr	r31,r3
	mr	r30,r4
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#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
	/* Save OPAL entry */
	mr	r28,r8
	mr	r29,r9
#endif
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#ifdef CONFIG_PPC_BOOK3E
	bl	.start_initialization_book3e
	b	.__after_prom_start
#else
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	/* Setup some critical 970 SPRs before switching MMU off */
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	mfspr	r0,SPRN_PVR
	srwi	r0,r0,16
	cmpwi	r0,0x39		/* 970 */
	beq	1f
	cmpwi	r0,0x3c		/* 970FX */
	beq	1f
	cmpwi	r0,0x44		/* 970MP */
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	beq	1f
	cmpwi	r0,0x45		/* 970GX */
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	bne	2f
1:	bl	.__cpu_preinit_ppc970
2:
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	/* Switch off MMU if not already off */
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	bl	.__mmu_off
	b	.__after_prom_start
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#endif /* CONFIG_PPC_BOOK3E */
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_INIT_STATIC(__boot_from_prom)
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#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
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	/* Save parameters */
	mr	r31,r3
	mr	r30,r4
	mr	r29,r5
	mr	r28,r6
	mr	r27,r7

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	/*
	 * Align the stack to 16-byte boundary
	 * Depending on the size and layout of the ELF sections in the initial
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	 * boot binary, the stack pointer may be unaligned on PowerMac
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	 */
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	rldicr	r1,r1,0,59

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#ifdef CONFIG_RELOCATABLE
	/* Relocate code for where we are now */
	mr	r3,r26
	bl	.relocate
#endif

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	/* Restore parameters */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27

	/* Do all of the interaction with OF client interface */
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	mr	r8,r26
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	bl	.prom_init
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#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */

	/* We never return. We also hit that trap if trying to boot
	 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
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	trap

_STATIC(__after_prom_start)
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#ifdef CONFIG_RELOCATABLE
	/* process relocations for the final address of the kernel */
	lis	r25,PAGE_OFFSET@highest	/* compute virtual base of kernel */
	sldi	r25,r25,32
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	lwz	r7,__run_at_load-_stext(r26)
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	cmplwi	cr0,r7,1	/* flagged to stay where we are ? */
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	bne	1f
	add	r25,r25,r26
1:	mr	r3,r25
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	bl	.relocate
#endif
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/*
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 * We need to run with _stext at physical address PHYSICAL_START.
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 * This will leave some code in the first 256B of
 * real memory, which are reserved for software use.
 *
 * Note: This process overwrites the OF exception vectors.
 */
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	li	r3,0			/* target addr */
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#ifdef CONFIG_PPC_BOOK3E
	tovirt(r3,r3)			/* on booke, we already run at PAGE_OFFSET */
#endif
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	mr.	r4,r26			/* In some cases the loader may  */
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	beq	9f			/* have already put us at zero */
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	li	r6,0x100		/* Start offset, the first 0x100 */
					/* bytes were copied earlier.	 */
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#ifdef CONFIG_PPC_BOOK3E
	tovirt(r6,r6)			/* on booke, we already run at PAGE_OFFSET */
#endif
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#ifdef CONFIG_RELOCATABLE
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/*
 * Check if the kernel has to be running as relocatable kernel based on the
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 * variable __run_at_load, if it is set the kernel is treated as relocatable
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 * kernel, otherwise it will be moved to PHYSICAL_START
 */
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	lwz	r7,__run_at_load-_stext(r26)
	cmplwi	cr0,r7,1
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	bne	3f

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	/* just copy interrupts */
	LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext)
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	b	5f
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#endif
	lis	r5,(copy_to_here - _stext)@ha
	addi	r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */

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	bl	.copy_and_flush		/* copy the first n bytes	 */
					/* this includes the code being	 */
					/* executed here.		 */
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	addis	r8,r3,(4f - _stext)@ha	/* Jump to the copy of this code */
	addi	r8,r8,(4f - _stext)@l	/* that we just made */
	mtctr	r8
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	bctr

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p_end:	.llong	_end - _stext

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4:	/* Now copy the rest of the kernel up to _end */
	addis	r5,r26,(p_end - _stext)@ha
	ld	r5,(p_end - _stext)@l(r5)	/* get _end */
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5:	bl	.copy_and_flush		/* copy the rest */
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9:	b	.start_here_multiplatform

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/*
 * Copy routine used to copy the kernel to start at physical address 0
 * and flush and invalidate the caches as needed.
 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
 *
 * Note: this routine *only* clobbers r0, r6 and lr
 */
_GLOBAL(copy_and_flush)
	addi	r5,r5,-8
	addi	r6,r6,-8
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4:	li	r0,8			/* Use the smallest common	*/
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					/* denominator cache line	*/
					/* size.  This results in	*/
					/* extra cache line flushes	*/
					/* but operation is correct.	*/
					/* Can't get cache line size	*/
					/* from NACA as it is being	*/
					/* moved too.			*/

	mtctr	r0			/* put # words/line in ctr	*/
3:	addi	r6,r6,8			/* copy a cache line		*/
	ldx	r0,r6,r4
	stdx	r0,r6,r3
	bdnz	3b
	dcbst	r6,r3			/* write it to memory		*/
	sync
	icbi	r6,r3			/* flush the icache line	*/
	cmpld	0,r6,r5
	blt	4b
	sync
	addi	r5,r5,8
	addi	r6,r6,8
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	isync
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	blr

.align 8
copy_to_here:

#ifdef CONFIG_SMP
#ifdef CONFIG_PPC_PMAC
/*
 * On PowerMac, secondary processors starts from the reset vector, which
 * is temporarily turned into a call to one of the functions below.
 */
	.section ".text";
	.align 2 ;

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	.globl	__secondary_start_pmac_0
__secondary_start_pmac_0:
	/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
	li	r24,0
	b	1f
	li	r24,1
	b	1f
	li	r24,2
	b	1f
	li	r24,3
1:
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_GLOBAL(pmac_secondary_start)
	/* turn on 64-bit mode */
	bl	.enable_64b_mode

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	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync
	slbia

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	/* get TOC pointer (real address) */
	bl	.relative_toc
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	tovirt(r2,r2)
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	/* Copy some CPU settings from CPU 0 */
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	bl	.__restore_cpu_ppc970
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	/* pSeries do that early though I don't think we really need it */
	mfmsr	r3
	ori	r3,r3,MSR_RI
	mtmsrd	r3			/* RI on */

	/* Set up a paca value for this processor. */
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	LOAD_REG_ADDR(r4,paca)		/* Load paca pointer		*/
	ld	r4,0(r4)		/* Get base vaddr of paca array	*/
567
	mulli	r13,r24,PACA_SIZE	/* Calculate vaddr of right paca */
568
	add	r13,r13,r4		/* for this processor.		*/
569
	SET_PACA(r13)			/* Save vaddr of paca in an SPRG*/
570

571
572
573
574
575
	/* Mark interrupts soft and hard disabled (they might be enabled
	 * in the PACA when doing hotplug)
	 */
	li	r0,0
	stb	r0,PACASOFTIRQEN(r13)
576
577
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)
578

579
580
581
582
	/* Create a temp kernel stack for use before relocation is on.	*/
	ld	r1,PACAEMERGSP(r13)
	subi	r1,r1,STACK_FRAME_OVERHEAD

583
	b	__secondary_start
584
585
586
587
588
589
590
591
592
593
594

#endif /* CONFIG_PPC_PMAC */

/*
 * This function is called after the master CPU has released the
 * secondary processors.  The execution environment is relocation off.
 * The paca for this processor has the following fields initialized at
 * this point:
 *   1. Processor number
 *   2. Segment table pointer (virtual address)
 * On entry the following are set:
595
 *   r1	       = stack pointer (real addr of temp stack)
596
597
598
 *   r24       = cpu# (in Linux terms)
 *   r13       = paca virtual address
 *   SPRG_PACA = paca virtual address
599
 */
600
601
602
	.section ".text";
	.align 2 ;

603
	.globl	__secondary_start
604
__secondary_start:
605
606
	/* Set thread priority to MEDIUM */
	HMT_MEDIUM
607

608
	/* Initialize the kernel stack */
609
	LOAD_REG_ADDR(r3, current_set)
610
	sldi	r28,r24,3		/* get current_set[cpu#]	 */
611
612
613
	ldx	r14,r3,r28
	addi	r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
	std	r14,PACAKSAVE(r13)
614

615
616
617
	/* Do early setup for that CPU (stab, slb, hash table pointer) */
	bl	.early_setup_secondary

618
619
620
621
622
623
	/*
	 * setup the new stack pointer, but *don't* use this until
	 * translation is on.
	 */
	mr	r1, r14

624
	/* Clear backchain so we get nice backtraces */
625
626
627
	li	r7,0
	mtlr	r7

628
629
630
	/* Mark interrupts soft and hard disabled (they might be enabled
	 * in the PACA when doing hotplug)
	 */
631
	stb	r7,PACASOFTIRQEN(r13)
632
633
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)
634

635
	/* enable MMU and jump to start_secondary */
636
637
	LOAD_REG_ADDR(r3, .start_secondary_prolog)
	LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
638

639
640
	mtspr	SPRN_SRR0,r3
	mtspr	SPRN_SRR1,r4
641
	RFI
642
643
644
645
	b	.	/* prevent speculative execution */

/* 
 * Running with relocation on at this point.  All we want to do is
646
647
 * zero the stack back-chain pointer and get the TOC virtual address
 * before going into C code.
648
649
 */
_GLOBAL(start_secondary_prolog)
650
	ld	r2,PACATOC(r13)
651
652
653
	li	r3,0
	std	r3,0(r1)		/* Zero the stack frame pointer	*/
	bl	.start_secondary
654
	b	.
655
656
657
658
659
660
661
662
663
664
665
/*
 * Reset stack pointer and call start_secondary
 * to continue with online operation when woken up
 * from cede in cpu offline.
 */
_GLOBAL(start_secondary_resume)
	ld	r1,PACAKSAVE(r13)	/* Reload kernel stack pointer */
	li	r3,0
	std	r3,0(r1)		/* Zero the stack frame pointer	*/
	bl	.start_secondary
	b	.
666
667
668
669
670
671
672
#endif

/*
 * This subroutine clobbers r11 and r12
 */
_GLOBAL(enable_64b_mode)
	mfmsr	r11			/* grab the current MSR */
673
674
675
676
#ifdef CONFIG_PPC_BOOK3E
	oris	r11,r11,0x8000		/* CM bit set, we'll set ICM later */
	mtmsr	r11
#else /* CONFIG_PPC_BOOK3E */
677
	li	r12,(MSR_64BIT | MSR_ISF)@highest
678
	sldi	r12,r12,48
679
680
681
	or	r11,r11,r12
	mtmsrd	r11
	isync
682
#endif
683
684
	blr

685
686
687
688
/*
 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
 * by the toolchain).  It computes the correct value for wherever we
 * are running at the moment, using position-independent code.
689
690
691
692
693
694
695
 *
 * Note: The compiler constructs pointers using offsets from the
 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
 * the MMU is on we need our TOC to be a virtual address otherwise
 * these pointers will be real addresses which may get stored and
 * accessed later with the MMU on. We use tovirt() at the call
 * sites to handle this.
696
697
698
699
 */
_GLOBAL(relative_toc)
	mflr	r0
	bcl	20,31,$+4
700
701
702
0:	mflr	r11
	ld	r2,(p_toc - 0b)(r11)
	add	r2,r2,r11
703
704
705
706
707
	mtlr	r0
	blr

p_toc:	.llong	__toc_start + 0x8000 - 0b

708
709
710
/*
 * This is where the main kernel code starts.
 */
711
_INIT_STATIC(start_here_multiplatform)
712
713
714
	/* set up the TOC */
	bl      .relative_toc
	tovirt(r2,r2)
715
716
717
718
719
720

	/* Clear out the BSS. It may have been done in prom_init,
	 * already but that's irrelevant since prom_init will soon
	 * be detached from the kernel completely. Besides, we need
	 * to clear it now for kexec-style entry.
	 */
721
722
	LOAD_REG_ADDR(r11,__bss_stop)
	LOAD_REG_ADDR(r8,__bss_start)
723
724
	sub	r11,r11,r8		/* bss size			*/
	addi	r11,r11,7		/* round up to an even double word */
725
	srdi.	r11,r11,3		/* shift right by 3		*/
726
727
728
729
730
731
732
733
	beq	4f
	addi	r8,r8,-8
	li	r0,0
	mtctr	r11			/* zero this many doublewords	*/
3:	stdu	r0,8(r8)
	bdnz	3b
4:

734
735
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
	/* Setup OPAL entry */
736
	LOAD_REG_ADDR(r11, opal)
737
738
739
740
	std	r28,0(r11);
	std	r29,8(r11);
#endif

741
#ifndef CONFIG_PPC_BOOK3E
742
743
744
	mfmsr	r6
	ori	r6,r6,MSR_RI
	mtmsrd	r6			/* RI on */
745
#endif
746

747
748
749
750
751
752
753
#ifdef CONFIG_RELOCATABLE
	/* Save the physical address we're running at in kernstart_addr */
	LOAD_REG_ADDR(r4, kernstart_addr)
	clrldi	r0,r25,2
	std	r0,0(r4)
#endif

754
	/* The following gets the stack set up with the regs */
755
756
757
758
759
	/* pointing to the real addr of the kernel stack.  This is   */
	/* all done to support the C function call below which sets  */
	/* up the htab.  This is done because we have relocated the  */
	/* kernel but are still running in real mode. */

760
	LOAD_REG_ADDR(r3,init_thread_union)
761

762
	/* set up a stack pointer */
763
764
765
766
767
768
769
770
771
	addi	r1,r3,THREAD_SIZE
	li	r0,0
	stdu	r0,-STACK_FRAME_OVERHEAD(r1)

	/* Do very early kernel initializations, including initial hash table,
	 * stab and slb setup before we turn on relocation.	*/

	/* Restore parameters passed from prom_init/kexec */
	mr	r3,r31
772
	bl	.early_setup		/* also sets r13 and SPRG_PACA */
773

774
775
	LOAD_REG_ADDR(r3, .start_here_common)
	ld	r4,PACAKMSR(r13)
776
777
	mtspr	SPRN_SRR0,r3
	mtspr	SPRN_SRR1,r4
778
	RFI
779
780
781
	b	.	/* prevent speculative execution */
	
	/* This is where all platforms converge execution */
782
_INIT_GLOBAL(start_here_common)
783
	/* relocation is on at this point */
784
	std	r1,PACAKSAVE(r13)
785

786
	/* Load the TOC (virtual address) */
787
788
	ld	r2,PACATOC(r13)

789
	/* Do more system initializations in virtual mode */
790
791
	bl	.setup_system

792
793
794
795
796
797
798
	/* Mark interrupts soft and hard disabled (they might be enabled
	 * in the PACA when doing hotplug)
	 */
	li	r0,0
	stb	r0,PACASOFTIRQEN(r13)
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)
799

800
	/* Generic kernel entry */
801
	bl	.start_kernel
802

803
804
	/* Not reached */
	BUG_OPCODE
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819

/*
 * We put a few things here that have to be page-aligned.
 * This stuff goes at the beginning of the bss, which is page-aligned.
 */
	.section ".bss"

	.align	PAGE_SHIFT

	.globl	empty_zero_page
empty_zero_page:
	.space	PAGE_SIZE

	.globl	swapper_pg_dir
swapper_pg_dir:
820
	.space	PGD_TABLE_SIZE