intel-iommu.c 99.8 KB
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/*
 * Copyright (c) 2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
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 * Copyright (C) 2006-2008 Intel Corporation
 * Author: Ashok Raj <ashok.raj@intel.com>
 * Author: Shaohua Li <shaohua.li@intel.com>
 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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 * Author: Fenghua Yu <fenghua.yu@intel.com>
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 */

#include <linux/init.h>
#include <linux/bitmap.h>
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#include <linux/debugfs.h>
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#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
#include <linux/dmar.h>
#include <linux/dma-mapping.h>
#include <linux/mempool.h>
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#include <linux/timer.h>
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#include <linux/iova.h>
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#include <linux/iommu.h>
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#include <linux/intel-iommu.h>
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#include <linux/syscore_ops.h>
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#include <linux/tboot.h>
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#include <linux/dmi.h>
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#include <linux/pci-ats.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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#define ROOT_SIZE		VTD_PAGE_SIZE
#define CONTEXT_SIZE		VTD_PAGE_SIZE

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#define IS_BRIDGE_HOST_DEVICE(pdev) \
			    ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
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#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
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#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
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#define IOAPIC_RANGE_START	(0xfee00000)
#define IOAPIC_RANGE_END	(0xfeefffff)
#define IOVA_START_ADDR		(0x1000)

#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48

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#define MAX_AGAW_WIDTH 64

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#define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)

/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
   to match. That way, we can use 'unsigned long' for PFNs with impunity. */
#define DOMAIN_MAX_PFN(gaw)	((unsigned long) min_t(uint64_t, \
				__DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
#define DOMAIN_MAX_ADDR(gaw)	(((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
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#define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
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#define DMA_32BIT_PFN		IOVA_PFN(DMA_BIT_MASK(32))
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#define DMA_64BIT_PFN		IOVA_PFN(DMA_BIT_MASK(64))
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/* page table handling */
#define LEVEL_STRIDE		(9)
#define LEVEL_MASK		(((u64)1 << LEVEL_STRIDE) - 1)

static inline int agaw_to_level(int agaw)
{
	return agaw + 2;
}

static inline int agaw_to_width(int agaw)
{
	return 30 + agaw * LEVEL_STRIDE;
}

static inline int width_to_agaw(int width)
{
	return (width - 30) / LEVEL_STRIDE;
}

static inline unsigned int level_to_offset_bits(int level)
{
	return (level - 1) * LEVEL_STRIDE;
}

static inline int pfn_level_offset(unsigned long pfn, int level)
{
	return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}

static inline unsigned long level_mask(int level)
{
	return -1UL << level_to_offset_bits(level);
}

static inline unsigned long level_size(int level)
{
	return 1UL << level_to_offset_bits(level);
}

static inline unsigned long align_to_level(unsigned long pfn, int level)
{
	return (pfn + level_size(level) - 1) & level_mask(level);
}
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static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
	return  1 << ((lvl - 1) * LEVEL_STRIDE);
}

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/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
   are never going to work. */
static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
{
	return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
}

static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
{
	return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
}
static inline unsigned long page_to_dma_pfn(struct page *pg)
{
	return mm_to_dma_pfn(page_to_pfn(pg));
}
static inline unsigned long virt_to_dma_pfn(void *p)
{
	return page_to_dma_pfn(virt_to_page(p));
}

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/* global iommu list, set NULL for ignored DMAR units */
static struct intel_iommu **g_iommus;

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static void __init check_tylersburg_isoch(void);
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static int rwbf_quirk;

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/*
 * set to 1 to panic kernel if can't successfully enable VT-d
 * (used when kernel is launched w/ TXT)
 */
static int force_on = 0;

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/*
 * 0: Present
 * 1-11: Reserved
 * 12-63: Context Ptr (12 - (haw-1))
 * 64-127: Reserved
 */
struct root_entry {
	u64	val;
	u64	rsvd1;
};
#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
static inline bool root_present(struct root_entry *root)
{
	return (root->val & 1);
}
static inline void set_root_present(struct root_entry *root)
{
	root->val |= 1;
}
static inline void set_root_value(struct root_entry *root, unsigned long value)
{
	root->val |= value & VTD_PAGE_MASK;
}

static inline struct context_entry *
get_context_addr_from_root(struct root_entry *root)
{
	return (struct context_entry *)
		(root_present(root)?phys_to_virt(
		root->val & VTD_PAGE_MASK) :
		NULL);
}

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/*
 * low 64 bits:
 * 0: present
 * 1: fault processing disable
 * 2-3: translation type
 * 12-63: address space root
 * high 64 bits:
 * 0-2: address width
 * 3-6: aval
 * 8-23: domain id
 */
struct context_entry {
	u64 lo;
	u64 hi;
};
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static inline bool context_present(struct context_entry *context)
{
	return (context->lo & 1);
}
static inline void context_set_present(struct context_entry *context)
{
	context->lo |= 1;
}

static inline void context_set_fault_enable(struct context_entry *context)
{
	context->lo &= (((u64)-1) << 2) | 1;
}

static inline void context_set_translation_type(struct context_entry *context,
						unsigned long value)
{
	context->lo &= (((u64)-1) << 4) | 3;
	context->lo |= (value & 3) << 2;
}

static inline void context_set_address_root(struct context_entry *context,
					    unsigned long value)
{
	context->lo |= value & VTD_PAGE_MASK;
}

static inline void context_set_address_width(struct context_entry *context,
					     unsigned long value)
{
	context->hi |= value & 7;
}

static inline void context_set_domain_id(struct context_entry *context,
					 unsigned long value)
{
	context->hi |= (value & ((1 << 16) - 1)) << 8;
}

static inline void context_clear_entry(struct context_entry *context)
{
	context->lo = 0;
	context->hi = 0;
}
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/*
 * 0: readable
 * 1: writable
 * 2-6: reserved
 * 7: super page
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 * 8-10: available
 * 11: snoop behavior
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 * 12-63: Host physcial address
 */
struct dma_pte {
	u64 val;
};

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static inline void dma_clear_pte(struct dma_pte *pte)
{
	pte->val = 0;
}

static inline void dma_set_pte_readable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_READ;
}

static inline void dma_set_pte_writable(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_WRITE;
}

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static inline void dma_set_pte_snp(struct dma_pte *pte)
{
	pte->val |= DMA_PTE_SNP;
}

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static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
{
	pte->val = (pte->val & ~3) | (prot & 3);
}

static inline u64 dma_pte_addr(struct dma_pte *pte)
{
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#ifdef CONFIG_64BIT
	return pte->val & VTD_PAGE_MASK;
#else
	/* Must have a full atomic 64-bit read */
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	return  __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
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#endif
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}

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static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
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{
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	pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
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}

static inline bool dma_pte_present(struct dma_pte *pte)
{
	return (pte->val & 3) != 0;
}
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static inline int first_pte_in_page(struct dma_pte *pte)
{
	return !((unsigned long)pte & ~VTD_PAGE_MASK);
}

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/*
 * This domain is a statically identity mapping domain.
 *	1. This domain creats a static 1:1 mapping to all usable memory.
 * 	2. It maps to each iommu if successful.
 *	3. Each iommu mapps to this domain if successful.
 */
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static struct dmar_domain *si_domain;
static int hw_pass_through = 1;
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/* devices under the same p2p bridge are owned in one domain */
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#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
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/* domain represents a virtual machine, more than one devices
 * across iommus may be owned in one domain, e.g. kvm guest.
 */
#define DOMAIN_FLAG_VIRTUAL_MACHINE	(1 << 1)

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/* si_domain contains mulitple devices */
#define DOMAIN_FLAG_STATIC_IDENTITY	(1 << 2)

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struct dmar_domain {
	int	id;			/* domain id */
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	int	nid;			/* node id */
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	unsigned long iommu_bmp;	/* bitmap of iommus this domain uses*/
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	struct list_head devices; 	/* all devices' list */
	struct iova_domain iovad;	/* iova's that belong to this domain */

	struct dma_pte	*pgd;		/* virtual address */
	int		gaw;		/* max guest address width */

	/* adjusted guest address width, 0 is level 2 30-bit */
	int		agaw;

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	int		flags;		/* flags to find out type of domain */
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	int		iommu_coherency;/* indicate coherency of iommu access */
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	int		iommu_snooping; /* indicate snooping control feature*/
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	int		iommu_count;	/* reference count of iommu */
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	int		iommu_superpage;/* Level of superpages supported:
					   0 == 4KiB (no superpages), 1 == 2MiB,
					   2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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	spinlock_t	iommu_lock;	/* protect iommu set in domain */
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	u64		max_addr;	/* maximum mapped address */
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};

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/* PCI domain-device relationship */
struct device_domain_info {
	struct list_head link;	/* link to domain siblings */
	struct list_head global; /* link to global list */
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	int segment;		/* PCI domain */
	u8 bus;			/* PCI bus number */
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	u8 devfn;		/* PCI devfn number */
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	struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
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	struct intel_iommu *iommu; /* IOMMU used by this device */
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	struct dmar_domain *domain; /* pointer to domain */
};

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static void flush_unmaps_timeout(unsigned long data);

DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);

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#define HIGH_WATER_MARK 250
struct deferred_flush_tables {
	int next;
	struct iova *iova[HIGH_WATER_MARK];
	struct dmar_domain *domain[HIGH_WATER_MARK];
};

static struct deferred_flush_tables *deferred_flush;

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/* bitmap for indexing intel_iommus */
static int g_num_of_iommus;

static DEFINE_SPINLOCK(async_umap_flush_lock);
static LIST_HEAD(unmaps_to_do);

static int timer_on;
static long list_size;

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static void domain_remove_dev_info(struct dmar_domain *domain);

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#ifdef CONFIG_DMAR_DEFAULT_ON
int dmar_disabled = 0;
#else
int dmar_disabled = 1;
#endif /*CONFIG_DMAR_DEFAULT_ON*/

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static int dmar_map_gfx = 1;
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static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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int intel_iommu_gfx_mapped;
EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);

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#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
static DEFINE_SPINLOCK(device_domain_lock);
static LIST_HEAD(device_domain_list);

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static struct iommu_ops intel_iommu_ops;

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static int __init intel_iommu_setup(char *str)
{
	if (!str)
		return -EINVAL;
	while (*str) {
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		if (!strncmp(str, "on", 2)) {
			dmar_disabled = 0;
			printk(KERN_INFO "Intel-IOMMU: enabled\n");
		} else if (!strncmp(str, "off", 3)) {
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			dmar_disabled = 1;
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			printk(KERN_INFO "Intel-IOMMU: disabled\n");
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		} else if (!strncmp(str, "igfx_off", 8)) {
			dmar_map_gfx = 0;
			printk(KERN_INFO
				"Intel-IOMMU: disable GFX device mapping\n");
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		} else if (!strncmp(str, "forcedac", 8)) {
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			printk(KERN_INFO
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				"Intel-IOMMU: Forcing DAC for PCI devices\n");
			dmar_forcedac = 1;
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		} else if (!strncmp(str, "strict", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable batched IOTLB flush\n");
			intel_iommu_strict = 1;
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		} else if (!strncmp(str, "sp_off", 6)) {
			printk(KERN_INFO
				"Intel-IOMMU: disable supported super page\n");
			intel_iommu_superpage = 0;
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		}

		str += strcspn(str, ",");
		while (*str == ',')
			str++;
	}
	return 0;
}
__setup("intel_iommu=", intel_iommu_setup);

static struct kmem_cache *iommu_domain_cache;
static struct kmem_cache *iommu_devinfo_cache;
static struct kmem_cache *iommu_iova_cache;

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static inline void *alloc_pgtable_page(int node)
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{
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	struct page *page;
	void *vaddr = NULL;
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	page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
	if (page)
		vaddr = page_address(page);
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	return vaddr;
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}

static inline void free_pgtable_page(void *vaddr)
{
	free_page((unsigned long)vaddr);
}

static inline void *alloc_domain_mem(void)
{
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	return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
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}

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static void free_domain_mem(void *vaddr)
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{
	kmem_cache_free(iommu_domain_cache, vaddr);
}

static inline void * alloc_devinfo_mem(void)
{
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	return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
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}

static inline void free_devinfo_mem(void *vaddr)
{
	kmem_cache_free(iommu_devinfo_cache, vaddr);
}

struct iova *alloc_iova_mem(void)
{
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	return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
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}

void free_iova_mem(struct iova *iova)
{
	kmem_cache_free(iommu_iova_cache, iova);
}

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static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
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{
	unsigned long sagaw;
	int agaw = -1;

	sagaw = cap_sagaw(iommu->cap);
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	for (agaw = width_to_agaw(max_gaw);
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	     agaw >= 0; agaw--) {
		if (test_bit(agaw, &sagaw))
			break;
	}

	return agaw;
}

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/*
 * Calculate max SAGAW for each iommu.
 */
int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
}

/*
 * calculate agaw for each iommu.
 * "SAGAW" may be different across iommus, use a default agaw, and
 * get a supported less agaw for iommus that don't support the default agaw.
 */
int iommu_calculate_agaw(struct intel_iommu *iommu)
{
	return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
}

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/* This functionin only returns single iommu in a domain */
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static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
{
	int iommu_id;

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	/* si_domain and vm domain should not get here. */
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	BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
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	BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
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	iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
	if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
		return NULL;

	return g_iommus[iommu_id];
}

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static void domain_update_iommu_coherency(struct dmar_domain *domain)
{
	int i;

	domain->iommu_coherency = 1;

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	for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
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		if (!ecap_coherent(g_iommus[i]->ecap)) {
			domain->iommu_coherency = 0;
			break;
		}
	}
}

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static void domain_update_iommu_snooping(struct dmar_domain *domain)
{
	int i;

	domain->iommu_snooping = 1;

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	for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
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		if (!ecap_sc_support(g_iommus[i]->ecap)) {
			domain->iommu_snooping = 0;
			break;
		}
	}
}

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static void domain_update_iommu_superpage(struct dmar_domain *domain)
{
	int i, mask = 0xf;

	if (!intel_iommu_superpage) {
		domain->iommu_superpage = 0;
		return;
	}

	domain->iommu_superpage = 4; /* 1TiB */

	for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
		mask |= cap_super_page_val(g_iommus[i]->cap);
		if (!mask) {
			break;
		}
	}
	domain->iommu_superpage = fls(mask);
}

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/* Some capabilities may be different across iommus */
static void domain_update_iommu_cap(struct dmar_domain *domain)
{
	domain_update_iommu_coherency(domain);
	domain_update_iommu_snooping(domain);
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	domain_update_iommu_superpage(domain);
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}

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static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
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{
	struct dmar_drhd_unit *drhd = NULL;
	int i;

	for_each_drhd_unit(drhd) {
		if (drhd->ignored)
			continue;
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		if (segment != drhd->segment)
			continue;
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		for (i = 0; i < drhd->devices_cnt; i++) {
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			if (drhd->devices[i] &&
			    drhd->devices[i]->bus->number == bus &&
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			    drhd->devices[i]->devfn == devfn)
				return drhd->iommu;
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			if (drhd->devices[i] &&
			    drhd->devices[i]->subordinate &&
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			    drhd->devices[i]->subordinate->number <= bus &&
			    drhd->devices[i]->subordinate->subordinate >= bus)
				return drhd->iommu;
		}
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		if (drhd->include_all)
			return drhd->iommu;
	}

	return NULL;
}

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static void domain_flush_cache(struct dmar_domain *domain,
			       void *addr, int size)
{
	if (!domain->iommu_coherency)
		clflush_cache_range(addr, size);
}

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/* Gets context entry for a given bus and devfn */
static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
		u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long phy_addr;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
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		context = (struct context_entry *)
				alloc_pgtable_page(iommu->node);
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		if (!context) {
			spin_unlock_irqrestore(&iommu->lock, flags);
			return NULL;
		}
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		__iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
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		phy_addr = virt_to_phys((void *)context);
		set_root_value(root, phy_addr);
		set_root_present(root);
		__iommu_flush_cache(iommu, root, sizeof(*root));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
	return &context[devfn];
}

static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	int ret;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (!context) {
		ret = 0;
		goto out;
	}
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	ret = context_present(&context[devfn]);
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out:
	spin_unlock_irqrestore(&iommu->lock, flags);
	return ret;
}

static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
{
	struct root_entry *root;
	struct context_entry *context;
	unsigned long flags;

	spin_lock_irqsave(&iommu->lock, flags);
	root = &iommu->root_entry[bus];
	context = get_context_addr_from_root(root);
	if (context) {
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		context_clear_entry(&context[devfn]);
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		__iommu_flush_cache(iommu, &context[devfn], \
			sizeof(*context));
	}
	spin_unlock_irqrestore(&iommu->lock, flags);
}

static void free_context_table(struct intel_iommu *iommu)
{
	struct root_entry *root;
	int i;
	unsigned long flags;
	struct context_entry *context;

	spin_lock_irqsave(&iommu->lock, flags);
	if (!iommu->root_entry) {
		goto out;
	}
	for (i = 0; i < ROOT_ENTRY_NR; i++) {
		root = &iommu->root_entry[i];
		context = get_context_addr_from_root(root);
		if (context)
			free_pgtable_page(context);
	}
	free_pgtable_page(iommu->root_entry);
	iommu->root_entry = NULL;
out:
	spin_unlock_irqrestore(&iommu->lock, flags);
}

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static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
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				      unsigned long pfn, int large_level)
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{
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	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
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	struct dma_pte *parent, *pte = NULL;
	int level = agaw_to_level(domain->agaw);
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	int offset, target_level;
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	BUG_ON(!domain->pgd);
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	BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
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	parent = domain->pgd;

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	/* Search pte */
	if (!large_level)
		target_level = 1;
	else
		target_level = large_level;

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	while (level > 0) {
		void *tmp_page;

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		offset = pfn_level_offset(pfn, level);
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		pte = &parent[offset];
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		if (!large_level && (pte->val & DMA_PTE_LARGE_PAGE))
			break;
		if (level == target_level)
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			break;

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		if (!dma_pte_present(pte)) {
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			uint64_t pteval;

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			tmp_page = alloc_pgtable_page(domain->nid);
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			if (!tmp_page)
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				return NULL;
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			domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
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			pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
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			if (cmpxchg64(&pte->val, 0ULL, pteval)) {
				/* Someone else set it while we were thinking; use theirs. */
				free_pgtable_page(tmp_page);
			} else {
				dma_pte_addr(pte);
				domain_flush_cache(domain, pte, sizeof(*pte));
			}
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		}
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		parent = phys_to_virt(dma_pte_addr(pte));
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		level--;
	}

	return pte;
}

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/* return address's pte at specific level */
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static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
					 unsigned long pfn,
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					 int level, int *large_page)
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{
	struct dma_pte *parent, *pte = NULL;
	int total = agaw_to_level(domain->agaw);
	int offset;

	parent = domain->pgd;
	while (level <= total) {
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		offset = pfn_level_offset(pfn, total);
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		pte = &parent[offset];
		if (level == total)
			return pte;

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		if (!dma_pte_present(pte)) {
			*large_page = total;
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			break;
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		}

		if (pte->val & DMA_PTE_LARGE_PAGE) {
			*large_page = total;
			return pte;
		}

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		parent = phys_to_virt(dma_pte_addr(pte));
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		total--;
	}
	return NULL;
}

/* clear last level pte, a tlb flush should be followed */
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static int dma_pte_clear_range(struct dmar_domain *domain,
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				unsigned long start_pfn,
				unsigned long last_pfn)
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{
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	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
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	unsigned int large_page = 1;
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	struct dma_pte *first_pte, *pte;
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	int order;
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	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
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	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
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	BUG_ON(start_pfn > last_pfn);
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	/* we don't need lock here; nobody else touches the iova range */
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	do {
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		large_page = 1;
		first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
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		if (!pte) {
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			start_pfn = align_to_level(start_pfn + 1, large_page + 1);
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			continue;
		}
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		do {
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			dma_clear_pte(pte);
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			start_pfn += lvl_to_nr_pages(large_page);
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			pte++;
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		} while (start_pfn <= last_pfn && !first_pte_in_page(pte));

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		domain_flush_cache(domain, first_pte,
				   (void *)pte - (void *)first_pte);
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	} while (start_pfn && start_pfn <= last_pfn);
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	order = (large_page - 1) * 9;
	return order;
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}

/* free page table pages. last level pte should already be cleared */
static void dma_pte_free_pagetable(struct dmar_domain *domain,
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				   unsigned long start_pfn,
				   unsigned long last_pfn)
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{
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	int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
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	struct dma_pte *first_pte, *pte;
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	int total = agaw_to_level(domain->agaw);
	int level;
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	unsigned long tmp;
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	int large_page = 2;
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	BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
	BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
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	BUG_ON(start_pfn > last_pfn);
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	/* We don't need lock here; nobody else touches the iova range */
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	level = 2;
	while (level <= total) {
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		tmp = align_to_level(start_pfn, level);

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		/* If we can't even clear one PTE at this level, we're done */
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		if (tmp + level_size(level) - 1 > last_pfn)
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			return;

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		do {
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			large_page = level;
			first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
			if (large_page > level)
				level = large_page + 1;
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			if (!pte) {
				tmp = align_to_level(tmp + 1, level + 1);
				continue;
			}
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			do {
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				if (dma_pte_present(pte)) {
					free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
					dma_clear_pte(pte);
				}
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				pte++;
				tmp += level_size(level);
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			} while (!first_pte_in_page(pte) &&
				 tmp + level_size(level) - 1 <= last_pfn);

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			domain_flush_cache(domain, first_pte,
					   (void *)pte - (void *)first_pte);
			
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		} while (tmp && tmp + level_size(level) - 1 <= last_pfn);
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		level++;
	}
	/* free pgd */
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	if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
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		free_pgtable_page(domain->pgd);
		domain->pgd = NULL;
	}
}

/* iommu handling */
static int iommu_alloc_root_entry(struct intel_iommu *iommu)
{
	struct root_entry *root;
	unsigned long flags;

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	root = (struct root_entry *)alloc_pgtable_page(iommu->node);
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	if (!root)
		return -ENOMEM;

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	__iommu_flush_cache(iommu, root, ROOT_SIZE);
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	spin_lock_irqsave(&iommu->lock, flags);
	iommu->root_entry = root;
	spin_unlock_irqrestore(&iommu->lock, flags);

	return 0;
}

static void iommu_set_root_entry(struct intel_iommu *iommu)
{
	void *addr;
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	u32 sts;
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	unsigned long flag;

	addr = iommu->root_entry;

	spin_lock_irqsave(&iommu->register_lock, flag);
	dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));

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	writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
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	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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		      readl, (sts & DMA_GSTS_RTPS), sts);
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	spin_unlock_irqrestore(&iommu->register_lock, flag);
}

static void iommu_flush_write_buffer(struct intel_iommu *iommu)
{
	u32 val;
	unsigned long flag;

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	if (!rwbf_quirk && !cap_rwbf(iommu->cap))
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		return;

	spin_lock_irqsave(&iommu->register_lock, flag);
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	writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
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	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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		      readl, (!(val & DMA_GSTS_WBFS)), val);
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	spin_unlock_irqrestore(&iommu->register_lock, flag);
}

/* return value determine if we need a write buffer flush */
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static void __iommu_flush_context(struct intel_iommu *iommu,
				  u16 did, u16 source_id, u8 function_mask,
				  u64 type)
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{
	u64 val = 0;
	unsigned long flag;

	switch (type) {
	case DMA_CCMD_GLOBAL_INVL:
		val = DMA_CCMD_GLOBAL_INVL;
		break;
	case DMA_CCMD_DOMAIN_INVL:
		val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
		break;
	case DMA_CCMD_DEVICE_INVL:
		val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
			| DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
		break;
	default:
		BUG();
	}
	val |= DMA_CCMD_ICC;

	spin_lock_irqsave(&iommu->register_lock, flag);
	dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
		dmar_readq, (!(val & DMA_CCMD_ICC)), val);

	spin_unlock_irqrestore(&iommu->register_lock, flag);
}

/* return value determine if we need a write buffer flush */
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static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
				u64 addr, unsigned int size_order, u64 type)
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{
	int tlb_offset = ecap_iotlb_offset(iommu->ecap);
	u64 val = 0, val_iva = 0;
	unsigned long flag;

	switch (type) {
	case DMA_TLB_GLOBAL_FLUSH:
		/* global flush doesn't need set IVA_REG */
		val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
		break;
	case DMA_TLB_DSI_FLUSH:
		val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		break;
	case DMA_TLB_PSI_FLUSH:
		val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
		/* Note: always flush non-leaf currently */
		val_iva = size_order | addr;
		break;
	default:
		BUG();
	}
	/* Note: set drain read/write */
#if 0
	/*
	 * This is probably to be super secure.. Looks like we can
	 * ignore it without any impact.
	 */
	if (cap_read_drain(iommu->cap))
		val |= DMA_TLB_READ_DRAIN;
#endif
	if (cap_write_drain(iommu->cap))
		val |= DMA_TLB_WRITE_DRAIN;

	spin_lock_irqsave(&iommu->register_lock, flag);
	/* Note: Only uses first TLB reg currently */
	if (val_iva)
		dmar_writeq(iommu->reg + tlb_offset, val_iva);
	dmar_writeq(iommu->reg + tlb_offset + 8, val);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, tlb_offset + 8,
		dmar_readq, (!(val & DMA_TLB_IVT)), val);

	spin_unlock_irqrestore(&iommu->register_lock, flag);

	/* check IOTLB invalidation granularity */
	if (DMA_TLB_IAIG(val) == 0)
		printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
	if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
		pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
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			(unsigned long long)DMA_TLB_IIRG(type),
			(unsigned long long)DMA_TLB_IAIG(val));
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}

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static struct device_domain_info *iommu_support_dev_iotlb(
	struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
{
	int found = 0;
	unsigned long flags;
	struct device_domain_info *info;
	struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);

	if (!ecap_dev_iotlb_support(iommu->ecap))
		return NULL;

	if (!iommu->qi)
		return NULL;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link)
		if (info->bus == bus && info->devfn == devfn) {
			found = 1;
			break;
		}
	spin_unlock_irqrestore(&device_domain_lock, flags);

	if (!found || !info->dev)
		return NULL;

	if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
		return NULL;

	if (!dmar_find_matched_atsr_unit(info->dev))
		return NULL;

	info->iommu = iommu;

	return info;
}

static void iommu_enable_dev_iotlb(struct device_domain_info *info)
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{
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	if (!info)
		return;

	pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
}

static void iommu_disable_dev_iotlb(struct device_domain_info *info)
{
	if (!info->dev || !pci_ats_enabled(info->dev))
		return;

	pci_disable_ats(info->dev);
}

static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
				  u64 addr, unsigned mask)
{
	u16 sid, qdep;
	unsigned long flags;
	struct device_domain_info *info;

	spin_lock_irqsave(&device_domain_lock, flags);
	list_for_each_entry(info, &domain->devices, link) {
		if (!info->dev || !pci_ats_enabled(info->dev))
			continue;

		sid = info->bus << 8 | info->devfn;
		qdep = pci_ats_queue_depth(info->dev);
		qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
	}
	spin_unlock_irqrestore(&device_domain_lock, flags);
}

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static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
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				  unsigned long pfn, unsigned int pages, int map)
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{
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	unsigned int mask = ilog2(__roundup_pow_of_two(pages));
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	uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
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	BUG_ON(pages == 0);

	/*
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	 * Fallback to domain selective flush if no PSI support or the size is
	 * too big.
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	 * PSI requires page size to be 2 ^ x, and the base address is naturally
	 * aligned to the size
	 */
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	if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
		iommu->flush.flush_iotlb(iommu, did, 0, 0,
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						DMA_TLB_DSI_FLUSH);
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	else
		iommu->flush.flush_iotlb(iommu, did, addr, mask,
						DMA_TLB_PSI_FLUSH);
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	/*
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	 * In caching mode, changes of pages from non-present to present require
	 * flush. However, device IOTLB doesn't need to be flushed in this case.
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	 */
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	if (!cap_caching_mode(iommu->cap) || !map)
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		iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
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}

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static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
{
	u32 pmen;
	unsigned long flags;

	spin_lock_irqsave(&iommu->register_lock, flags);
	pmen = readl(iommu->reg + DMAR_PMEN_REG);
	pmen &= ~DMA_PMEN_EPM;
	writel(pmen, iommu->reg + DMAR_PMEN_REG);

	/* wait for the protected region status bit to clear */
	IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
		readl, !(pmen & DMA_PMEN_PRS), pmen);

	spin_unlock_irqrestore(&iommu->register_lock, flags);
}

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static int iommu_enable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flags;

	spin_lock_irqsave(&iommu->register_lock, flags);
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	iommu->gcmd |= DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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		      readl, (sts & DMA_GSTS_TES), sts);
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	spin_unlock_irqrestore(&iommu->register_lock, flags);
	return 0;
}

static int iommu_disable_translation(struct intel_iommu *iommu)
{
	u32 sts;
	unsigned long flag;

	spin_lock_irqsave(&iommu->register_lock, flag);
	iommu->gcmd &= ~DMA_GCMD_TE;
	writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

	/* Make sure hardware complete it */
	IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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		      readl, (!(sts & DMA_GSTS_TES)), sts);
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	spin_unlock_irqrestore(&iommu->register_lock, flag);
	return 0;
}

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static int iommu_init_domains(struct intel_iommu *iommu)
{
	unsigned long ndomains;
	unsigned long nlongs;

	ndomains = cap_ndoms(iommu->cap);
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	pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id,
			ndomains);
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	nlongs = BITS_TO_LONGS(ndomains);

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	spin_lock_init(&iommu->lock);

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	/* TBD: there might be 64K domains,
	 * consider other allocation for future chip
	 */
	iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
	if (!iommu->domain_ids) {
		printk(KERN_ERR "Allocating domain id array failed\n");
		return -ENOMEM;
	}
	iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
			GFP_KERNEL);
	if (!iommu->domains) {
		printk(KERN_ERR "Allocating domain array failed\n");
		return -ENOMEM;
	}

	/*
	 * if Caching mode is set, then invalid translations are tagged
	 * with domainid 0. Hence we need to pre-allocate it.
	 */
	if (cap_caching_mode(iommu->cap))
		set_bit(0, iommu->domain_ids);
	return 0;
}


static void domain_exit(struct dmar_domain *domain);
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static void vm_domain_exit(struct dmar_domain *domain);
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void free_dmar_iommu(struct intel_iommu *iommu)
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{
	struct dmar_domain *domain;
	int i;
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	unsigned long flags;
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	if ((iommu->domains) && (iommu->domain_ids)) {
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		for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
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			domain = iommu->domains[i];
			clear_bit(i, iommu->domain_ids);

			spin_lock_irqsave(&domain->iommu_lock, flags);
			if (--domain->iommu_count == 0) {
				if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
					vm_domain_exit(domain);
				else
					domain_exit(domain);
			}
			spin_unlock_irqrestore(&domain->iommu_lock, flags);
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		}
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	}

	if (iommu->gcmd & DMA_GCMD_TE)
		iommu_disable_translation(iommu);

	if (iommu->irq) {
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		irq_set_handler_data(iommu->irq, NULL);
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		/* This will mask the irq */
		free_irq(iommu->irq, iommu);
		destroy_irq(iommu->irq);
	}

	kfree(iommu->domains);
	kfree(iommu->domain_ids);

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	g_iommus[iommu->seq_id] = NULL;

	/* if all iommus are freed, free g_iommus */
	for (i = 0; i < g_num_of_iommus; i++) {
		if (g_iommus[i])
			break;
	}

	if (i == g_num_of_iommus)
		kfree(g_iommus);

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	/* free context mapping */
	free_context_table(iommu);
}

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static struct dmar_domain *alloc_domain(void)
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{
	struct dmar_domain *domain;

	domain = alloc_domain_mem();
	if (!domain)
		return NULL;

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	domain->nid = -1;
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	memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
	domain->flags = 0;

	return domain;
}

static int iommu_attach_domain(struct dmar_domain *domain,
			       struct intel_iommu *iommu)
{
	int num;
	unsigned long ndomains;
	unsigned long flags;

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	ndomains = cap_ndoms(iommu->cap);

	spin_lock_irqsave(&iommu->lock, flags);
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	num = find_first_zero_bit(iommu->domain_ids, ndomains);
	if (num >= ndomains) {
		spin_unlock_irqrestore(&iommu->lock, flags);
		printk(KERN_ERR "IOMMU: no free domain ids\n");
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		return -ENOMEM;
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	}

	domain->id = num;
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	set_bit(num, iommu->domain_ids);
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	set_bit(iommu->seq_id, &domain->iommu_bmp);
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	iommu->domains[num] = domain;
	spin_unlock_irqrestore(&iommu->lock, flags);

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	return 0;
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}

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static void iommu_detach_domain(struct dmar_domain *domain,
				struct intel_iommu *iommu)
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{
	unsigned long flags;
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	int num, ndomains;
	int found = 0;
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	spin_lock_irqsave(&iommu->lock, flags);
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	ndomains = cap_ndoms(iommu->cap);
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	for_each_set_bit(num, iommu->domain_ids, ndomains) {
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		if (iommu->domains[num] == domain) {
			found = 1;
			break;
		}
	}

	if (found) {
		clear_bit(num, iommu->domain_ids);
		clear_bit(iommu->seq_id, &domain->iommu_bmp);
		iommu->domains[num] = NULL;
	}
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	spin_unlock_irqrestore(&iommu->lock, flags);
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}

static struct iova_domain reserved_iova_list;
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static struct lock_class_key reserved_rbtree_key;
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static int dmar_init_reserved_ranges(void)
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{
	struct pci_dev *pdev = NULL;
	struct iova *iova;
	int i;