hpt366.c 42.2 KB
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/*
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 * linux/drivers/ide/pci/hpt366.c		Version 0.51	Jun 04, 2006
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 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
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 * Portions Copyright (C) 2005-2006	MontaVista Software, Inc.
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 *
 * Thanks to HighPoint Technologies for their assistance, and hardware.
 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
 * donation of an ABit BP6 mainboard, processor, and memory acellerated
 * development and support.
 *
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 *
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 * HighPoint has its own drivers (open source except for the RAID part)
 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
 * This may be useful to anyone wanting to work on this driver, however  do not
 * trust  them too much since the code tends to become less and less meaningful
 * as the time passes... :-/
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 *
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 * Note that final HPT370 support was done by force extraction of GPL.
 *
 * - add function for getting/setting power status of drive
 * - the HPT370's state machine can get confused. reset it before each dma 
 *   xfer to prevent that from happening.
 * - reset state engine whenever we get an error.
 * - check for busmaster state at end of dma. 
 * - use new highpoint timings.
 * - detect bus speed using highpoint register.
 * - use pll if we don't have a clock table. added a 66MHz table that's
 *   just 2x the 33MHz table.
 * - removed turnaround. NOTE: we never want to switch between pll and
 *   pci clocks as the chip can glitch in those cases. the highpoint
 *   approved workaround slows everything down too much to be useful. in
 *   addition, we would have to serialize access to each chip.
 * 	Adrian Sun <a.sun@sun.com>
 *
 * add drive timings for 66MHz PCI bus,
 * fix ATA Cable signal detection, fix incorrect /proc info
 * add /proc display for per-drive PIO/DMA/UDMA mode and
 * per-channel ATA-33/66 Cable detect.
 * 	Duncan Laurie <void@sun.com>
 *
 * fixup /proc output for multiple controllers
 *	Tim Hockin <thockin@sun.com>
 *
 * On hpt366: 
 * Reset the hpt366 on error, reset on dma
 * Fix disabling Fast Interrupt hpt366.
 * 	Mike Waychison <crlf@sun.com>
 *
 * Added support for 372N clocking and clock switching. The 372N needs
 * different clocks on read/write. This requires overloading rw_disk and
 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
 * keeping me sane. 
 *		Alan Cox <alan@redhat.com>
 *
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 * - fix the clock turnaround code: it was writing to the wrong ports when
 *   called for the secondary channel, caching the current clock mode per-
 *   channel caused the cached register value to get out of sync with the
 *   actual one, the channels weren't serialized, the turnaround shouldn't
 *   be done on 66 MHz PCI bus
 * - avoid calibrating PLL twice as the second time results in a wrong PCI
 *   frequency and thus in the wrong timings for the secondary channel
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 * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
 *   as the ATA clock being used does not allow for this speed anyway
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 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
 * - HPT371/N are single channel chips, so avoid touching the primary channel
 *   which exists only virtually (there's no pins for it)
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 * - fix/remove bad/unused timing tables and use one set of tables for the whole
 *   HPT37x chip family; save space by introducing the separate transfer mode
 *   table in which the mode lookup is done
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 * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
 *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
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 * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
 *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
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 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
 *   they tamper with its fields
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 * - prefix the driver startup messages with the real chip name
 * - claim the extra 240 bytes of I/O space for all chips
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 * - optimize the rate masking/filtering and the drive list lookup code
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 * - use pci_get_slot() to get to the function 1 of HPT36x/374
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 * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting
 *   the cable type on HPT374's function 1
 * - rename all the register related variables consistently
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 * - move the interrupt twiddling code from the speedproc handlers into the
 *   init_hwif handler, also grouping all the DMA related code together there;
 *   simplify  the init_chipset handler
 * - merge two HPT37x speedproc handlers and fix the PIO timing register mask
 *   there; make HPT36x speedproc handler look the same way as the HPT37x one
 * - fix  the tuneproc handler to always set the PIO mode requested,  not the
 *   best possible one
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 *		<source@mvista.com>
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 */

#include <linux/types.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/ioport.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>

#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ide.h>

#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>

/* various tuning parameters */
#define HPT_RESET_STATE_ENGINE
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#undef	HPT_DELAY_INTERRUPT
#define HPT_SERIALIZE_IO	0
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static const char *quirk_drives[] = {
	"QUANTUM FIREBALLlct08 08",
	"QUANTUM FIREBALLP KA6.4",
	"QUANTUM FIREBALLP LM20.4",
	"QUANTUM FIREBALLP LM20.5",
	NULL
};

static const char *bad_ata100_5[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

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static u8 xfer_speeds[] = {
	XFER_UDMA_6,
	XFER_UDMA_5,
	XFER_UDMA_4,
	XFER_UDMA_3,
	XFER_UDMA_2,
	XFER_UDMA_1,
	XFER_UDMA_0,

	XFER_MW_DMA_2,
	XFER_MW_DMA_1,
	XFER_MW_DMA_0,

	XFER_PIO_4,
	XFER_PIO_3,
	XFER_PIO_2,
	XFER_PIO_1,
	XFER_PIO_0
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};

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/* Key for bus clock timings
 * 36x   37x
 * bits  bits
 * 0:3	 0:3	data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *		cycles = value + 1
 * 4:7	 4:8	data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *		cycles = value + 1
 * 8:11  9:12	cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *		register access.
 * 12:15 13:17	cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *		register access.
 * 16:18 18:20	udma_cycle_time. Clock cycles for UDMA xfer.
 * -	 21	CLK frequency: 0=ATA clock, 1=dual ATA clock.
 * 19:21 22:24	pre_high_time. Time to initialize the 1st cycle for PIO and
 *		MW DMA xfer.
 * 22:24 25:27	cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 *		task file register access.
 * 28	 28	UDMA enable.
 * 29	 29	DMA  enable.
 * 30	 30	PIO MST enable. If set, the chip is in bus master mode during
 *		PIO xfer.
 * 31	 31	FIFO enable.
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 */

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static u32 forty_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x900fd943,
	/* XFER_UDMA_5 */	0x900fd943,
	/* XFER_UDMA_4 */	0x900fd943,
	/* XFER_UDMA_3 */	0x900ad943,
	/* XFER_UDMA_2 */	0x900bd943,
	/* XFER_UDMA_1 */	0x9008d943,
	/* XFER_UDMA_0 */	0x9008d943,

	/* XFER_MW_DMA_2 */	0xa008d943,
	/* XFER_MW_DMA_1 */	0xa010d955,
	/* XFER_MW_DMA_0 */	0xa010d9fc,

	/* XFER_PIO_4 */	0xc008d963,
	/* XFER_PIO_3 */	0xc010d974,
	/* XFER_PIO_2 */	0xc010d997,
	/* XFER_PIO_1 */	0xc010d9c7,
	/* XFER_PIO_0 */	0xc018d9d9
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};

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static u32 thirty_three_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x90c9a731,
	/* XFER_UDMA_5 */	0x90c9a731,
	/* XFER_UDMA_4 */	0x90c9a731,
	/* XFER_UDMA_3 */	0x90cfa731,
	/* XFER_UDMA_2 */	0x90caa731,
	/* XFER_UDMA_1 */	0x90cba731,
	/* XFER_UDMA_0 */	0x90c8a731,

	/* XFER_MW_DMA_2 */	0xa0c8a731,
	/* XFER_MW_DMA_1 */	0xa0c8a732,	/* 0xa0c8a733 */
	/* XFER_MW_DMA_0 */	0xa0c8a797,

	/* XFER_PIO_4 */	0xc0c8a731,
	/* XFER_PIO_3 */	0xc0c8a742,
	/* XFER_PIO_2 */	0xc0d0a753,
	/* XFER_PIO_1 */	0xc0d0a7a3,	/* 0xc0d0a793 */
	/* XFER_PIO_0 */	0xc0d0a7aa	/* 0xc0d0a7a7 */
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};

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static u32 twenty_five_base_hpt36x[] = {
	/* XFER_UDMA_6 */	0x90c98521,
	/* XFER_UDMA_5 */	0x90c98521,
	/* XFER_UDMA_4 */	0x90c98521,
	/* XFER_UDMA_3 */	0x90cf8521,
	/* XFER_UDMA_2 */	0x90cf8521,
	/* XFER_UDMA_1 */	0x90cb8521,
	/* XFER_UDMA_0 */	0x90cb8521,

	/* XFER_MW_DMA_2 */	0xa0ca8521,
	/* XFER_MW_DMA_1 */	0xa0ca8532,
	/* XFER_MW_DMA_0 */	0xa0ca8575,

	/* XFER_PIO_4 */	0xc0ca8521,
	/* XFER_PIO_3 */	0xc0ca8532,
	/* XFER_PIO_2 */	0xc0ca8542,
	/* XFER_PIO_1 */	0xc0d08572,
	/* XFER_PIO_0 */	0xc0d08585
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};

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static u32 thirty_three_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x12446231,	/* 0x12646231 ?? */
	/* XFER_UDMA_5 */	0x12446231,
	/* XFER_UDMA_4 */	0x12446231,
	/* XFER_UDMA_3 */	0x126c6231,
	/* XFER_UDMA_2 */	0x12486231,
	/* XFER_UDMA_1 */	0x124c6233,
	/* XFER_UDMA_0 */	0x12506297,

	/* XFER_MW_DMA_2 */	0x22406c31,
	/* XFER_MW_DMA_1 */	0x22406c33,
	/* XFER_MW_DMA_0 */	0x22406c97,

	/* XFER_PIO_4 */	0x06414e31,
	/* XFER_PIO_3 */	0x06414e42,
	/* XFER_PIO_2 */	0x06414e53,
	/* XFER_PIO_1 */	0x06814e93,
	/* XFER_PIO_0 */	0x06814ea7
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};

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static u32 fifty_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x12848242,
	/* XFER_UDMA_5 */	0x12848242,
	/* XFER_UDMA_4 */	0x12ac8242,
	/* XFER_UDMA_3 */	0x128c8242,
	/* XFER_UDMA_2 */	0x120c8242,
	/* XFER_UDMA_1 */	0x12148254,
	/* XFER_UDMA_0 */	0x121882ea,

	/* XFER_MW_DMA_2 */	0x22808242,
	/* XFER_MW_DMA_1 */	0x22808254,
	/* XFER_MW_DMA_0 */	0x228082ea,

	/* XFER_PIO_4 */	0x0a81f442,
	/* XFER_PIO_3 */	0x0a81f443,
	/* XFER_PIO_2 */	0x0a81f454,
	/* XFER_PIO_1 */	0x0ac1f465,
	/* XFER_PIO_0 */	0x0ac1f48a
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};

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static u32 sixty_six_base_hpt37x[] = {
	/* XFER_UDMA_6 */	0x1c869c62,
	/* XFER_UDMA_5 */	0x1cae9c62,	/* 0x1c8a9c62 */
	/* XFER_UDMA_4 */	0x1c8a9c62,
	/* XFER_UDMA_3 */	0x1c8e9c62,
	/* XFER_UDMA_2 */	0x1c929c62,
	/* XFER_UDMA_1 */	0x1c9a9c62,
	/* XFER_UDMA_0 */	0x1c829c62,

	/* XFER_MW_DMA_2 */	0x2c829c62,
	/* XFER_MW_DMA_1 */	0x2c829c66,
	/* XFER_MW_DMA_0 */	0x2c829d2e,

	/* XFER_PIO_4 */	0x0c829c62,
	/* XFER_PIO_3 */	0x0c829c84,
	/* XFER_PIO_2 */	0x0c829ca6,
	/* XFER_PIO_1 */	0x0d029d26,
	/* XFER_PIO_0 */	0x0d029d5e
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};

#define HPT366_DEBUG_DRIVE_INFO		0
#define HPT374_ALLOW_ATA133_6		0
#define HPT371_ALLOW_ATA133_6		0
#define HPT302_ALLOW_ATA133_6		0
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#define HPT372_ALLOW_ATA133_6		0
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#define HPT370_ALLOW_ATA100_5		0
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#define HPT366_ALLOW_ATA66_4		1
#define HPT366_ALLOW_ATA66_3		1
#define HPT366_MAX_DEVS			8

#define F_LOW_PCI_33	0x23
#define F_LOW_PCI_40	0x29
#define F_LOW_PCI_50	0x2d
#define F_LOW_PCI_66	0x42

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/*
 *	Hold all the highpoint quirks and revision information in one
 *	place.
 */
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struct hpt_info
{
	u8 max_mode;		/* Speeds allowed */
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	u8 revision;		/* Chipset revision */
	u8 flags;		/* Chipset properties */
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#define PLL_MODE	1
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#define IS_3xxN 	2
#define PCI_66MHZ	4
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				/* Speed table */
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	u32 *speed;
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};

/*
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 *	This wants fixing so that we do everything not by revision
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 *	(which breaks on the newest chips) but by creating an
 *	enumeration of chip variants and using that
 */

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static __devinit u8 hpt_revision(struct pci_dev *dev)
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{
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	u8 rev = 0;

	pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
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	switch(dev->device) {
		/* Remap new 372N onto 372 */
		case PCI_DEVICE_ID_TTI_HPT372N:
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			rev = PCI_DEVICE_ID_TTI_HPT372;
			break;
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		case PCI_DEVICE_ID_TTI_HPT374:
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			rev = PCI_DEVICE_ID_TTI_HPT374;
			break;
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		case PCI_DEVICE_ID_TTI_HPT371:
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			rev = PCI_DEVICE_ID_TTI_HPT371;
			break;
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		case PCI_DEVICE_ID_TTI_HPT302:
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			rev = PCI_DEVICE_ID_TTI_HPT302;
			break;
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		case PCI_DEVICE_ID_TTI_HPT372:
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			rev = PCI_DEVICE_ID_TTI_HPT372;
			break;
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		default:
			break;
	}
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	return rev;
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}

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static int check_in_drive_list(ide_drive_t *drive, const char **list)
{
	struct hd_driveid *id = drive->id;

	while (*list)
		if (!strcmp(*list++,id->model))
			return 1;
	return 0;
}
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static u8 hpt3xx_ratemask(ide_drive_t *drive)
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{
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	struct hpt_info *info	= ide_get_hwifdata(HWIF(drive));
	u8 mode			= info->max_mode;

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	if (!eighty_ninty_three(drive) && mode)
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		mode = min(mode, (u8)1);
	return mode;
}

/*
 *	Note for the future; the SATA hpt37x we must set
 *	either PIO or UDMA modes 0,4,5
 */
 
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static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
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{
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	struct hpt_info *info	= ide_get_hwifdata(HWIF(drive));
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	u8 mode			= hpt3xx_ratemask(drive);

	if (drive->media != ide_disk)
		return min(speed, (u8)XFER_PIO_4);

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	switch (mode) {
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		case 0x04:
			speed = min(speed, (u8)XFER_UDMA_6);
			break;
		case 0x03:
			speed = min(speed, (u8)XFER_UDMA_5);
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			if (info->revision >= 5)
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				break;
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			if (!check_in_drive_list(drive, bad_ata100_5))
				goto check_bad_ata33;
			/* fall thru */
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		case 0x02:
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			speed = min_t(u8, speed, XFER_UDMA_4);
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	/*
	 * CHECK ME, Does this need to be set to 5 ??
	 */
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			if (info->revision >= 3)
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				goto check_bad_ata33;
			if (HPT366_ALLOW_ATA66_4 &&
			    !check_in_drive_list(drive, bad_ata66_4))
				goto check_bad_ata33;

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			speed = min_t(u8, speed, XFER_UDMA_3);
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			if (HPT366_ALLOW_ATA66_3 &&
			    !check_in_drive_list(drive, bad_ata66_3))
				goto check_bad_ata33;
			/* fall thru */
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		case 0x01:
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			speed = min_t(u8, speed, XFER_UDMA_2);
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		check_bad_ata33:
 			if (info->revision >= 4)
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				break;
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			if (!check_in_drive_list(drive, bad_ata33))
				break;
			/* fall thru */
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		case 0x00:
		default:
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			speed = min_t(u8, speed, XFER_MW_DMA_2);
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			break;
	}
	return speed;
}

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static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
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{
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	int i;

	/*
	 * Lookup the transfer mode table to get the index into
	 * the timing table.
	 *
	 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
	 */
	for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
		if (xfer_speeds[i] == speed)
			break;
	return chipset_table[i];
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}

static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
{
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	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev  *dev	= hwif->pci_dev;
	struct hpt_info	*info	= ide_get_hwifdata (hwif);
	u8  speed		= hpt3xx_ratefilter(drive, xferspeed);
	u8  itr_addr		= drive->dn ? 0x44 : 0x40;
	u32 itr_mask		= (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000;
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	u32 new_itr		= pci_bus_clock_list(speed, info->speed);
	u32 old_itr		= 0;
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	/*
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	 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
	 * to avoid problems handling I/O errors later
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	 */
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	pci_read_config_dword(dev, itr_addr, &old_itr);
	new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
	new_itr &= ~0xc0000000;
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	pci_write_config_dword(dev, itr_addr, new_itr);
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	return ide_config_drive_speed(drive, speed);
}

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static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
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{
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	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev  *dev	= hwif->pci_dev;
	struct hpt_info	*info	= ide_get_hwifdata (hwif);
	u8  speed		= hpt3xx_ratefilter(drive, xferspeed);
	u8  itr_addr		= 0x40 + (drive->dn * 4);
	u32 itr_mask		= (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
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	u32 new_itr		= pci_bus_clock_list(speed, info->speed);
	u32 old_itr		= 0;
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	pci_read_config_dword(dev, itr_addr, &old_itr);
	new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
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	if (speed < XFER_MW_DMA_0)
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		new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
	pci_write_config_dword(dev, itr_addr, new_itr);
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	return ide_config_drive_speed(drive, speed);
}

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static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
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{
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	ide_hwif_t *hwif	= HWIF(drive);
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	struct hpt_info	*info	= ide_get_hwifdata(hwif);
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	if (info->revision >= 3)
		return hpt37x_tune_chipset(drive, speed);
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	else	/* hpt368: hpt_minimum_revision(dev, 2) */
		return hpt36x_tune_chipset(drive, speed);
}

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static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
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{
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	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
	(void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
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}

/*
 * This allows the configuration of ide_pci chipset registers
 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
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 * after the drive is reported by the OS.  Initially designed for
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 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 *
 */
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static int config_chipset_for_dma(ide_drive_t *drive)
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{
	u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
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	ide_hwif_t *hwif	= HWIF(drive);
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	struct hpt_info	*info	= ide_get_hwifdata(hwif);
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	if (!speed)
		return 0;

	/* If we don't have any timings we can't do a lot */
	if (info->speed == NULL)
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		return 0;

	(void) hpt3xx_tune_chipset(drive, speed);
	return ide_dma_enable(drive);
}

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static int hpt3xx_quirkproc(ide_drive_t *drive)
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{
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	struct hd_driveid *id	= drive->id;
	const  char **list	= quirk_drives;

	while (*list)
		if (strstr(id->model, *list++))
			return 1;
	return 0;
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}

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static void hpt3xx_intrproc(ide_drive_t *drive)
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{
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	ide_hwif_t *hwif = HWIF(drive);
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	if (drive->quirk_list)
		return;
	/* drives in the quirk_list may not like intr setups/cleanups */
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	hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
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}

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static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
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{
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	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev	*dev	= hwif->pci_dev;
	struct hpt_info *info	= ide_get_hwifdata(hwif);
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	if (drive->quirk_list) {
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		if (info->revision >= 3) {
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			u8 scr1 = 0;

			pci_read_config_byte(dev, 0x5a, &scr1);
			if (((scr1 & 0x10) >> 4) != mask) {
				if (mask)
					scr1 |=  0x10;
				else
					scr1 &= ~0x10;
				pci_write_config_byte(dev, 0x5a, scr1);
			}
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		} else {
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			if (mask)
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				disable_irq(hwif->irq);
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			else
				enable_irq (hwif->irq);
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		}
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	} else
		hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
			   IDE_CONTROL_REG);
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}

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static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
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{
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	ide_hwif_t *hwif	= HWIF(drive);
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	struct hd_driveid *id	= drive->id;

	drive->init_speed = 0;

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	if ((id->capability & 1) && drive->autodma) {
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		if (ide_use_dma(drive) && config_chipset_for_dma(drive))
			return hwif->ide_dma_on(drive);
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		goto fast_ata_pio;

	} else if ((id->capability & 8) || (id->field_valid & 2)) {
fast_ata_pio:
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		hpt3xx_tune_drive(drive, 255);
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		return hwif->ide_dma_off_quietly(drive);
	}
	/* IORDY not supported */
	return 0;
}

/*
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 * This is specific to the HPT366 UDMA chipset
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 * by HighPoint|Triones Technologies, Inc.
 */
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static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
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{
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	struct pci_dev *dev = HWIF(drive)->pci_dev;
	u8 mcr1 = 0, mcr3 = 0, scr1 = 0;

	pci_read_config_byte(dev, 0x50, &mcr1);
	pci_read_config_byte(dev, 0x52, &mcr3);
	pci_read_config_byte(dev, 0x5a, &scr1);
	printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
		drive->name, __FUNCTION__, mcr1, mcr3, scr1);
	if (scr1 & 0x10)
		pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
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	return __ide_dma_lostirq(drive);
}

static void hpt370_clear_engine (ide_drive_t *drive)
{
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	ide_hwif_t *hwif = HWIF(drive);

	pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
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	udelay(10);
}

static void hpt370_ide_dma_start(ide_drive_t *drive)
{
#ifdef HPT_RESET_STATE_ENGINE
	hpt370_clear_engine(drive);
#endif
	ide_dma_start(drive);
}

static int hpt370_ide_dma_end (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u8 dma_stat		= hwif->INB(hwif->dma_status);

	if (dma_stat & 0x01) {
		/* wait a little */
		udelay(20);
		dma_stat = hwif->INB(hwif->dma_status);
	}
	if ((dma_stat & 0x01) != 0) 
		/* fallthrough */
		(void) HWIF(drive)->ide_dma_timeout(drive);

	return __ide_dma_end(drive);
}

static void hpt370_lostirq_timeout (ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
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	u8 bfifo = 0;
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	u8 dma_stat = 0, dma_cmd = 0;

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	pci_read_config_byte(HWIF(drive)->pci_dev, hwif->select_data + 2, &bfifo);
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	printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
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	hpt370_clear_engine(drive);
	/* get dma command mode */
	dma_cmd = hwif->INB(hwif->dma_command);
	/* stop dma */
	hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
	dma_stat = hwif->INB(hwif->dma_status);
	/* clear errors */
	hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
}

static int hpt370_ide_dma_timeout (ide_drive_t *drive)
{
	hpt370_lostirq_timeout(drive);
	hpt370_clear_engine(drive);
	return __ide_dma_timeout(drive);
}

static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
{
	hpt370_lostirq_timeout(drive);
	hpt370_clear_engine(drive);
	return __ide_dma_lostirq(drive);
}

/* returns 1 if DMA IRQ issued, 0 otherwise */
static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
{
	ide_hwif_t *hwif	= HWIF(drive);
	u16 bfifo		= 0;
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	u8  dma_stat;
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	pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
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	if (bfifo & 0x1FF) {
//		printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
		return 0;
	}

	dma_stat = hwif->INB(hwif->dma_status);
	/* return 1 if INTR asserted */
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	if (dma_stat & 4)
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		return 1;

	if (!drive->waiting_for_dma)
		printk(KERN_WARNING "%s: (%s) called while not waiting\n",
				drive->name, __FUNCTION__);
	return 0;
}

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static int hpt374_ide_dma_end(ide_drive_t *drive)
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{
	ide_hwif_t *hwif	= HWIF(drive);
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	struct pci_dev	*dev	= hwif->pci_dev;
	u8 mcr	= 0, mcr_addr	= hwif->select_data;
	u8 bwsr = 0, mask	= hwif->channel ? 0x02 : 0x01;

	pci_read_config_byte(dev, 0x6a, &bwsr);
	pci_read_config_byte(dev, mcr_addr, &mcr);
	if (bwsr & mask)
		pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
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	return __ide_dma_end(drive);
}

/**
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 *	hpt3xxn_set_clock	-	perform clock switching dance
 *	@hwif: hwif to switch
 *	@mode: clocking mode (0x21 for write, 0x23 otherwise)
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 *
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 *	Switch the DPLL clock on the HPT3xxN devices. This is a	right mess.
 *	NOTE: avoid touching the disabled primary channel on HPT371N -- it
 *	doesn't physically exist anyway...
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 */
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static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
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{
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	u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);

	if ((scr2 & 0x7f) == mode)
		return;

	/* MISC. control register 1 has the channel enable bit... */
	mcr1 = hwif->INB(hwif->dma_master + 0x70);

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	/* Tristate the bus */
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	if (mcr1 & 0x04)
		hwif->OUTB(0x80, hwif->dma_master + 0x73);
	hwif->OUTB(0x80, hwif->dma_master + 0x77);

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	/* Switch clock and reset channels */
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	hwif->OUTB(mode, hwif->dma_master + 0x7b);
	hwif->OUTB(0xc0, hwif->dma_master + 0x79);

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	/* Reset state machines */
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	if (mcr1 & 0x04)
		hwif->OUTB(0x37, hwif->dma_master + 0x70);
	hwif->OUTB(0x37, hwif->dma_master + 0x74);

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	/* Complete reset */
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	hwif->OUTB(0x00, hwif->dma_master + 0x79);

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	/* Reconnect channels to bus */
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	if (mcr1 & 0x04)
		hwif->OUTB(0x00, hwif->dma_master + 0x73);
	hwif->OUTB(0x00, hwif->dma_master + 0x77);
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}

/**
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 *	hpt3xxn_rw_disk		-	prepare for I/O
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 *	@drive: drive for command
 *	@rq: block request structure
 *
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 *	We need it because of the clock switching.
 */

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static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
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{
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	ide_hwif_t *hwif	= HWIF(drive);
	u8 wantclock		= rq_data_dir(rq) ? 0x23 : 0x21;
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	hpt3xxn_set_clock(hwif, wantclock);
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}

/* 
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 * Set/get power state for a drive.
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 * NOTE: affects both drives on each channel.
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 *
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 * When we turn the power back on, we need to re-initialize things.
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 */
#define TRISTATE_BIT  0x8000
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static int hpt3xx_busproc(ide_drive_t *drive, int state)
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{
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	ide_hwif_t *hwif	= HWIF(drive);
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	struct pci_dev *dev	= hwif->pci_dev;
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	u8  mcr_addr		= hwif->select_data + 2;
	u8  resetmask		= hwif->channel ? 0x80 : 0x40;
	u8  bsr2		= 0;
	u16 mcr			= 0;
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	hwif->bus_state = state;

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	/* Grab the status. */
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	pci_read_config_word(dev, mcr_addr, &mcr);
	pci_read_config_byte(dev, 0x59, &bsr2);
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	/*
	 * Set the state. We don't set it if we don't need to do so.
	 * Make sure that the drive knows that it has failed if it's off.
	 */
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	switch (state) {
	case BUSSTATE_ON:
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		if (!(bsr2 & resetmask))
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			return 0;
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		hwif->drives[0].failures = hwif->drives[1].failures = 0;

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		pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
		pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
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		return 0;
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	case BUSSTATE_OFF:
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		if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
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			return 0;
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		mcr &= ~TRISTATE_BIT;
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		break;
	case BUSSTATE_TRISTATE:
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		if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
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			return 0;
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		mcr |= TRISTATE_BIT;
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		break;
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	default:
		return -EINVAL;
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	}

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	hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
	hwif->drives[1].failures = hwif->drives[1].max_failures + 1;

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	pci_write_config_word(dev, mcr_addr, mcr);
	pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
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	return 0;
}

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static void __devinit hpt366_clocking(ide_hwif_t *hwif)
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{
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	u32 itr1	= 0;
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	struct hpt_info *info = ide_get_hwifdata(hwif);

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	pci_read_config_dword(hwif->pci_dev, 0x40, &itr1);
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	/* detect bus speed by looking at control reg timing: */
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	switch((itr1 >> 8) & 7) {
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		case 5:
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			info->speed = forty_base_hpt36x;
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			break;
		case 9:
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			info->speed = twenty_five_base_hpt36x;
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			break;
		case 7:
		default:
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			info->speed = thirty_three_base_hpt36x;
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			break;
	}
}

static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
{
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	struct hpt_info *info	= ide_get_hwifdata(hwif);
	struct pci_dev  *dev	= hwif->pci_dev;
	char *name		= hwif->cds->name;
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	int adjust, i;
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	u16 freq = 0;
	u32 pll, temp = 0;
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	u8  scr2 = 0, mcr1 = 0;
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	/*
	 * default to pci clock. make sure MA15/16 are set to output
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	 * to prevent drives having problems with 40-pin cables. Needed
	 * for some drives such as IBM-DTLA which will not enter ready
	 * state on reset when PDIAG is a input.
	 *
	 * ToDo: should we set 0x21 when using PLL mode ?
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	 */
	pci_write_config_byte(dev, 0x5b, 0x23);

	/*
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	 * We'll have to read f_CNT value in order to determine
	 * the PCI clock frequency according to the following ratio:
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	 *
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	 * f_CNT = Fpci * 192 / Fdpll
	 *
	 * First try reading the register in which the HighPoint BIOS
	 * saves f_CNT value before  reprogramming the DPLL from its
	 * default setting (which differs for the various chips).
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	 * NOTE: This register is only accessible via I/O space.
	 *
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	 * In case the signature check fails, we'll have to resort to
	 * reading the f_CNT register itself in hopes that nobody has
	 * touched the DPLL yet...
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	 */
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	temp = inl(pci_resource_start(dev, 4) + 0x90);
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	if ((temp & 0xFFFFF000) != 0xABCDE000) {
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		printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
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		/* Calculate the average value of f_CNT */
		for (temp = i = 0; i < 128; i++) {
			pci_read_config_word(dev, 0x78, &freq);
			temp += freq & 0x1ff;
			mdelay(1);
		}
		freq = temp / 128;
	} else
		freq = temp & 0x1ff;

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	/*
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	 * HPT3xxN chips use different PCI clock information.
	 * Currently we always set up the PLL for them.
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	 */
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	if (info->flags & IS_3xxN) {
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		if(freq < 0x55)
			pll = F_LOW_PCI_33;
		else if(freq < 0x70)
			pll = F_LOW_PCI_40;
		else if(freq < 0x7F)
			pll = F_LOW_PCI_50;
		else
			pll = F_LOW_PCI_66;
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	} else {
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		if(freq < 0x9C)
			pll = F_LOW_PCI_33;
		else if(freq < 0xb0)
			pll = F_LOW_PCI_40;
		else if(freq <0xc8)
			pll = F_LOW_PCI_50;
		else
			pll = F_LOW_PCI_66;
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	}
	printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
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	if (!(info->flags & IS_3xxN)) {
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		if (pll == F_LOW_PCI_33) {
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			info->speed = thirty_three_base_hpt37x;
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			printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
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		} else if (pll == F_LOW_PCI_40) {
			/* Unsupported */
		} else if (pll == F_LOW_PCI_50) {
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			info->speed = fifty_base_hpt37x;
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			printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
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		} else {
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			info->speed = sixty_six_base_hpt37x;
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			printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
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		}
	}
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	if (pll == F_LOW_PCI_66)
		info->flags |= PCI_66MHZ;

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	/*
	 * only try the pll if we don't have a table for the clock
	 * speed that we're running at. NOTE: the internal PLL will
	 * result in slow reads when using a 33MHz PCI clock. we also
	 * don't like to use the PLL because it will cause glitches
	 * on PRST/SRST when the HPT state engine gets reset.
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	 *
	 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
	 * 372 device so we can get ATA133 support
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	 */
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	if (info->speed)
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		goto init_hpt37X_done;
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	info->flags |= PLL_MODE;
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	/*
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	 * Adjust the PLL based upon the PCI clock, enable it, and
	 * wait for stabilization...
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	 */
	adjust = 0;
	freq = (pll < F_LOW_PCI_50) ? 2 : 4;
	while (adjust++ < 6) {
		pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
				       pll | 0x100);

		/* wait for clock stabilization */
		for (i = 0; i < 0x50000; i++) {
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			pci_read_config_byte(dev, 0x5b, &scr2);
			if (scr2 & 0x80) {
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				/* spin looking for the clock to destabilize */
				for (i = 0; i < 0x1000; ++i) {
					pci_read_config_byte(dev, 0x5b, 
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							     &scr2);
					if ((scr2 & 0x80) == 0)
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						goto pll_recal;
				}
				pci_read_config_dword(dev, 0x5c, &pll);
				pci_write_config_dword(dev, 0x5c, 
						       pll & ~0x100);
				pci_write_config_byte(dev, 0x5b, 0x21);
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				info->speed = fifty_base_hpt37x;
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				printk("%s: using 50MHz internal PLL\n", name);
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				goto init_hpt37X_done;
			}
		}
pll_recal:
		if (adjust & 1)
			pll -= (adjust >> 1);
		else
			pll += (adjust >> 1);
	} 

init_hpt37X_done:
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	if (!info->speed)
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		printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
		       name, pll, freq);
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	/*
	 * Reset the state engines.
	 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
	 */
	pci_read_config_byte(dev, 0x50, &mcr1);
	if (mcr1 & 0x04)
		pci_write_config_byte(dev, 0x50, 0x37);
	pci_write_config_byte(dev, 0x54, 0x37);
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	udelay(100);
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}

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static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
{
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	/*
	 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
	 * We don't seem to be using it.
	 */
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	if (dev->resource[PCI_ROM_RESOURCE].start)
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		pci_write_config_dword(dev, PCI_ROM_ADDRESS,
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			dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);

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	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
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	if (hpt_revision(dev) >= 3) {
		u8 scr1 = 0;
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		/* Interrupt force enable. */
		pci_read_config_byte(dev, 0x5a, &scr1);
		if (scr1 & 0x10)
			pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
	}
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	return dev->irq;
}

static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
{
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	struct pci_dev	*dev		= hwif->pci_dev;
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	struct hpt_info *info		= ide_get_hwifdata(hwif);
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	int serialize			= HPT_SERIALIZE_IO;
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	u8  scr1 = 0, ata66		= (hwif->channel) ? 0x01 : 0x02;
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	u8  new_mcr, old_mcr 		= 0;
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	/* Cache the channel's MISC. control registers' offset */
	hwif->select_data		= hwif->channel ? 0x54 : 0x50;

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	hwif->tuneproc			= &hpt3xx_tune_drive;
	hwif->speedproc			= &hpt3xx_tune_chipset;
	hwif->quirkproc			= &hpt3xx_quirkproc;
	hwif->intrproc			= &hpt3xx_intrproc;
	hwif->maskproc			= &hpt3xx_maskproc;
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	hwif->busproc			= &hpt3xx_busproc;

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	/*
	 * HPT3xxN chips have some complications:
	 *
	 * - on 33 MHz PCI we must clock switch
	 * - on 66 MHz PCI we must NOT use the PCI clock
	 */
	if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
		/*
		 * Clock is shared between the channels,
		 * so we'll have to serialize them... :-(
		 */
		serialize = 1;
		hwif->rw_disk = &hpt3xxn_rw_disk;
	}
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	/* Serialize access to this device if needed */
	if (serialize && hwif->mate)
		hwif->serialized = hwif->mate->serialized = 1;

	/*
	 * Disable the "fast interrupt" prediction.  Don't hold off
	 * on interrupts. (== 0x01 despite what the docs say)
	 */
	pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);

	if (info->revision >= 5)		/* HPT372 and newer   */
		new_mcr = old_mcr & ~0x07;
	else if (info->revision >= 3) {		/* HPT370 and HPT370A */
		new_mcr = old_mcr;
		new_mcr &= ~0x02;

#ifdef HPT_DELAY_INTERRUPT
		new_mcr &= ~0x01;
#else
		new_mcr |=  0x01;
#endif
	} else					/* HPT366 and HPT368  */
		new_mcr = old_mcr & ~0x80;

	if (new_mcr != old_mcr)
		pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);

	if (!hwif->dma_base) {
		hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
		return;
	}

	hwif->ultra_mask = 0x7f;
	hwif->mwdma_mask = 0x07;

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	/*
	 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
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	 * address lines to access an external EEPROM.  To read valid
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	 * cable detect state the pins must be enabled as inputs.
	 */
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	if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
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		/*
		 * HPT374 PCI function 1
		 * - set bit 15 of reg 0x52 to enable TCBLID as input
		 * - set bit 15 of reg 0x56 to enable FCBLID as input
		 */
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		u8  mcr_addr = hwif->select_data + 2;
		u16 mcr;

		pci_read_config_word (dev, mcr_addr, &mcr);
		pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
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		/* now read cable id register */
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		pci_read_config_byte (dev, 0x5a, &scr1);
		pci_write_config_word(dev, mcr_addr, mcr);
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	} else if (info->revision >= 3) {
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		/*
		 * HPT370/372 and 374 pcifn 0
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		 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
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		 */
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		u8 scr2 = 0;
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		pci_read_config_byte (dev, 0x5b, &scr2);
		pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
		/* now read cable id register */
		pci_read_config_byte (dev, 0x5a, &scr1);
		pci_write_config_byte(dev, 0x5b,  scr2);
	} else
		pci_read_config_byte (dev, 0x5a, &scr1);
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	if (!hwif->udma_four)
		hwif->udma_four = (scr1 & ata66) ? 0 : 1;
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	hwif->ide_dma_check		= &hpt366_config_drive_xfer_rate;
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	if (info->revision >= 5) {
		hwif->ide_dma_test_irq	= &hpt374_ide_dma_test_irq;
		hwif->ide_dma_end	= &hpt374_ide_dma_end;
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	} else if (info->revision >= 3) {
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		hwif->dma_start 	= &hpt370_ide_dma_start;
		hwif->ide_dma_end	= &hpt370_ide_dma_end;
		hwif->ide_dma_timeout	= &hpt370_ide_dma_timeout;
		hwif->ide_dma_lostirq	= &hpt370_ide_dma_lostirq;
	} else
		hwif->ide_dma_lostirq	= &hpt366_ide_dma_lostirq;
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	if (!noautodma)
		hwif->autodma = 1;
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	hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
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}

static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
{
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	struct pci_dev	*dev		= hwif->pci_dev;
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	struct hpt_info	*info		= ide_get_hwifdata(hwif);
	u8 masterdma	= 0, slavedma	= 0;
	u8 dma_new	= 0, dma_old	= 0;
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	unsigned long flags;

	if (!dmabase)
		return;