i915_gem.c 103 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#include <linux/shmem_fs.h>
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
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static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
						    unsigned alignment,
						    bool map_and_fenceable);
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static int i915_gem_phys_pwrite(struct drm_device *dev,
				struct drm_i915_gem_object *obj,
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				struct drm_i915_gem_pwrite *args,
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				struct drm_file *file);
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static void i915_gem_write_fence(struct drm_device *dev, int reg,
				 struct drm_i915_gem_object *obj);
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
					 struct drm_i915_fence_reg *fence,
					 bool enable);

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static int i915_gem_inactive_shrink(struct shrinker *shrinker,
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				    struct shrink_control *sc);
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static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
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static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
{
	if (obj->tiling_mode)
		i915_gem_release_mmap(obj);

	/* As we do not have an associated fence register, we will force
	 * a tiling change if we ever need to acquire one.
	 */
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	obj->fence_dirty = false;
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	obj->fence_reg = I915_FENCE_REG_NONE;
}

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/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
				  size_t size)
{
	dev_priv->mm.object_count++;
	dev_priv->mm.object_memory += size;
}

static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
				     size_t size)
{
	dev_priv->mm.object_count--;
	dev_priv->mm.object_memory -= size;
}

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static int
i915_gem_wait_for_error(struct drm_device *dev)
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{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct completion *x = &dev_priv->error_completion;
	unsigned long flags;
	int ret;

	if (!atomic_read(&dev_priv->mm.wedged))
		return 0;

	ret = wait_for_completion_interruptible(x);
	if (ret)
		return ret;

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	if (atomic_read(&dev_priv->mm.wedged)) {
		/* GPU is hung, bump the completion count to account for
		 * the token we just consumed so that we never hit zero and
		 * end up waiting upon a subsequent completion event that
		 * will never happen.
		 */
		spin_lock_irqsave(&x->wait.lock, flags);
		x->done++;
		spin_unlock_irqrestore(&x->wait.lock, flags);
	}
	return 0;
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}

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int i915_mutex_lock_interruptible(struct drm_device *dev)
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{
	int ret;

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	ret = i915_gem_wait_for_error(dev);
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	if (ret)
		return ret;

	ret = mutex_lock_interruptible(&dev->struct_mutex);
	if (ret)
		return ret;

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	WARN_ON(i915_verify_lists(dev));
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	return 0;
}
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static inline bool
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i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
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{
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	return !obj->active;
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}

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int
i915_gem_init_ioctl(struct drm_device *dev, void *data,
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		    struct drm_file *file)
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{
	struct drm_i915_gem_init *args = data;
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	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return -ENODEV;

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	if (args->gtt_start >= args->gtt_end ||
	    (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
		return -EINVAL;
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	/* GEM with user mode setting was never supported on ilk and later. */
	if (INTEL_INFO(dev)->gen >= 5)
		return -ENODEV;

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	mutex_lock(&dev->struct_mutex);
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	i915_gem_init_global_gtt(dev, args->gtt_start,
				 args->gtt_end, args->gtt_end);
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	mutex_unlock(&dev->struct_mutex);

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	return 0;
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}

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int
i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
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			    struct drm_file *file)
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{
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct drm_i915_gem_get_aperture *args = data;
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	struct drm_i915_gem_object *obj;
	size_t pinned;
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	pinned = 0;
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	mutex_lock(&dev->struct_mutex);
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	list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
		if (obj->pin_count)
			pinned += obj->gtt_space->size;
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	mutex_unlock(&dev->struct_mutex);
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	args->aper_size = dev_priv->mm.gtt_total;
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	args->aper_available_size = args->aper_size - pinned;
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	return 0;
}

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static int
i915_gem_create(struct drm_file *file,
		struct drm_device *dev,
		uint64_t size,
		uint32_t *handle_p)
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{
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	struct drm_i915_gem_object *obj;
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	int ret;
	u32 handle;
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	size = roundup(size, PAGE_SIZE);
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	if (size == 0)
		return -EINVAL;
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	/* Allocate the new object */
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	obj = i915_gem_alloc_object(dev, size);
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	if (obj == NULL)
		return -ENOMEM;

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	ret = drm_gem_handle_create(file, &obj->base, &handle);
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	if (ret) {
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		drm_gem_object_release(&obj->base);
		i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
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		kfree(obj);
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		return ret;
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	}
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	/* drop reference from allocate - handle holds it now */
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	drm_gem_object_unreference(&obj->base);
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	trace_i915_gem_object_create(obj);

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	*handle_p = handle;
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	return 0;
}

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int
i915_gem_dumb_create(struct drm_file *file,
		     struct drm_device *dev,
		     struct drm_mode_create_dumb *args)
{
	/* have to work out size/pitch and return them */
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	args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
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	args->size = args->pitch * args->height;
	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

int i915_gem_dumb_destroy(struct drm_file *file,
			  struct drm_device *dev,
			  uint32_t handle)
{
	return drm_gem_handle_delete(file, handle);
}

/**
 * Creates a new mm object and returns a handle to it.
 */
int
i915_gem_create_ioctl(struct drm_device *dev, void *data,
		      struct drm_file *file)
{
	struct drm_i915_gem_create *args = data;
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	return i915_gem_create(file, dev,
			       args->size, &args->handle);
}

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static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
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{
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	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
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	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
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		obj->tiling_mode != I915_TILING_NONE;
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}

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static inline int
__copy_to_user_swizzled(char __user *cpu_vaddr,
			const char *gpu_vaddr, int gpu_offset,
			int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_to_user(cpu_vaddr + cpu_offset,
				     gpu_vaddr + swizzled_gpu_offset,
				     this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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static inline int
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__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
			  const char __user *cpu_vaddr,
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			  int length)
{
	int ret, cpu_offset = 0;

	while (length > 0) {
		int cacheline_end = ALIGN(gpu_offset + 1, 64);
		int this_length = min(cacheline_end - gpu_offset, length);
		int swizzled_gpu_offset = gpu_offset ^ 64;

		ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
				       cpu_vaddr + cpu_offset,
				       this_length);
		if (ret)
			return ret + length;

		cpu_offset += this_length;
		gpu_offset += this_length;
		length -= this_length;
	}

	return 0;
}

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/* Per-page copy function for the shmem pread fastpath.
 * Flushes invalid cachelines before reading the target if
 * needs_clflush is set. */
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static int
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shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

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	if (unlikely(page_do_bit17_swizzling))
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		return -EINVAL;

	vaddr = kmap_atomic(page);
	if (needs_clflush)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_to_user_inatomic(user_data,
				      vaddr + shmem_page_offset,
				      page_length);
	kunmap_atomic(vaddr);

	return ret;
}

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static void
shmem_clflush_swizzled_range(char *addr, unsigned long length,
			     bool swizzled)
{
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	if (unlikely(swizzled)) {
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		unsigned long start = (unsigned long) addr;
		unsigned long end = (unsigned long) addr + length;

		/* For swizzling simply ensure that we always flush both
		 * channels. Lame, but simple and it works. Swizzled
		 * pwrite/pread is far from a hotpath - current userspace
		 * doesn't use it at all. */
		start = round_down(start, 128);
		end = round_up(end, 128);

		drm_clflush_virt_range((void *)start, end - start);
	} else {
		drm_clflush_virt_range(addr, length);
	}

}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
static int
shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
		 char __user *user_data,
		 bool page_do_bit17_swizzling, bool needs_clflush)
{
	char *vaddr;
	int ret;

	vaddr = kmap(page);
	if (needs_clflush)
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	if (page_do_bit17_swizzling)
		ret = __copy_to_user_swizzled(user_data,
					      vaddr, shmem_page_offset,
					      page_length);
	else
		ret = __copy_to_user(user_data,
				     vaddr + shmem_page_offset,
				     page_length);
	kunmap(page);

	return ret;
}

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static int
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i915_gem_shmem_pread(struct drm_device *dev,
		     struct drm_i915_gem_object *obj,
		     struct drm_i915_gem_pread *args,
		     struct drm_file *file)
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{
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	struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
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	char __user *user_data;
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	ssize_t remain;
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	loff_t offset;
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	int shmem_page_offset, page_length, ret = 0;
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	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
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	int hit_slowpath = 0;
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	int prefaulted = 0;
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	int needs_clflush = 0;
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	int release_page;
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	user_data = (char __user *) (uintptr_t) args->data_ptr;
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	remain = args->size;

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	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
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	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
		/* If we're not in the cpu read domain, set ourself into the gtt
		 * read domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will dirty the data
		 * anyway again before the next pread happens. */
		if (obj->cache_level == I915_CACHE_NONE)
			needs_clflush = 1;
		ret = i915_gem_object_set_to_gtt_domain(obj, false);
		if (ret)
			return ret;
	}
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	offset = args->offset;
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	while (remain > 0) {
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		struct page *page;

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		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
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		shmem_page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

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		if (obj->pages) {
			page = obj->pages[offset >> PAGE_SHIFT];
			release_page = 0;
		} else {
			page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
			if (IS_ERR(page)) {
				ret = PTR_ERR(page);
				goto out;
			}
			release_page = 1;
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		}
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		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

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		ret = shmem_pread_fast(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
		if (ret == 0)
			goto next_page;
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		hit_slowpath = 1;
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		page_cache_get(page);
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		mutex_unlock(&dev->struct_mutex);

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		if (!prefaulted) {
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			ret = fault_in_multipages_writeable(user_data, remain);
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			/* Userspace is tricking us, but we've already clobbered
			 * its pages with the prefault and promised to write the
			 * data up to the first fault. Hence ignore any errors
			 * and just continue. */
			(void)ret;
			prefaulted = 1;
		}
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		ret = shmem_pread_slow(page, shmem_page_offset, page_length,
				       user_data, page_do_bit17_swizzling,
				       needs_clflush);
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		mutex_lock(&dev->struct_mutex);
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		page_cache_release(page);
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next_page:
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		mark_page_accessed(page);
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		if (release_page)
			page_cache_release(page);
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		if (ret) {
			ret = -EFAULT;
			goto out;
		}

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		remain -= page_length;
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		user_data += page_length;
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		offset += page_length;
	}

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out:
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	if (hit_slowpath) {
		/* Fixup: Kill any reinstated backing storage pages */
		if (obj->madv == __I915_MADV_PURGED)
			i915_gem_object_truncate(obj);
	}
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	return ret;
}

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/**
 * Reads data from the object referenced by handle.
 *
 * On error, the contents of *data are undefined.
 */
int
i915_gem_pread_ioctl(struct drm_device *dev, void *data,
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		     struct drm_file *file)
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{
	struct drm_i915_gem_pread *args = data;
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	struct drm_i915_gem_object *obj;
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	int ret = 0;
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	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_WRITE,
		       (char __user *)(uintptr_t)args->data_ptr,
		       args->size))
		return -EFAULT;

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	ret = i915_mutex_lock_interruptible(dev);
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	if (ret)
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		return ret;
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	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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	if (&obj->base == NULL) {
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		ret = -ENOENT;
		goto unlock;
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	}
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	/* Bounds check source.  */
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	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
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		ret = -EINVAL;
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		goto out;
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	}

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	trace_i915_gem_object_pread(obj, args->offset, args->size);

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	ret = i915_gem_shmem_pread(dev, obj, args, file);
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out:
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	drm_gem_object_unreference(&obj->base);
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unlock:
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	mutex_unlock(&dev->struct_mutex);
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	return ret;
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}

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/* This is the fast write path which cannot handle
 * page faults in the source data
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 */
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static inline int
fast_user_write(struct io_mapping *mapping,
		loff_t page_base, int page_offset,
		char __user *user_data,
		int length)
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{
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	void __iomem *vaddr_atomic;
	void *vaddr;
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	unsigned long unwritten;
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	vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
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	/* We can use the cpu mem copy function because this is X86. */
	vaddr = (void __force*)vaddr_atomic + page_offset;
	unwritten = __copy_from_user_inatomic_nocache(vaddr,
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						      user_data, length);
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	io_mapping_unmap_atomic(vaddr_atomic);
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	return unwritten;
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}

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/**
 * This is the fast pwrite path, where we copy the data directly from the
 * user into the GTT, uncached.
 */
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static int
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i915_gem_gtt_pwrite_fast(struct drm_device *dev,
			 struct drm_i915_gem_object *obj,
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			 struct drm_i915_gem_pwrite *args,
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			 struct drm_file *file)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	ssize_t remain;
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	loff_t offset, page_base;
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	char __user *user_data;
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	int page_offset, page_length, ret;

	ret = i915_gem_object_pin(obj, 0, true);
	if (ret)
		goto out;

	ret = i915_gem_object_set_to_gtt_domain(obj, true);
	if (ret)
		goto out_unpin;

	ret = i915_gem_object_put_fence(obj);
	if (ret)
		goto out_unpin;
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	user_data = (char __user *) (uintptr_t) args->data_ptr;
	remain = args->size;

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	offset = obj->gtt_offset + args->offset;
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	while (remain > 0) {
		/* Operation in this page
		 *
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		 * page_base = page offset within aperture
		 * page_offset = offset within page
		 * page_length = bytes to copy for this page
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		 */
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		page_base = offset & PAGE_MASK;
		page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((page_offset + remain) > PAGE_SIZE)
			page_length = PAGE_SIZE - page_offset;

		/* If we get a fault while copying data, then (presumably) our
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		 * source page isn't available.  Return the error and we'll
		 * retry in the slow path.
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		 */
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		if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
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				    page_offset, user_data, page_length)) {
			ret = -EFAULT;
			goto out_unpin;
		}
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		remain -= page_length;
		user_data += page_length;
		offset += page_length;
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	}

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out_unpin:
	i915_gem_object_unpin(obj);
out:
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	return ret;
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}

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/* Per-page copy function for the shmem pwrite fastpath.
 * Flushes invalid cachelines before writing to the target if
 * needs_clflush_before is set and flushes out any written cachelines after
 * writing if needs_clflush is set. */
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static int
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shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
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{
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	char *vaddr;
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	int ret;
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	if (unlikely(page_do_bit17_swizzling))
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		return -EINVAL;
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	vaddr = kmap_atomic(page);
	if (needs_clflush_before)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
						user_data,
						page_length);
	if (needs_clflush_after)
		drm_clflush_virt_range(vaddr + shmem_page_offset,
				       page_length);
	kunmap_atomic(vaddr);
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	return ret;
}

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/* Only difference to the fast-path function is that this can handle bit17
 * and uses non-atomic copy and kmap functions. */
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static int
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shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
		  char __user *user_data,
		  bool page_do_bit17_swizzling,
		  bool needs_clflush_before,
		  bool needs_clflush_after)
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{
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	char *vaddr;
	int ret;
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	vaddr = kmap(page);
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	if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	if (page_do_bit17_swizzling)
		ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
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						user_data,
						page_length);
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	else
		ret = __copy_from_user(vaddr + shmem_page_offset,
				       user_data,
				       page_length);
	if (needs_clflush_after)
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		shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
					     page_length,
					     page_do_bit17_swizzling);
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	kunmap(page);
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	return ret;
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}

static int
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i915_gem_shmem_pwrite(struct drm_device *dev,
		      struct drm_i915_gem_object *obj,
		      struct drm_i915_gem_pwrite *args,
		      struct drm_file *file)
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{
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	struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
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	ssize_t remain;
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	loff_t offset;
	char __user *user_data;
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	int shmem_page_offset, page_length, ret = 0;
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	int obj_do_bit17_swizzling, page_do_bit17_swizzling;
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	int hit_slowpath = 0;
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	int needs_clflush_after = 0;
	int needs_clflush_before = 0;
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	int release_page;
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	user_data = (char __user *) (uintptr_t) args->data_ptr;
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	remain = args->size;

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	obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
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	if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
		/* If we're not in the cpu write domain, set ourself into the gtt
		 * write domain and manually flush cachelines (if required). This
		 * optimizes for the case when the gpu will use the data
		 * right away and we therefore have to clflush anyway. */
		if (obj->cache_level == I915_CACHE_NONE)
			needs_clflush_after = 1;
		ret = i915_gem_object_set_to_gtt_domain(obj, true);
		if (ret)
			return ret;
	}
	/* Same trick applies for invalidate partially written cachelines before
	 * writing.  */
	if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
	    && obj->cache_level == I915_CACHE_NONE)
		needs_clflush_before = 1;

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	offset = args->offset;
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	obj->dirty = 1;
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	while (remain > 0) {
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		struct page *page;
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		int partial_cacheline_write;
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		/* Operation in this page
		 *
		 * shmem_page_offset = offset within page in shmem file
		 * page_length = bytes to copy for this page
		 */
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		shmem_page_offset = offset_in_page(offset);
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		page_length = remain;
		if ((shmem_page_offset + page_length) > PAGE_SIZE)
			page_length = PAGE_SIZE - shmem_page_offset;

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		/* If we don't overwrite a cacheline completely we need to be
		 * careful to have up-to-date data by first clflushing. Don't
		 * overcomplicate things and flush the entire patch. */
		partial_cacheline_write = needs_clflush_before &&
			((shmem_page_offset | page_length)
				& (boot_cpu_data.x86_clflush_size - 1));

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		if (obj->pages) {
			page = obj->pages[offset >> PAGE_SHIFT];
			release_page = 0;
		} else {
			page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
			if (IS_ERR(page)) {
				ret = PTR_ERR(page);
				goto out;
			}
			release_page = 1;
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		}

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		page_do_bit17_swizzling = obj_do_bit17_swizzling &&
			(page_to_phys(page) & (1 << 17)) != 0;

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		ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
		if (ret == 0)
			goto next_page;
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		hit_slowpath = 1;
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		page_cache_get(page);
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		mutex_unlock(&dev->struct_mutex);

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		ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
					user_data, page_do_bit17_swizzling,
					partial_cacheline_write,
					needs_clflush_after);
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		mutex_lock(&dev->struct_mutex);
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		page_cache_release(page);
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next_page:
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		set_page_dirty(page);
		mark_page_accessed(page);
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		if (release_page)
			page_cache_release(page);
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		if (ret) {
			ret = -EFAULT;
			goto out;
		}

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		remain -= page_length;
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		user_data += page_length;
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		offset += page_length;
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	}

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out:
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	if (hit_slowpath) {
		/* Fixup: Kill any reinstated backing storage pages */
		if (obj->madv == __I915_MADV_PURGED)
			i915_gem_object_truncate(obj);
		/* and flush dirty cachelines in case the object isn't in the cpu write
		 * domain anymore. */
		if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
			i915_gem_clflush_object(obj);
			intel_gtt_chipset_flush();
		}
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	}
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	if (needs_clflush_after)
		intel_gtt_chipset_flush();

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	return ret;
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}

/**
 * Writes data to the object referenced by handle.
 *
 * On error, the contents of the buffer that were to be modified are undefined.
 */
int
i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
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		      struct drm_file *file)
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{
	struct drm_i915_gem_pwrite *args = data;
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	struct drm_i915_gem_object *obj;
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	int ret;

	if (args->size == 0)
		return 0;

	if (!access_ok(VERIFY_READ,
		       (char __user *)(uintptr_t)args->data_ptr,
		       args->size))
		return -EFAULT;

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	ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
					   args->size);
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	if (ret)
		return -EFAULT;
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	ret = i915_mutex_lock_interruptible(dev);
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	if (ret)
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		return ret;
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	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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	if (&obj->base == NULL) {
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		ret = -ENOENT;
		goto unlock;
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	}
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	/* Bounds check destination. */
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	if (args->offset > obj->base.size ||
	    args->size > obj->base.size - args->offset) {
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		ret = -EINVAL;
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		goto out;
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	}

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	trace_i915_gem_object_pwrite(obj, args->offset, args->size);

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	ret = -EFAULT;
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	/* We can only do the GTT pwrite on untiled buffers, as otherwise
	 * it would end up going through the fenced access, and we'll get
	 * different detiling behavior between reading and writing.
	 * pread/pwrite currently are reading and writing from the CPU
	 * perspective, requiring manual detiling by the client.
	 */
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	if (obj->phys_obj) {
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		ret = i915_gem_phys_pwrite(dev, obj, args, file);
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		goto out;
	}

	if (obj->gtt_space &&
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	    obj->cache_level == I915_CACHE_NONE &&
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	    obj->tiling_mode == I915_TILING_NONE &&
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	    obj->map_and_fenceable &&
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	    obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
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		ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
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		/* Note that the gtt paths might fail with non-page-backed user
		 * pointers (e.g. gtt mappings when moving data between
		 * textures). Fallback to the shmem path in that case. */
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	}
907

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	if (ret == -EFAULT)
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		ret = i915_gem_shmem_pwrite(dev, obj, args, file);
910

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out:
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	drm_gem_object_unreference(&obj->base);
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unlock:
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	mutex_unlock(&dev->struct_mutex);
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	return ret;
}

/**
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 * Called when user space prepares to use an object with the CPU, either
 * through the mmap ioctl's mapping or a GTT mapping.
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 */
int
i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
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			  struct drm_file *file)
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{
	struct drm_i915_gem_set_domain *args = data;
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	struct drm_i915_gem_object *obj;
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	uint32_t read_domains = args->read_domains;
	uint32_t write_domain = args->write_domain;
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	int ret;

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	/* Only handle setting domains to types used by the CPU. */
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	if (write_domain & I915_GEM_GPU_DOMAINS)
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		return -EINVAL;

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	if (read_domains & I915_GEM_GPU_DOMAINS)
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		return -EINVAL;

	/* Having something in the write domain implies it's in the read
	 * domain, and only that read domain.  Enforce that in the request.
	 */
	if (write_domain != 0 && read_domains != write_domain)
		return -EINVAL;

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	ret = i915_mutex_lock_interruptible(dev);
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	if (ret)
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		return ret;
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	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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	if (&obj->base == NULL) {
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		ret = -ENOENT;
		goto unlock;
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	}
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	if (read_domains & I915_GEM_DOMAIN_GTT) {
		ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
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		/* Silently promote "you're not bound, there was nothing to do"
		 * to success, since the client was just asking us to
		 * make sure everything was done.
		 */
		if (ret == -EINVAL)
			ret = 0;
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	} else {
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		ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
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	}

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	drm_gem_object_unreference(&obj->base);
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unlock:
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	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Called when user space has done writes to this buffer
 */
int
i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
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			 struct drm_file *file)
980
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{
	struct drm_i915_gem_sw_finish *args = data;
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	struct drm_i915_gem_object *obj;
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	int ret = 0;

985
	ret = i915_mutex_lock_interruptible(dev);
986
	if (ret)
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		return ret;
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	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
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	if (&obj->base == NULL) {
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		ret = -ENOENT;
		goto unlock;
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	}

	/* Pinned buffers may be scanout, so flush the cache */
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	if (obj->pin_count)
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		i915_gem_object_flush_cpu_write_domain(obj);

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	drm_gem_object_unreference(&obj->base);
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unlock:
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	mutex_unlock(&dev->struct_mutex);
	return ret;
}

/**
 * Maps the contents of an object, returning the address it is mapped
 * into.
 *
 * While the mapping holds a reference on the contents of the object, it doesn't
 * imply a ref on the object itself.
 */
int
i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
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		    struct drm_file *file)
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{
	struct drm_i915_gem_mmap *args = data;
	struct drm_gem_object *obj;
	unsigned long addr;

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	obj = drm_gem_object_lookup(dev, file, args->handle);
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	if (obj == NULL)
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		return -ENOENT;
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1024
	addr = vm_mmap(obj->filp, 0, args->size,
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		       PROT_READ | PROT_WRITE, MAP_SHARED,
		       args->offset);
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	drm_gem_object_unreference_unlocked(obj);
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	if (IS_ERR((void *)addr))
		return addr;

	args->addr_ptr = (uint64_t) addr;

	return 0;
}

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/**
 * i915_gem_fault - fault a page into the GTT
 * vma: VMA in question
 * vmf: fault info
 *
 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
 * from userspace.  The fault handler takes care of binding the object to
 * the GTT (if needed), allocating and programming a fence register (again,
 * only if needed based on whether the old reg is still valid or the object
 * is tiled) and inserting a new PTE into the faulting process.
 *
 * Note that the faulting process may involve evicting existing objects
 * from the GTT and/or fence registers to make room.  So performance may
 * suffer if the GTT working set is large or there are few fence registers
 * left.
 */
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
{
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	struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
	struct drm_device *dev = obj->base.dev;
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	drm_i915_private_t *dev_priv = dev->dev_private;
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