i7core_edac.c 45.1 KB
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/* Intel 7 core  Memory Controller kernel module (Nehalem)
 *
 * This file may be distributed under the terms of the
 * GNU General Public License version 2 only.
 *
 * Copyright (c) 2009 by:
 *	 Mauro Carvalho Chehab <mchehab@redhat.com>
 *
 * Red Hat Inc. http://www.redhat.com
 *
 * Forked and adapted from the i5400_edac driver
 *
 * Based on the following public Intel datasheets:
 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
 * Datasheet, Volume 2:
 *	http://download.intel.com/design/processor/datashts/320835.pdf
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
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#include <linux/edac_mce.h>
#include <linux/spinlock.h>
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#include "edac_core.h"

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/* To use the new pci_[read/write]_config_qword instead of two dword */
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#define USE_QWORD 0
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/*
 * Alter this version for the module when modifications are made
 */
#define I7CORE_REVISION    " Ver: 1.0.0 " __DATE__
#define EDAC_MOD_STR      "i7core_edac"

/* HACK: temporary, just to enable all logs, for now */
#undef debugf0
#define debugf0(fmt, arg...)  edac_printk(KERN_INFO, "i7core", fmt, ##arg)

/*
 * Debug macros
 */
#define i7core_printk(level, fmt, arg...)			\
	edac_printk(level, "i7core", fmt, ##arg)

#define i7core_mc_printk(mci, level, fmt, arg...)		\
	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

/*
 * i7core Memory Controller Registers
 */

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	/* OFFSETS for Device 0 Function 0 */

#define MC_CFG_CONTROL	0x90

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	/* OFFSETS for Device 3 Function 0 */

#define MC_CONTROL	0x48
#define MC_STATUS	0x4c
#define MC_MAX_DOD	0x64

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/*
 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */

#define MC_TEST_ERR_RCV1	0x60
  #define DIMM2_COR_ERR(r)			((r) & 0x7fff)

#define MC_TEST_ERR_RCV0	0x64
  #define DIMM1_COR_ERR(r)			(((r) >> 16) & 0x7fff)
  #define DIMM0_COR_ERR(r)			((r) & 0x7fff)

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	/* OFFSETS for Devices 4,5 and 6 Function 0 */

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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  #define THREE_DIMMS_PRESENT		(1 << 24)
  #define SINGLE_QUAD_RANK_PRESENT	(1 << 23)
  #define QUAD_RANK_PRESENT		(1 << 22)
  #define REGISTERED_DIMM		(1 << 15)

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#define MC_CHANNEL_MAPPER	0x60
  #define RDLCH(r, ch)		((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  #define WRLCH(r, ch)		((((r) >> (ch * 6)) & 0x07) - 1)

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#define MC_CHANNEL_RANK_PRESENT 0x7c
  #define RANK_PRESENT_MASK		0xffff

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#define MC_CHANNEL_ADDR_MATCH	0xf0
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#define MC_CHANNEL_ERROR_MASK	0xf8
#define MC_CHANNEL_ERROR_INJECT	0xfc
  #define INJECT_ADDR_PARITY	0x10
  #define INJECT_ECC		0x08
  #define MASK_CACHELINE	0x06
  #define MASK_FULL_CACHELINE	0x06
  #define MASK_MSB32_CACHELINE	0x04
  #define MASK_LSB32_CACHELINE	0x02
  #define NO_MASK_CACHELINE	0x00
  #define REPEAT_EN		0x01
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	/* OFFSETS for Devices 4,5 and 6 Function 1 */
#define MC_DOD_CH_DIMM0		0x48
#define MC_DOD_CH_DIMM1		0x4c
#define MC_DOD_CH_DIMM2		0x50
  #define RANKOFFSET_MASK	((1 << 12) | (1 << 11) | (1 << 10))
  #define RANKOFFSET(x)		((x & RANKOFFSET_MASK) >> 10)
  #define DIMM_PRESENT_MASK	(1 << 9)
  #define DIMM_PRESENT(x)	(((x) & DIMM_PRESENT_MASK) >> 9)
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  #define MC_DOD_NUMBANK_MASK		((1 << 8) | (1 << 7))
  #define MC_DOD_NUMBANK(x)		(((x) & MC_DOD_NUMBANK_MASK) >> 7)
  #define MC_DOD_NUMRANK_MASK		((1 << 6) | (1 << 5))
  #define MC_DOD_NUMRANK(x)		(((x) & MC_DOD_NUMRANK_MASK) >> 5)
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  #define MC_DOD_NUMROW_MASK		((1 << 4) | (1 << 3) | (1 << 2))
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  #define MC_DOD_NUMROW(x)		(((x) & MC_DOD_NUMROW_MASK) >> 2)
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  #define MC_DOD_NUMCOL_MASK		3
  #define MC_DOD_NUMCOL(x)		((x) & MC_DOD_NUMCOL_MASK)
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#define MC_RANK_PRESENT		0x7c

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#define MC_SAG_CH_0	0x80
#define MC_SAG_CH_1	0x84
#define MC_SAG_CH_2	0x88
#define MC_SAG_CH_3	0x8c
#define MC_SAG_CH_4	0x90
#define MC_SAG_CH_5	0x94
#define MC_SAG_CH_6	0x98
#define MC_SAG_CH_7	0x9c

#define MC_RIR_LIMIT_CH_0	0x40
#define MC_RIR_LIMIT_CH_1	0x44
#define MC_RIR_LIMIT_CH_2	0x48
#define MC_RIR_LIMIT_CH_3	0x4C
#define MC_RIR_LIMIT_CH_4	0x50
#define MC_RIR_LIMIT_CH_5	0x54
#define MC_RIR_LIMIT_CH_6	0x58
#define MC_RIR_LIMIT_CH_7	0x5C
#define MC_RIR_LIMIT_MASK	((1 << 10) - 1)

#define MC_RIR_WAY_CH		0x80
  #define MC_RIR_WAY_OFFSET_MASK	(((1 << 14) - 1) & ~0x7)
  #define MC_RIR_WAY_RANK_MASK		0x7

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/*
 * i7core structs
 */

#define NUM_CHANS 3
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#define MAX_DIMMS 3		/* Max DIMMS per channel */
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#define NUM_SOCKETS 2		/* Max number of MC sockets */
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#define MAX_MCR_FUNC  4
#define MAX_CHAN_FUNC 3
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struct i7core_info {
	u32	mc_control;
	u32	mc_status;
	u32	max_dod;
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	u32	ch_map;
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};

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struct i7core_inject {
	int	enable;

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	u8	socket;
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	u32	section;
	u32	type;
	u32	eccmask;

	/* Error address mask */
	int channel, dimm, rank, bank, page, col;
};

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struct i7core_channel {
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	u32		ranks;
	u32		dimms;
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};

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struct pci_id_descr {
	int		dev;
	int		func;
	int 		dev_id;
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	struct pci_dev	*pdev[NUM_SOCKETS];
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};

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struct i7core_pvt {
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	struct pci_dev	*pci_noncore[NUM_SOCKETS];
	struct pci_dev	*pci_mcr[NUM_SOCKETS][MAX_MCR_FUNC + 1];
	struct pci_dev	*pci_ch[NUM_SOCKETS][NUM_CHANS][MAX_CHAN_FUNC + 1];

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	struct i7core_info	info;
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	struct i7core_inject	inject;
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	struct i7core_channel	channel[NUM_SOCKETS][NUM_CHANS];

	int			sockets; /* Number of sockets */
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	int			channels; /* Number of active channels */
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	int		ce_count_available[NUM_SOCKETS];
			/* ECC corrected errors counts per dimm */
	unsigned long	ce_count[NUM_SOCKETS][MAX_DIMMS];
	int		last_ce_count[NUM_SOCKETS][MAX_DIMMS];
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	/* mcelog glue */
	struct edac_mce		edac_mce;
	struct mce		mce_entry[MCE_LOG_LEN];
	unsigned		mce_count;
	spinlock_t		mce_lock;
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};

/* Device name and register DID (Device ID) */
struct i7core_dev_info {
	const char *ctl_name;	/* name for this device */
	u16 fsb_mapping_errors;	/* DID for the branchmap,control */
};

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#define PCI_DESCR(device, function, device_id)	\
	.dev = (device),			\
	.func = (function),			\
	.dev_id = (device_id)

struct pci_id_descr pci_devs[] = {
		/* Memory controller */
	{ PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR)     },
	{ PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD)  },
	{ PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS)  }, /* if RDIMM is supported */
	{ PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },

		/* Channel 0 */
	{ PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
	{ PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
	{ PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
	{ PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC)   },

		/* Channel 1 */
	{ PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
	{ PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
	{ PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
	{ PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC)   },

		/* Channel 2 */
	{ PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
	{ PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
	{ PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
	{ PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC)   },
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		/* Generic Non-core registers */
	/*
	 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
	 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
	 * the probing code needs to test for the other address in case of
	 * failure of this one
	 */
	{ PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE)  },

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};
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#define N_DEVS ARRAY_SIZE(pci_devs)

/*
 *	pci_device_id	table for which devices we are looking for
 * This should match the first device at pci_devs table
 */
static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
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	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
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	{0,}			/* 0 terminated list. */
};

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/* Table of devices attributes supported by this driver */
static const struct i7core_dev_info i7core_devs[] = {
	{
		.ctl_name = "i7 Core",
		.fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7_MCR,
	},
};

static struct edac_pci_ctl_info *i7core_pci;

/****************************************************************************
			Anciliary status routines
 ****************************************************************************/

	/* MC_CONTROL bits */
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#define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
#define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
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	/* MC_STATUS bits */
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#define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 3))
#define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
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	/* MC_MAX_DOD read functions */
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static inline int numdimms(u32 dimms)
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{
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	return (dimms & 0x3) + 1;
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}

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static inline int numrank(u32 rank)
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{
	static int ranks[4] = { 1, 2, 4, -EINVAL };

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	return ranks[rank & 0x3];
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}

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static inline int numbank(u32 bank)
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{
	static int banks[4] = { 4, 8, 16, -EINVAL };

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	return banks[bank & 0x3];
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}

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static inline int numrow(u32 row)
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{
	static int rows[8] = {
		1 << 12, 1 << 13, 1 << 14, 1 << 15,
		1 << 16, -EINVAL, -EINVAL, -EINVAL,
	};

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	return rows[row & 0x7];
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}

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static inline int numcol(u32 col)
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{
	static int cols[8] = {
		1 << 10, 1 << 11, 1 << 12, -EINVAL,
	};
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	return cols[col & 0x3];
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}

/****************************************************************************
			Memory check routines
 ****************************************************************************/
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static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
					  unsigned func)
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{
	int i;

	for (i = 0; i < N_DEVS; i++) {
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		if (!pci_devs[i].pdev[socket])
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			continue;

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		if (PCI_SLOT(pci_devs[i].pdev[socket]->devfn) == slot &&
		    PCI_FUNC(pci_devs[i].pdev[socket]->devfn) == func) {
			return pci_devs[i].pdev[socket];
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		}
	}

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	return NULL;
}

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/**
 * i7core_get_active_channels() - gets the number of channels and csrows
 * @socket:	Quick Path Interconnect socket
 * @channels:	Number of channels that will be returned
 * @csrows:	Number of csrows found
 *
 * Since EDAC core needs to know in advance the number of available channels
 * and csrows, in order to allocate memory for csrows/channels, it is needed
 * to run two similar steps. At the first step, implemented on this function,
 * it checks the number of csrows/channels present at one socket.
 * this is used in order to properly allocate the size of mci components.
 *
 * It should be noticed that none of the current available datasheets explain
 * or even mention how csrows are seen by the memory controller. So, we need
 * to add a fake description for csrows.
 * So, this driver is attributing one DIMM memory for one csrow.
 */
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static int i7core_get_active_channels(u8 socket, unsigned *channels,
				      unsigned *csrows)
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{
	struct pci_dev *pdev = NULL;
	int i, j;
	u32 status, control;

	*channels = 0;
	*csrows = 0;

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	pdev = get_pdev_slot_func(socket, 3, 0);
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	if (!pdev) {
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		i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
			      socket);
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		return -ENODEV;
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	}
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	/* Device 3 function 0 reads */
	pci_read_config_dword(pdev, MC_STATUS, &status);
	pci_read_config_dword(pdev, MC_CONTROL, &control);

	for (i = 0; i < NUM_CHANS; i++) {
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		u32 dimm_dod[3];
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		/* Check if the channel is active */
		if (!(control & (1 << (8 + i))))
			continue;

		/* Check if the channel is disabled */
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		if (status & (1 << i))
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			continue;

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		pdev = get_pdev_slot_func(socket, i + 4, 1);
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		if (!pdev) {
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			i7core_printk(KERN_ERR, "Couldn't find socket %d "
						"fn %d.%d!!!\n",
						socket, i + 4, 1);
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			return -ENODEV;
		}
		/* Devices 4-6 function 1 */
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM0, &dimm_dod[0]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM1, &dimm_dod[1]);
		pci_read_config_dword(pdev,
				MC_DOD_CH_DIMM2, &dimm_dod[2]);

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		(*channels)++;
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		for (j = 0; j < 3; j++) {
			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;
			(*csrows)++;
		}
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	}

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	debugf0("Number of active channels on socket %d: %d\n",
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		socket, *channels);
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	return 0;
}

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static int get_dimm_config(struct mem_ctl_info *mci, int *csrow, u8 socket)
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{
	struct i7core_pvt *pvt = mci->pvt_info;
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	struct csrow_info *csr;
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	struct pci_dev *pdev;
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	int i, j;
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	unsigned long last_page = 0;
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	enum edac_type mode;
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	enum mem_type mtype;
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	/* Get data from the MC register, function 0 */
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	pdev = pvt->pci_mcr[socket][0];
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	if (!pdev)
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		return -ENODEV;

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	/* Device 3 function 0 reads */
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	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
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	debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
		socket, pvt->info.mc_control, pvt->info.mc_status,
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		pvt->info.max_dod, pvt->info.ch_map);
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	if (ECC_ENABLED(pvt)) {
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		debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
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		if (ECCx8(pvt))
			mode = EDAC_S8ECD8ED;
		else
			mode = EDAC_S4ECD4ED;
	} else {
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		debugf0("ECC disabled\n");
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		mode = EDAC_NONE;
	}
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	/* FIXME: need to handle the error codes */
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	debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
		"x%x x 0x%x\n",
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		numdimms(pvt->info.max_dod),
		numrank(pvt->info.max_dod >> 2),
		numbank(pvt->info.max_dod >> 4));
		numrow(pvt->info.max_dod >> 6),
		numcol(pvt->info.max_dod >> 9));
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	for (i = 0; i < NUM_CHANS; i++) {
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		u32 data, dimm_dod[3], value[8];
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		if (!CH_ACTIVE(pvt, i)) {
			debugf0("Channel %i is not active\n", i);
			continue;
		}
		if (CH_DISABLED(pvt, i)) {
			debugf0("Channel %i is disabled\n", i);
			continue;
		}

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		/* Devices 4-6 function 0 */
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		pci_read_config_dword(pvt->pci_ch[socket][i][0],
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				MC_CHANNEL_DIMM_INIT_PARAMS, &data);

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		pvt->channel[socket][i].ranks = (data & QUAD_RANK_PRESENT) ?
						4 : 2;
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		if (data & REGISTERED_DIMM)
			mtype = MEM_RDDR3;
		else
			mtype = MEM_DDR3;
#if 0
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		if (data & THREE_DIMMS_PRESENT)
			pvt->channel[i].dimms = 3;
		else if (data & SINGLE_QUAD_RANK_PRESENT)
			pvt->channel[i].dimms = 1;
		else
			pvt->channel[i].dimms = 2;
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#endif

		/* Devices 4-6 function 1 */
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		pci_read_config_dword(pvt->pci_ch[socket][i][1],
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				MC_DOD_CH_DIMM0, &dimm_dod[0]);
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		pci_read_config_dword(pvt->pci_ch[socket][i][1],
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				MC_DOD_CH_DIMM1, &dimm_dod[1]);
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		pci_read_config_dword(pvt->pci_ch[socket][i][1],
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				MC_DOD_CH_DIMM2, &dimm_dod[2]);
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		debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
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			"%d ranks, %cDIMMs\n",
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			i,
			RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
			data,
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			pvt->channel[socket][i].ranks,
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			(data & REGISTERED_DIMM) ? 'R' : 'U');
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		for (j = 0; j < 3; j++) {
			u32 banks, ranks, rows, cols;
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			u32 size, npages;
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			if (!DIMM_PRESENT(dimm_dod[j]))
				continue;

			banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
			ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
			rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
			cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));

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			/* DDR3 has 8 I/O banks */
			size = (rows * cols * banks * ranks) >> (20 - 3);

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			pvt->channel[socket][i].dimms++;
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			debugf0("\tdimm %d %d Mb offset: %x, "
				"bank: %d, rank: %d, row: %#x, col: %#x\n",
				j, size,
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				RANKOFFSET(dimm_dod[j]),
				banks, ranks, rows, cols);

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#if PAGE_SHIFT > 20
			npages = size >> (PAGE_SHIFT - 20);
#else
			npages = size << (20 - PAGE_SHIFT);
#endif
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			csr = &mci->csrows[*csrow];
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			csr->first_page = last_page + 1;
			last_page += npages;
			csr->last_page = last_page;
			csr->nr_pages = npages;

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			csr->page_mask = 0;
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			csr->grain = 8;
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			csr->csrow_idx = *csrow;
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			csr->nr_channels = 1;

			csr->channels[0].chan_idx = i;
			csr->channels[0].ce_count = 0;
570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587

			switch (banks) {
			case 4:
				csr->dtype = DEV_X4;
				break;
			case 8:
				csr->dtype = DEV_X8;
				break;
			case 16:
				csr->dtype = DEV_X16;
				break;
			default:
				csr->dtype = DEV_UNKNOWN;
			}

			csr->edac_mode = mode;
			csr->mtype = mtype;

588
			(*csrow)++;
589
		}
590

591 592 593 594 595 596 597 598
		pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
		pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
		pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
		pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
		pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
		pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
		pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
		pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
599
		debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
600
		for (j = 0; j < 8; j++)
601
			debugf1("\t\t%#x\t%#x\t%#x\n",
602 603 604
				(value[j] >> 27) & 0x1,
				(value[j] >> 24) & 0x7,
				(value[j] && ((1 << 24) - 1)));
605 606
	}

607 608 609
	return 0;
}

610 611 612 613 614 615 616 617 618 619 620
/****************************************************************************
			Error insertion routines
 ****************************************************************************/

/* The i7core has independent error injection features per channel.
   However, to have a simpler code, we don't allow enabling error injection
   on more than one channel.
   Also, since a change at an inject parameter will be applied only at enable,
   we're disabling error injection on all write calls to the sysfs nodes that
   controls the error code injection.
 */
621
static int disable_inject(struct mem_ctl_info *mci)
622 623 624 625 626
{
	struct i7core_pvt *pvt = mci->pvt_info;

	pvt->inject.enable = 0;

627
	if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
628 629
		return -ENODEV;

630
	pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
631
				MC_CHANNEL_ERROR_MASK, 0);
632 633

	return 0;
634 635
}

636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662
/*
 * i7core inject inject.socket
 *
 *	accept and store error injection inject.socket value
 */
static ssize_t i7core_inject_socket_store(struct mem_ctl_info *mci,
					   const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > pvt->sockets))
		return 0;

	pvt->inject.section = (u32) value;
	return count;
}

static ssize_t i7core_inject_socket_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "%d\n", pvt->inject.socket);
}

663 664 665 666 667 668 669 670 671 672 673 674 675 676 677
/*
 * i7core inject inject.section
 *
 *	accept and store error injection inject.section value
 *	bit 0 - refers to the lower 32-byte half cacheline
 *	bit 1 - refers to the upper 32-byte half cacheline
 */
static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
					   const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
678
		disable_inject(mci);
679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 3))
		return 0;

	pvt->inject.section = (u32) value;
	return count;
}

static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.section);
}

/*
 * i7core inject.type
 *
 *	accept and store error injection inject.section value
 *	bit 0 - repeat enable - Enable error repetition
 *	bit 1 - inject ECC error
 *	bit 2 - inject parity error
 */
static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
711
		disable_inject(mci);
712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745

	rc = strict_strtoul(data, 10, &value);
	if ((rc < 0) || (value > 7))
		return 0;

	pvt->inject.type = (u32) value;
	return count;
}

static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.type);
}

/*
 * i7core_inject_inject.eccmask_store
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	unsigned long value;
	int rc;

	if (pvt->inject.enable)
746
		disable_inject(mci);
747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781

	rc = strict_strtoul(data, 10, &value);
	if (rc < 0)
		return 0;

	pvt->inject.eccmask = (u32) value;
	return count;
}

static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
}

/*
 * i7core_addrmatch
 *
 * The type of error (UE/CE) will depend on the inject.eccmask value:
 *   Any bits set to a 1 will flip the corresponding ECC bit
 *   Correctable errors can be injected by flipping 1 bit or the bits within
 *   a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
 *   23:16 and 31:24). Flipping bits in two symbol pairs will cause an
 *   uncorrectable error to be injected.
 */
static ssize_t i7core_inject_addrmatch_store(struct mem_ctl_info *mci,
					const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	char *cmd, *val;
	long value;
	int rc;

	if (pvt->inject.enable)
782
		disable_inject(mci);
783 784 785 786 787 788 789 790 791

	do {
		cmd = strsep((char **) &data, ":");
		if (!cmd)
			break;
		val = strsep((char **) &data, " \n\t");
		if (!val)
			return cmd - data;

792
		if (!strcasecmp(val, "any"))
793 794 795 796 797 798 799
			value = -1;
		else {
			rc = strict_strtol(val, 10, &value);
			if ((rc < 0) || (value < 0))
				return cmd - data;
		}

800
		if (!strcasecmp(cmd, "channel")) {
801 802 803 804
			if (value < 3)
				pvt->inject.channel = value;
			else
				return cmd - data;
805
		} else if (!strcasecmp(cmd, "dimm")) {
806 807 808 809
			if (value < 4)
				pvt->inject.dimm = value;
			else
				return cmd - data;
810
		} else if (!strcasecmp(cmd, "rank")) {
811 812 813 814
			if (value < 4)
				pvt->inject.rank = value;
			else
				return cmd - data;
815
		} else if (!strcasecmp(cmd, "bank")) {
816 817 818 819
			if (value < 4)
				pvt->inject.bank = value;
			else
				return cmd - data;
820
		} else if (!strcasecmp(cmd, "page")) {
821 822 823 824
			if (value <= 0xffff)
				pvt->inject.page = value;
			else
				return cmd - data;
825 826
		} else if (!strcasecmp(cmd, "col") ||
			   !strcasecmp(cmd, "column")) {
827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899
			if (value <= 0x3fff)
				pvt->inject.col = value;
			else
				return cmd - data;
		}
	} while (1);

	return count;
}

static ssize_t i7core_inject_addrmatch_show(struct mem_ctl_info *mci,
					      char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	char channel[4], dimm[4], bank[4], rank[4], page[7], col[7];

	if (pvt->inject.channel < 0)
		sprintf(channel, "any");
	else
		sprintf(channel, "%d", pvt->inject.channel);
	if (pvt->inject.dimm < 0)
		sprintf(dimm, "any");
	else
		sprintf(dimm, "%d", pvt->inject.dimm);
	if (pvt->inject.bank < 0)
		sprintf(bank, "any");
	else
		sprintf(bank, "%d", pvt->inject.bank);
	if (pvt->inject.rank < 0)
		sprintf(rank, "any");
	else
		sprintf(rank, "%d", pvt->inject.rank);
	if (pvt->inject.page < 0)
		sprintf(page, "any");
	else
		sprintf(page, "0x%04x", pvt->inject.page);
	if (pvt->inject.col < 0)
		sprintf(col, "any");
	else
		sprintf(col, "0x%04x", pvt->inject.col);

	return sprintf(data, "channel: %s\ndimm: %s\nbank: %s\n"
			     "rank: %s\npage: %s\ncolumn: %s\n",
		       channel, dimm, bank, rank, page, col);
}

/*
 * This routine prepares the Memory Controller for error injection.
 * The error will be injected when some process tries to write to the
 * memory that matches the given criteria.
 * The criteria can be set in terms of a mask where dimm, rank, bank, page
 * and col can be specified.
 * A -1 value for any of the mask items will make the MCU to ignore
 * that matching criteria for error injection.
 *
 * It should be noticed that the error will only happen after a write operation
 * on a memory that matches the condition. if REPEAT_EN is not enabled at
 * inject mask, then it will produce just one error. Otherwise, it will repeat
 * until the injectmask would be cleaned.
 *
 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
 *    is reliable enough to check if the MC is using the
 *    three channels. However, this is not clear at the datasheet.
 */
static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
				       const char *data, size_t count)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 injectmask;
	u64 mask = 0;
	int  rc;
	long enable;

900
	if (!pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0])
901 902
		return 0;

903 904 905 906 907 908 909 910 911 912 913 914 915
	rc = strict_strtoul(data, 10, &enable);
	if ((rc < 0))
		return 0;

	if (enable) {
		pvt->inject.enable = 1;
	} else {
		disable_inject(mci);
		return count;
	}

	/* Sets pvt->inject.dimm mask */
	if (pvt->inject.dimm < 0)
916
		mask |= 1L << 41;
917
	else {
918
		if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
919
			mask |= (pvt->inject.dimm & 0x3L) << 35;
920
		else
921
			mask |= (pvt->inject.dimm & 0x1L) << 36;
922 923 924 925
	}

	/* Sets pvt->inject.rank mask */
	if (pvt->inject.rank < 0)
926
		mask |= 1L << 40;
927
	else {
928
		if (pvt->channel[pvt->inject.socket][pvt->inject.channel].dimms > 2)
929
			mask |= (pvt->inject.rank & 0x1L) << 34;
930
		else
931
			mask |= (pvt->inject.rank & 0x3L) << 34;
932 933 934 935
	}

	/* Sets pvt->inject.bank mask */
	if (pvt->inject.bank < 0)
936
		mask |= 1L << 39;
937
	else
938
		mask |= (pvt->inject.bank & 0x15L) << 30;
939 940 941

	/* Sets pvt->inject.page mask */
	if (pvt->inject.page < 0)
942
		mask |= 1L << 38;
943
	else
944
		mask |= (pvt->inject.page & 0xffffL) << 14;
945 946 947

	/* Sets pvt->inject.column mask */
	if (pvt->inject.col < 0)
948
		mask |= 1L << 37;
949
	else
950
		mask |= (pvt->inject.col & 0x3fffL);
951

952
	/* Unlock writes to registers */
953 954
	pci_write_config_dword(pvt->pci_noncore[pvt->inject.socket],
			       MC_CFG_CONTROL, 0x2);
955 956 957
	msleep(100);

	/* Zeroes error count registers */
958 959 960 961 962
	pci_write_config_dword(pvt->pci_mcr[pvt->inject.socket][4],
			       MC_TEST_ERR_RCV1, 0);
	pci_write_config_dword(pvt->pci_mcr[pvt->inject.socket][4],
			       MC_TEST_ERR_RCV0, 0);
	pvt->ce_count_available[pvt->inject.socket] = 0;
963 964


965
#if USE_QWORD
966
	pci_write_config_qword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
967
			       MC_CHANNEL_ADDR_MATCH, mask);
968
#else
969
	pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
970
			       MC_CHANNEL_ADDR_MATCH, mask);
971
	pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
972 973 974 975 976 977
			       MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
#endif

#if 1
#if USE_QWORD
	u64 rdmask;
978
	pci_read_config_qword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
979 980 981 982 983 984
			       MC_CHANNEL_ADDR_MATCH, &rdmask);
	debugf0("Inject addr match write 0x%016llx, read: 0x%016llx\n",
		mask, rdmask);
#else
	u32 rdmask1, rdmask2;

985
	pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
986
			       MC_CHANNEL_ADDR_MATCH, &rdmask1);
987
	pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
988 989
			       MC_CHANNEL_ADDR_MATCH + 4, &rdmask2);

990
	debugf0("Inject addr match write 0x%016llx, read: 0x%08x 0x%08x\n",
991 992 993
		mask, rdmask1, rdmask2);
#endif
#endif
994

995
	pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
996 997 998 999 1000 1001 1002 1003 1004
			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);

	/*
	 * bit    0: REPEAT_EN
	 * bits 1-2: MASK_HALF_CACHELINE
	 * bit    3: INJECT_ECC
	 * bit    4: INJECT_ADDR_PARITY
	 */

1005 1006
	injectmask = (pvt->inject.type & 1) |
		     (pvt->inject.section & 0x3) << 1 |
1007 1008
		     (pvt->inject.type & 0x6) << (3 - 1);

1009
	pci_write_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
1010 1011
			       MC_CHANNEL_ERROR_MASK, injectmask);

1012 1013 1014 1015
#if 0
	/* lock writes to registers */
	pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, 0);
#endif
1016 1017
	debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
		" inject 0x%08x\n",
1018 1019
		mask, pvt->inject.eccmask, injectmask);

1020

1021 1022 1023 1024 1025 1026 1027
	return count;
}

static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
					char *data)
{
	struct i7core_pvt *pvt = mci->pvt_info;
1028 1029
	u32 injectmask;

1030
	pci_read_config_dword(pvt->pci_ch[pvt->inject.socket][pvt->inject.channel][0],
1031 1032 1033 1034 1035 1036 1037
			       MC_CHANNEL_ERROR_MASK, &injectmask);

	debugf0("Inject error read: 0x%018x\n", injectmask);

	if (injectmask & 0x0c)
		pvt->inject.enable = 1;

1038 1039 1040
	return sprintf(data, "%d\n", pvt->inject.enable);
}

1041 1042
static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
{
1043
	unsigned i, count, total = 0;
1044 1045
	struct i7core_pvt *pvt = mci->pvt_info;

1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058
	for (i = 0; i < pvt->sockets; i++) {
		if (!pvt->ce_count_available[i])
			count = sprintf(data, "socket 0 data unavailable\n");
		else
			count = sprintf(data, "socket %d, dimm0: %lu\n"
					      "dimm1: %lu\ndimm2: %lu\n",
					i,
					pvt->ce_count[i][0],
					pvt->ce_count[i][1],
					pvt->ce_count[i][2]);
		data  += count;
		total += count;
	}
1059

1060
	return total;
1061 1062
}

1063 1064 1065 1066 1067
/*
 * Sysfs struct
 */
static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
	{
1068 1069 1070 1071 1072 1073 1074
		.attr = {
			.name = "inject_socket",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_socket_show,
		.store = i7core_inject_socket_store,
	}, {
1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108
		.attr = {
			.name = "inject_section",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_section_show,
		.store = i7core_inject_section_store,
	}, {
		.attr = {
			.name = "inject_type",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_type_show,
		.store = i7core_inject_type_store,
	}, {
		.attr = {
			.name = "inject_eccmask",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_eccmask_show,
		.store = i7core_inject_eccmask_store,
	}, {
		.attr = {
			.name = "inject_addrmatch",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_addrmatch_show,
		.store = i7core_inject_addrmatch_store,
	}, {
		.attr = {
			.name = "inject_enable",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_inject_enable_show,
		.store = i7core_inject_enable_store,
1109 1110 1111 1112 1113 1114 1115
	}, {
		.attr = {
			.name = "corrected_error_counts",
			.mode = (S_IRUGO | S_IWUSR)
		},
		.show  = i7core_ce_regs_show,
		.store = NULL,
1116 1117 1118
	},
};

1119 1120 1121 1122 1123 1124 1125 1126
/****************************************************************************
	Device initialization routines: put/get, init/exit
 ****************************************************************************/

/*
 *	i7core_put_devices	'put' all the devices that we have
 *				reserved via 'get'
 */
1127
static void i7core_put_devices(void)
1128
{
1129
	int i, j;
1130

1131 1132 1133
	for (i = 0; i < NUM_SOCKETS; i++)
		for (j = 0; j < N_DEVS; j++)
			pci_dev_put(pci_devs[j].pdev[i]);
1134 1135 1136 1137 1138 1139 1140 1141
}

/*
 *	i7core_get_devices	Find and perform 'get' operation on the MCH's
 *			device/functions we want to reference for this driver
 *
 *			Need to 'get' device 16 func 1 and func 2
 */
1142
int i7core_get_onedevice(struct pci_dev **prev, int devno)
1143
{
1144
	struct pci_dev *pdev = NULL;
1145 1146
	u8 bus = 0;
	u8 socket = 0;
1147

1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159
	pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
			      pci_devs[devno].dev_id, *prev);

	/*
	 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
	 * aren't announced by acpi. So, we need to use a legacy scan probing
	 * to detect them
	 */
	if (unlikely(!pdev && !devno && !prev)) {
		pcibios_scan_specific_bus(254);
		pcibios_scan_specific_bus(255);

1160
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1161 1162
				      pci_devs[devno].dev_id, *prev);
	}
1163

1164 1165 1166 1167 1168 1169 1170 1171
	/*
	 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
	 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
	 * to probe for the alternate address in case of failure
	 */
	if (pci_devs[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
		pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
				      PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev);
1172

1173 1174 1175 1176
	if (!pdev) {
		if (*prev) {
			*prev = pdev;
			return 0;
1177 1178
		}

1179
		/*
1180 1181
		 * Dev 3 function 2 only exists on chips with RDIMMs
		 * so, it is ok to not found it
1182
		 */
1183 1184 1185 1186
		if ((pci_devs[devno].dev == 3) && (pci_devs[devno].func == 2)) {
			*prev = pdev;
			return 0;
		}
1187

1188 1189 1190 1191
		i7core_printk(KERN_ERR,
			"Device not found: dev %02x.%d PCI ID %04x:%04x\n",
			pci_devs[devno].dev, pci_devs[devno].func,
			PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1192

1193 1194 1195 1196
		/* End of list, leave */
		return -ENODEV;
	}
	bus = pdev->bus->number;
1197

1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
	if (bus == 0x3f)
		socket = 0;
	else
		socket = 255 - bus;

	if (socket >= NUM_SOCKETS) {
		i7core_printk(KERN_ERR,
			"Unexpected socket for "
			"dev %02x:%02x.%d PCI ID %04x:%04x\n",
			bus, pci_devs[devno].dev, pci_devs[devno].func,
			PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
		pci_dev_put(pdev);
		return -ENODEV;
	}
1212

1213 1214 1215 1216 1217 1218 1219 1220 1221
	if (pci_devs[devno].pdev[socket]) {
		i7core_printk(KERN_ERR,
			"Duplicated device for "
			"dev %02x:%02x.%d PCI ID %04x:%04x\n",
			bus, pci_devs[devno].dev, pci_devs[devno].func,
			PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
		pci_dev_put(pdev);
		return -ENODEV;
	}
1222

1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
	pci_devs[devno].pdev[socket] = pdev;

	/* Sanity check */
	if (unlikely(PCI_SLOT(pdev->devfn) != pci_devs[devno].dev ||
			PCI_FUNC(pdev->devfn) != pci_devs[devno].func)) {
		i7core_printk(KERN_ERR,
			"Device PCI ID %04x:%04x "
			"has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
			PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id,
			bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
			bus, pci_devs[devno].dev, pci_devs[devno].func);
		return -ENODEV;
	}
1236

1237 1238 1239 1240 1241 1242 1243 1244 1245
	/* Be sure that the device is enabled */
	if (unlikely(pci_enable_device(pdev) < 0)) {
		i7core_printk(KERN_ERR,
			"Couldn't enable "
			"dev %02x:%02x.%d PCI ID %04x:%04x\n",
			bus, pci_devs[devno].dev, pci_devs[devno].func,
			PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
		return -ENODEV;
	}
1246

1247 1248 1249 1250 1251
	i7core_printk(KERN_INFO,
			"Registered socket %d "
			"dev %02x:%02x.%d PCI ID %04x:%04x\n",
			socket, bus, pci_devs[devno].dev, pci_devs[devno].func,
			PCI_VENDOR_ID_INTEL, pci_devs[devno].dev_id);
1252

1253
	*prev = pdev;
1254

1255 1256
	return 0;
}
1257

1258 1259 1260 1261
static int i7core_get_devices(void)
{
	int i;
	struct pci_dev *pdev = NULL;
1262

1263 1264 1265 1266 1267 1268 1269 1270 1271
	for (i = 0; i < N_DEVS; i++) {
		pdev = NULL;
		do {
			if (i7core_get_onedevice(&pdev, i) < 0) {
				i7core_put_devices();
				return -ENODEV;
			}
		} while (pdev);
	}
1272 1273 1274 1275 1276 1277 1278
	return 0;
}

static int mci_bind_devs(struct mem_ctl_info *mci)
{
	struct i7core_pvt *pvt = mci->pvt_info;
	struct pci_dev *pdev;
1279
	int i, j, func, slot;
1280

1281 1282 1283 1284 1285
	for (i = 0; i < pvt->sockets; i++) {
		for (j = 0; j < N_DEVS; j++) {
			pdev = pci_devs[j].pdev[i];
			if (!pdev)
				continue;
1286

1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299
			func = PCI_FUNC(pdev->devfn);
			slot = PCI_SLOT(pdev->devfn);
			if (slot == 3) {
				if (unlikely(func > MAX_MCR_FUNC))
					goto error;
				pvt->pci_mcr[i][func] = pdev;
			} else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
				if (unlikely(func > MAX_CHAN_FUNC))
					goto error;
				pvt->pci_ch[i][slot - 4][func] = pdev;
			} else if (!slot && !func)
				pvt->pci_noncore[i] = pdev;
			else
1300 1301
				goto error;

1302 1303 1304 1305
			debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
				PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
				pdev, i);
		}
1306
	}
1307

1308
	return 0;
1309 1310 1311 1312 1313 1314

error:
	i7core_printk(KERN_ERR, "Device %d, function %d "
		      "is out of the expected range\n",
		      slot, func);
	return -EINVAL;
1315 1316
}

1317 1318 1319 1320 1321 1322 1323 1324 1325 1326
/****************************************************************************
			Error check routines
 ****************************************************************************/

/* This function is based on the device 3 function 4 registers as described on:
 * Intel Xeon Processor 5500 Series Datasheet Volume 2
 *	http://www.intel.com/Assets/PDF/datasheet/321322.pdf
 * also available at:
 * 	http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
 */
1327
static void check_mc_test_err(struct mem_ctl_info *mci, u8 socket)
1328 1329 1330 1331 1332
{
	struct i7core_pvt *pvt = mci->pvt_info;
	u32 rcv1, rcv0;
	int new0, new1, new2;

1333
	if (!pvt->pci_mcr[socket][4]) {
1334 1335 1336 1337 1338
		debugf0("%s MCR registers not found\n",__func__);
		return;
	}

	/* Corrected error reads */
1339 1340
	pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV1, &rcv1);
	pci_read_config_dword(pvt->pci_mcr[socket][4], MC_TEST_ERR_RCV0, &rcv0);
1341 1342 1343 1344 1345 1346

	/* Store the new values */
	new2 = DIMM2_COR_ERR(rcv1);
	new1 = DIMM1_COR_ERR(rcv0);
	new0 = DIMM0_COR_ERR(rcv0);

1347
#if 0
1348 1349 1350
	debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
		(pvt->ce_count_available ? "UPDATE" : "READ"),
		rcv1, rcv0, new0, new1, new2);
1351
#endif
1352 1353

	/* Updates CE counters if it is not the first time here */
1354
	if (pvt->ce_count_available[socket]) {
1355 1356 1357
		/* Updates CE counters */
		int add0, add1, add2;

1358 1359 1360
		add2 = new2 - pvt->last_ce_count[socket][2];
		add1 = new1 - pvt->last_ce_count[socket][1];
		add0 = new0 - pvt->last_ce_count[socket][0];
1361 1362 1363

		if (add2 < 0)
			add2 += 0x7fff;
1364
		pvt->ce_count[socket][2] += add2;
1365 1366 1367

		if (add1 < 0)
			add1 += 0x7fff;
1368
		pvt->ce_count[socket][1] += add1;
1369 1370 1371

		if (add0 < 0)
			add0 += 0x7fff;
1372
		pvt->ce_count[socket][0] += add0;
1373
	} else