iwl-4965.c 109 KB
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/******************************************************************************
 *
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 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
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 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/wireless.h>
#include <net/mac80211.h>
#include <linux/etherdevice.h>
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#include <asm/unaligned.h>
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#include "iwl-eeprom.h"
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-io.h"
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#include "iwl-helpers.h"
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#include "iwl-calib.h"
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/* module parameters */
static struct iwl_mod_params iwl4965_mod_params = {
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	.num_of_queues = IWL49_NUM_QUEUES,
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	.enable_qos = 1,
	.amsdu_size_8K = 1,
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	.restart_fw = 1,
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	/* the rest are 0 by default */
};

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#ifdef CONFIG_IWL4965_HT

static const u16 default_tid_to_tx_fifo[] = {
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC0,
	IWL_TX_FIFO_AC0,
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_AC3
};

#endif	/*CONFIG_IWL4965_HT */

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/* check contents of special bootstrap uCode SRAM */
static int iwl4965_verify_bsm(struct iwl_priv *priv)
{
	__le32 *image = priv->ucode_boot.v_addr;
	u32 len = priv->ucode_boot.len;
	u32 reg;
	u32 val;

	IWL_DEBUG_INFO("Begin verify bsm\n");

	/* verify BSM SRAM contents */
	val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
	for (reg = BSM_SRAM_LOWER_BOUND;
	     reg < BSM_SRAM_LOWER_BOUND + len;
	     reg += sizeof(u32), image++) {
		val = iwl_read_prph(priv, reg);
		if (val != le32_to_cpu(*image)) {
			IWL_ERROR("BSM uCode verification failed at "
				  "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
				  BSM_SRAM_LOWER_BOUND,
				  reg - BSM_SRAM_LOWER_BOUND, len,
				  val, le32_to_cpu(*image));
			return -EIO;
		}
	}

	IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");

	return 0;
}

/**
 * iwl4965_load_bsm - Load bootstrap instructions
 *
 * BSM operation:
 *
 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
 * in special SRAM that does not power down during RFKILL.  When powering back
 * up after power-saving sleeps (or during initial uCode load), the BSM loads
 * the bootstrap program into the on-board processor, and starts it.
 *
 * The bootstrap program loads (via DMA) instructions and data for a new
 * program from host DRAM locations indicated by the host driver in the
 * BSM_DRAM_* registers.  Once the new program is loaded, it starts
 * automatically.
 *
 * When initializing the NIC, the host driver points the BSM to the
 * "initialize" uCode image.  This uCode sets up some internal data, then
 * notifies host via "initialize alive" that it is complete.
 *
 * The host then replaces the BSM_DRAM_* pointer values to point to the
 * normal runtime uCode instructions and a backup uCode data cache buffer
 * (filled initially with starting data values for the on-board processor),
 * then triggers the "initialize" uCode to load and launch the runtime uCode,
 * which begins normal operation.
 *
 * When doing a power-save shutdown, runtime uCode saves data SRAM into
 * the backup data cache in DRAM before SRAM is powered down.
 *
 * When powering back up, the BSM loads the bootstrap program.  This reloads
 * the runtime uCode instructions and the backup data cache into SRAM,
 * and re-launches the runtime uCode from where it left off.
 */
static int iwl4965_load_bsm(struct iwl_priv *priv)
{
	__le32 *image = priv->ucode_boot.v_addr;
	u32 len = priv->ucode_boot.len;
	dma_addr_t pinst;
	dma_addr_t pdata;
	u32 inst_len;
	u32 data_len;
	int i;
	u32 done;
	u32 reg_offset;
	int ret;

	IWL_DEBUG_INFO("Begin load bsm\n");

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	priv->ucode_type = UCODE_RT;

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	/* make sure bootstrap program is no larger than BSM's SRAM size */
	if (len > IWL_MAX_BSM_SIZE)
		return -EINVAL;

	/* Tell bootstrap uCode where to find the "Initialize" uCode
	 *   in host DRAM ... host DRAM physical address bits 35:4 for 4965.
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	 * NOTE:  iwl_init_alive_start() will replace these values,
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	 *        after the "initialize" uCode has run, to point to
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	 *        runtime/protocol instructions and backup data cache.
	 */
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	pinst = priv->ucode_init.p_addr >> 4;
	pdata = priv->ucode_init_data.p_addr >> 4;
	inst_len = priv->ucode_init.len;
	data_len = priv->ucode_init_data.len;

	ret = iwl_grab_nic_access(priv);
	if (ret)
		return ret;

	iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
	iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
	iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
	iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);

	/* Fill BSM memory with bootstrap instructions */
	for (reg_offset = BSM_SRAM_LOWER_BOUND;
	     reg_offset < BSM_SRAM_LOWER_BOUND + len;
	     reg_offset += sizeof(u32), image++)
		_iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));

	ret = iwl4965_verify_bsm(priv);
	if (ret) {
		iwl_release_nic_access(priv);
		return ret;
	}

	/* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
	iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
	iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
	iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));

	/* Load bootstrap code into instruction SRAM now,
	 *   to prepare to load "initialize" uCode */
	iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);

	/* Wait for load of bootstrap uCode to finish */
	for (i = 0; i < 100; i++) {
		done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
		if (!(done & BSM_WR_CTRL_REG_BIT_START))
			break;
		udelay(10);
	}
	if (i < 100)
		IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
	else {
		IWL_ERROR("BSM write did not complete!\n");
		return -EIO;
	}

	/* Enable future boot loads whenever power management unit triggers it
	 *   (e.g. when powering back up after power-save shutdown) */
	iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);

	iwl_release_nic_access(priv);

	return 0;
}

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/**
 * iwl4965_set_ucode_ptrs - Set uCode address location
 *
 * Tell initialization uCode where to find runtime uCode.
 *
 * BSM registers initially contain pointers to initialization uCode.
 * We need to replace them to load runtime uCode inst and data,
 * and to save runtime data when powering down.
 */
static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
{
	dma_addr_t pinst;
	dma_addr_t pdata;
	unsigned long flags;
	int ret = 0;

	/* bits 35:4 for 4965 */
	pinst = priv->ucode_code.p_addr >> 4;
	pdata = priv->ucode_data_backup.p_addr >> 4;

	spin_lock_irqsave(&priv->lock, flags);
	ret = iwl_grab_nic_access(priv);
	if (ret) {
		spin_unlock_irqrestore(&priv->lock, flags);
		return ret;
	}

	/* Tell bootstrap uCode where to find image to load */
	iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
	iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
	iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
				 priv->ucode_data.len);

	/* Inst bytecount must be last to set up, bit 31 signals uCode
	 *   that all new ptr/size info is in place */
	iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
				 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
	iwl_release_nic_access(priv);

	spin_unlock_irqrestore(&priv->lock, flags);

	IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");

	return ret;
}

/**
 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
 *
 * Called after REPLY_ALIVE notification received from "initialize" uCode.
 *
 * The 4965 "initialize" ALIVE reply contains calibration data for:
 *   Voltage, temperature, and MIMO tx gain correction, now stored in priv
 *   (3945 does not contain this data).
 *
 * Tell "initialize" uCode to go ahead and load the runtime uCode.
*/
static void iwl4965_init_alive_start(struct iwl_priv *priv)
{
	/* Check alive response for "valid" sign from uCode */
	if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
		/* We had an error bringing up the hardware, so take it
		 * all the way back down so we can try again */
		IWL_DEBUG_INFO("Initialize Alive failed.\n");
		goto restart;
	}

	/* Bootstrap uCode has loaded initialize uCode ... verify inst image.
	 * This is a paranoid check, because we would not have gotten the
	 * "initialize" alive if code weren't properly loaded.  */
	if (iwl_verify_ucode(priv)) {
		/* Runtime instruction load was bad;
		 * take it all the way back down so we can try again */
		IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
		goto restart;
	}

	/* Calculate temperature */
	priv->temperature = iwl4965_get_temperature(priv);

	/* Send pointers to protocol/runtime uCode image ... init code will
	 * load and launch runtime uCode, which will send us another "Alive"
	 * notification. */
	IWL_DEBUG_INFO("Initialization Alive received.\n");
	if (iwl4965_set_ucode_ptrs(priv)) {
		/* Runtime instruction load won't happen;
		 * take it all the way back down so we can try again */
		IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
		goto restart;
	}
	return;

restart:
	queue_work(priv->workqueue, &priv->restart);
}

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static int is_fat_channel(__le32 rxon_flags)
{
	return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
		(rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
}

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int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
{
	int idx = 0;

	/* 4965 HT rate format */
	if (rate_n_flags & RATE_MCS_HT_MSK) {
		idx = (rate_n_flags & 0xff);

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		if (idx >= IWL_RATE_MIMO2_6M_PLCP)
			idx = idx - IWL_RATE_MIMO2_6M_PLCP;
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		idx += IWL_FIRST_OFDM_RATE;
		/* skip 9M not supported in ht*/
		if (idx >= IWL_RATE_9M_INDEX)
			idx += 1;
		if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
			return idx;

	/* 4965 legacy rate format, search for match in table */
	} else {
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		for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
			if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
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				return idx;
	}

	return -1;
}

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/**
 * translate ucode response to mac80211 tx status control values
 */
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void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
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				  struct ieee80211_tx_info *control)
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{
	int rate_index;

	control->antenna_sel_tx =
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		((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
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	if (rate_n_flags & RATE_MCS_HT_MSK)
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		control->flags |= IEEE80211_TX_CTL_OFDM_HT;
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	if (rate_n_flags & RATE_MCS_GF_MSK)
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		control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
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	if (rate_n_flags & RATE_MCS_FAT_MSK)
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		control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
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	if (rate_n_flags & RATE_MCS_DUP_MSK)
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		control->flags |= IEEE80211_TX_CTL_DUP_DATA;
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	if (rate_n_flags & RATE_MCS_SGI_MSK)
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		control->flags |= IEEE80211_TX_CTL_SHORT_GI;
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	rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
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	if (control->band == IEEE80211_BAND_5GHZ)
		rate_index -= IWL_FIRST_OFDM_RATE;
	control->tx_rate_idx = rate_index;
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}
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/*
 * EEPROM handlers
 */

static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
{
	u16 eeprom_ver;
	u16 calib_ver;

	eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);

	calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);

	if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
	    calib_ver < EEPROM_4965_TX_POWER_VERSION)
		goto err;

	return 0;
err:
	IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
		  eeprom_ver, EEPROM_4965_EEPROM_VERSION,
		  calib_ver, EEPROM_4965_TX_POWER_VERSION);
	return -EINVAL;

}
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int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
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{
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	int ret;
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	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);
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	ret = iwl_grab_nic_access(priv);
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	if (ret) {
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		spin_unlock_irqrestore(&priv->lock, flags);
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		return ret;
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	}

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	if (src == IWL_PWR_SRC_VAUX) {
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		u32 val;
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		ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
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					    &val);
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		if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
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			iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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					       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
					       ~APMG_PS_CTRL_MSK_PWR_SRC);
		}
	} else {
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		iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
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				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
				       ~APMG_PS_CTRL_MSK_PWR_SRC);
	}
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	iwl_release_nic_access(priv);
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	spin_unlock_irqrestore(&priv->lock, flags);

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	return ret;
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}

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/*
 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
 * must be called under priv->lock and mac access
 */
static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
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{
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	iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
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}

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static int iwl4965_apm_init(struct iwl_priv *priv)
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{
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	int ret = 0;
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	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
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			  CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
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	/* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
			  CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);

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	/* set "initialization complete" bit to move adapter
	 * D0U* --> D0A* state */
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	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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	/* wait for clock stabilization */
	ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
	if (ret < 0) {
		IWL_DEBUG_INFO("Failed to init the card\n");
		goto out;
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	}

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	ret = iwl_grab_nic_access(priv);
	if (ret)
		goto out;
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	/* enable DMA */
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	iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
						APMG_CLK_VAL_BSM_CLK_RQT);
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	udelay(20);

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	/* disable L1-Active */
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	iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
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			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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	iwl_release_nic_access(priv);
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out:
	return ret;
}

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static void iwl4965_nic_config(struct iwl_priv *priv)
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{
	unsigned long flags;
	u32 val;
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	u16 radio_cfg;
	u8 val_link;
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	spin_lock_irqsave(&priv->lock, flags);

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	if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
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		pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
		/* Enable No Snoop field */
		pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
				       val & ~(1 << 11));
	}

	pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);

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	/* L1 is enabled by BIOS */
	if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
		/* diable L0S disabled L1A enabled */
		iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
	else
		/* L0S enabled L1A disabled */
		iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
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	radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
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	/* write radio config values to register */
	if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
		iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
			    EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
			    EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
			    EEPROM_RF_CFG_DASH_MSK(radio_cfg));
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	/* set CSR_HW_CONFIG_REG for uCode use */
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	iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
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		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
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	priv->calib_info = (struct iwl_eeprom_calib_info *)
		iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);

	spin_unlock_irqrestore(&priv->lock, flags);
}

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static int iwl4965_apm_stop_master(struct iwl_priv *priv)
{
	int ret = 0;
	unsigned long flags;

	spin_lock_irqsave(&priv->lock, flags);

	/* set stop master bit */
	iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);

	ret = iwl_poll_bit(priv, CSR_RESET,
				  CSR_RESET_REG_FLAG_MASTER_DISABLED,
				  CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
	if (ret < 0)
		goto out;

out:
	spin_unlock_irqrestore(&priv->lock, flags);
	IWL_DEBUG_INFO("stop master\n");

	return ret;
}

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static void iwl4965_apm_stop(struct iwl_priv *priv)
{
	unsigned long flags;

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	iwl4965_apm_stop_master(priv);
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	spin_lock_irqsave(&priv->lock, flags);

	iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);

	udelay(10);

	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
	spin_unlock_irqrestore(&priv->lock, flags);
}

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static int iwl4965_apm_reset(struct iwl_priv *priv)
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{
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	int ret = 0;
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	unsigned long flags;

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	iwl4965_apm_stop_master(priv);
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	spin_lock_irqsave(&priv->lock, flags);

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	iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
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	udelay(10);

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	/* FIXME: put here L1A -L0S w/a */

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	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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	ret = iwl_poll_bit(priv, CSR_RESET,
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			  CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			  CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);

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	if (ret)
		goto out;

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	udelay(10);

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	ret = iwl_grab_nic_access(priv);
	if (ret)
		goto out;
	/* Enable DMA and BSM Clock */
	iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
					      APMG_CLK_VAL_BSM_CLK_RQT);
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	udelay(10);
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	/* disable L1A */
	iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
			  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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	iwl_release_nic_access(priv);
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	clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
	wake_up_interruptible(&priv->wait_command_queue);

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out:
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	spin_unlock_irqrestore(&priv->lock, flags);

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	return ret;
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}

#define REG_RECALIB_PERIOD (60)

/**
 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
 *
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 * This callback is provided in order to send a statistics request.
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 *
 * This timer function is continually reset to execute within
 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 * was received.  We need to ensure we receive the statistics in order
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 * to update the temperature used for calibrating the TXPOWER.
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 */
static void iwl4965_bg_statistics_periodic(unsigned long data)
{
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	struct iwl_priv *priv = (struct iwl_priv *)data;
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	if (test_bit(STATUS_EXIT_PENDING, &priv->status))
		return;

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	iwl_send_statistics_request(priv, CMD_ASYNC);
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}

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void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
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{
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	struct iwl4965_ct_kill_config cmd;
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	unsigned long flags;
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	int ret = 0;
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	spin_lock_irqsave(&priv->lock, flags);
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	iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
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		    CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
	spin_unlock_irqrestore(&priv->lock, flags);

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	cmd.critical_temperature_R =
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		cpu_to_le32(priv->hw_params.ct_kill_threshold);

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	ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
			       sizeof(cmd), &cmd);
	if (ret)
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		IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
	else
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		IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
			"critical temperature is %d\n",
			cmd.critical_temperature_R);
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}

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#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
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/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
 * Called after every association, but this runs only once!
 *  ... once chain noise is calibrated the first time, it's good forever.  */
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static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
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{
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	struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
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	if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
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		struct iwl4965_calibration_cmd cmd;
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		memset(&cmd, 0, sizeof(cmd));
		cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
		cmd.diff_gain_a = 0;
		cmd.diff_gain_b = 0;
		cmd.diff_gain_c = 0;
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		if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
				 sizeof(cmd), &cmd))
			IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
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		data->state = IWL_CHAIN_NOISE_ACCUMULATE;
		IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
	}
}

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static void iwl4965_gain_computation(struct iwl_priv *priv,
		u32 *average_noise,
		u16 min_average_noise_antenna_i,
		u32 min_average_noise)
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{
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	int i, ret;
	struct iwl_chain_noise_data *data = &priv->chain_noise_data;
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	data->delta_gain_code[min_average_noise_antenna_i] = 0;
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	for (i = 0; i < NUM_RX_CHAINS; i++) {
		s32 delta_g = 0;
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		if (!(data->disconn_array[i]) &&
		    (data->delta_gain_code[i] ==
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			     CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
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			delta_g = average_noise[i] - min_average_noise;
			data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
			data->delta_gain_code[i] =
				min(data->delta_gain_code[i],
				(u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);

			data->delta_gain_code[i] =
				(data->delta_gain_code[i] | (1 << 2));
		} else {
			data->delta_gain_code[i] = 0;
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		}
	}
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	IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
		     data->delta_gain_code[0],
		     data->delta_gain_code[1],
		     data->delta_gain_code[2]);
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	/* Differential gain gets sent to uCode only once */
	if (!data->radio_write) {
		struct iwl4965_calibration_cmd cmd;
		data->radio_write = 1;
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		memset(&cmd, 0, sizeof(cmd));
		cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
		cmd.diff_gain_a = data->delta_gain_code[0];
		cmd.diff_gain_b = data->delta_gain_code[1];
		cmd.diff_gain_c = data->delta_gain_code[2];
		ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
				      sizeof(cmd), &cmd);
		if (ret)
			IWL_DEBUG_CALIB("fail sending cmd "
				     "REPLY_PHY_CALIBRATION_CMD \n");

		/* TODO we might want recalculate
		 * rx_chain in rxon cmd */

		/* Mark so we run this algo only once! */
		data->state = IWL_CHAIN_NOISE_CALIBRATED;
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	}
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	data->chain_noise_a = 0;
	data->chain_noise_b = 0;
	data->chain_noise_c = 0;
	data->chain_signal_a = 0;
	data->chain_signal_b = 0;
	data->chain_signal_c = 0;
	data->beacon_count = 0;
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}

static void iwl4965_bg_sensitivity_work(struct work_struct *work)
{
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	struct iwl_priv *priv = container_of(work, struct iwl_priv,
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			sensitivity_work);

	mutex_lock(&priv->mutex);

	if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
	    test_bit(STATUS_SCANNING, &priv->status)) {
		mutex_unlock(&priv->mutex);
		return;
	}

	if (priv->start_calib) {
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		iwl_chain_noise_calibration(priv, &priv->statistics);

		iwl_sensitivity_calibration(priv, &priv->statistics);
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	}

	mutex_unlock(&priv->mutex);
	return;
}
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#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
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static void iwl4965_bg_txpower_work(struct work_struct *work)
{
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	struct iwl_priv *priv = container_of(work, struct iwl_priv,
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			txpower_work);

	/* If a scan happened to start before we got here
	 * then just return; the statistics notification will
	 * kick off another scheduled work to compensate for
	 * any temperature delta we missed here. */
	if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
	    test_bit(STATUS_SCANNING, &priv->status))
		return;

	mutex_lock(&priv->mutex);

	/* Regardless of if we are assocaited, we must reconfigure the
	 * TX power since frames can be sent on non-radar channels while
	 * not associated */
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	iwl4965_hw_reg_send_txpower(priv);
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	/* Update last_temperature to keep is_calib_needed from running
	 * when it isn't needed... */
	priv->last_temperature = priv->temperature;

	mutex_unlock(&priv->mutex);
}

/*
 * Acquire priv->lock before calling this function !
 */
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static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
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{
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	iwl_write_direct32(priv, HBUS_TARG_WRPTR,
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			     (index & 0xff) | (txq_id << 8));
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	iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
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}

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/**
 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
 * @scd_retry: (1) Indicates queue will be used in aggregation mode
 *
 * NOTE:  Acquire priv->lock before calling this function !
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 */
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static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
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					struct iwl_tx_queue *txq,
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					int tx_fifo_id, int scd_retry)
{
	int txq_id = txq->q.id;
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	/* Find out whether to activate Tx queue */
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	int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;

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	/* Set up and activate */
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	iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
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			 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
			 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
			 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
			 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
			 IWL49_SCD_QUEUE_STTS_REG_MSK);
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	txq->sched_retry = scd_retry;

	IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
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		       active ? "Activate" : "Deactivate",
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		       scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
}

static const u16 default_queue_to_tx_fifo[] = {
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC0,
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	IWL49_CMD_FIFO_NUM,
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	IWL_TX_FIFO_HCCA_1,
	IWL_TX_FIFO_HCCA_2
};

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int iwl4965_alive_notify(struct iwl_priv *priv)
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{
	u32 a;
	int i = 0;
	unsigned long flags;
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	int ret;
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	spin_lock_irqsave(&priv->lock, flags);

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	ret = iwl_grab_nic_access(priv);
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	if (ret) {
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		spin_unlock_irqrestore(&priv->lock, flags);
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		return ret;
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	}

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	/* Clear 4965's internal Tx Scheduler data base */
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	priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
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	a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
	for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
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		iwl_write_targ_mem(priv, a, 0);
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	for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
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		iwl_write_targ_mem(priv, a, 0);
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	for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
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		iwl_write_targ_mem(priv, a, 0);
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	/* Tel 4965 where to find Tx byte count tables */
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	iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
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		(priv->shared_phys +
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		 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
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	/* Disable chain mode for all queues */
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	iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
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	/* Initialize each Tx queue (including the command queue) */
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	for (i = 0; i < priv->hw_params.max_txq_num; i++) {
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		/* TFD circular buffer read/write indexes */
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		iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
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		iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
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		/* Max Tx Window size for Scheduler-ACK mode */
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		iwl_write_targ_mem(priv, priv->scd_base_addr +
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				IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
				(SCD_WIN_SIZE <<
				IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
				IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
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		/* Frame limit */
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		iwl_write_targ_mem(priv, priv->scd_base_addr +
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				IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
				sizeof(u32),
				(SCD_FRAME_LIMIT <<
				IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
				IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
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	}
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	iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
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				 (1 << priv->hw_params.max_txq_num) - 1);
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	/* Activate all Tx DMA/FIFO channels */
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	priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
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	iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
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	/* Map each Tx/cmd queue to its corresponding fifo */
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	for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
		int ac = default_queue_to_tx_fifo[i];
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		iwl_txq_ctx_activate(priv, i);
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		iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
	}

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	iwl_release_nic_access(priv);
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	spin_unlock_irqrestore(&priv->lock, flags);

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	return ret;
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}

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#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
	.min_nrg_cck = 97,
	.max_nrg_cck = 0,

	.auto_corr_min_ofdm = 85,
	.auto_corr_min_ofdm_mrc = 170,
	.auto_corr_min_ofdm_x1 = 105,
	.auto_corr_min_ofdm_mrc_x1 = 220,

	.auto_corr_max_ofdm = 120,
	.auto_corr_max_ofdm_mrc = 210,
	.auto_corr_max_ofdm_x1 = 140,
	.auto_corr_max_ofdm_mrc_x1 = 270,

	.auto_corr_min_cck = 125,
	.auto_corr_max_cck = 200,
	.auto_corr_min_cck_mrc = 200,
	.auto_corr_max_cck_mrc = 400,

	.nrg_th_cck = 100,
	.nrg_th_ofdm = 100,
};
#endif

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/**
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 * iwl4965_hw_set_hw_params
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 *
 * Called when initializing driver
 */
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int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
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{
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	if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
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	    (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
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		IWL_ERROR("invalid queues_num, should be between %d and %d\n",
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			  IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
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		return -EINVAL;
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	}
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	priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
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	priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
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	priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
	priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
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	if (priv->cfg->mod_params->amsdu_size_8K)
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		priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
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	else
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		priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
	priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
	priv->hw_params.max_stations = IWL4965_STATION_COUNT;
	priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
997

998
999
1000
	priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
	priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
	priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;