s2io.c 246 KB
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/************************************************************************
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 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
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 * Copyright(c) 2002-2007 Neterion Inc.
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 * This software may be used and distributed according to the terms of
 * the GNU General Public License (GPL), incorporated herein by reference.
 * Drivers based on or derived from this code fall under the GPL and must
 * retain the authorship, copyright and license notice.  This file is not
 * a complete program and may only be used when the entire operating
 * system is licensed under the GPL.
 * See the file COPYING in this distribution for more information.
 *
 * Credits:
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 * Jeff Garzik		: For pointing out the improper error condition
 *			  check in the s2io_xmit routine and also some
 *			  issues in the Tx watch dog function. Also for
 *			  patiently answering all those innumerable
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 *			  questions regaring the 2.6 porting issues.
 * Stephen Hemminger	: Providing proper 2.6 porting mechanism for some
 *			  macros available only in 2.6 Kernel.
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 * Francois Romieu	: For pointing out all code part that were
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 *			  deprecated and also styling related comments.
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 * Grant Grundler	: For helping me get rid of some Architecture
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 *			  dependent code.
 * Christopher Hellwig	: Some more 2.6 specific issues in the driver.
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 *
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 * The module loadable parameters that are supported by the driver and a brief
 * explaination of all the variables.
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 *
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 * rx_ring_num : This can be used to program the number of receive rings used
 * in the driver.
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 * rx_ring_sz: This defines the number of receive blocks each ring can have.
 *     This is also an array of size 8.
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 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
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 *		values are 1, 2.
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 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
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 * tx_fifo_len: This too is an array of 8. Each element defines the number of
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 * Tx descriptors that can be associated with each corresponding FIFO.
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 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
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 *     2(MSI_X). Default value is '2(MSI_X)'
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 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
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 *     Possible values '1' for enable '0' for disable. Default is '0'
 * lro_max_pkts: This parameter defines maximum number of packets can be
 *     aggregated as a single large packet
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 * napi: This parameter used to enable/disable NAPI (polling Rx)
 *     Possible values '1' for enable and '0' for disable. Default is '1'
 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
 *      Possible values '1' for enable and '0' for disable. Default is '0'
 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
 *                 Possible values '1' for enable , '0' for disable.
 *                 Default is '2' - which means disable in promisc mode
 *                 and enable in non-promiscuous mode.
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 * multiq: This parameter used to enable/disable MULTIQUEUE support.
 *      Possible values '1' for enable and '0' for disable. Default is '0'
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 ************************************************************************/

#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/ioctl.h>
#include <linux/timex.h>
#include <linux/ethtool.h>
#include <linux/workqueue.h>
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#include <linux/if_vlan.h>
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#include <linux/ip.h>
#include <linux/tcp.h>
#include <net/tcp.h>
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#include <asm/system.h>
#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/div64.h>
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#include <asm/irq.h>
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/* local include */
#include "s2io.h"
#include "s2io-regs.h"

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#define DRV_VERSION "2.0.26.25"
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/* S2io Driver name & version. */
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static char s2io_driver_name[] = "Neterion";
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static char s2io_driver_version[] = DRV_VERSION;
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static int rxd_size[2] = {32,48};
static int rxd_count[2] = {127,85};
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static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
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{
	int ret;

	ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
		(GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));

	return ret;
}

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/*
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 * Cards with following subsystem_id have a link state indication
 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 * macro below identifies these cards given the subsystem_id.
 */
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#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
	(dev_type == XFRAME_I_DEVICE) ?			\
		((((subid >= 0x600B) && (subid <= 0x600D)) || \
		 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
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#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
				      ADAPTER_STATUS_RMAC_LOCAL_FAULT)))

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static inline int is_s2io_card_up(const struct s2io_nic * sp)
{
	return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
}

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/* Ethtool related variables and Macros. */
static char s2io_gstrings[][ETH_GSTRING_LEN] = {
	"Register test\t(offline)",
	"Eeprom test\t(offline)",
	"Link test\t(online)",
	"RLDRAM test\t(offline)",
	"BIST Test\t(offline)"
};

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static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
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	{"tmac_frms"},
	{"tmac_data_octets"},
	{"tmac_drop_frms"},
	{"tmac_mcst_frms"},
	{"tmac_bcst_frms"},
	{"tmac_pause_ctrl_frms"},
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	{"tmac_ttl_octets"},
	{"tmac_ucst_frms"},
	{"tmac_nucst_frms"},
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	{"tmac_any_err_frms"},
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	{"tmac_ttl_less_fb_octets"},
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	{"tmac_vld_ip_octets"},
	{"tmac_vld_ip"},
	{"tmac_drop_ip"},
	{"tmac_icmp"},
	{"tmac_rst_tcp"},
	{"tmac_tcp"},
	{"tmac_udp"},
	{"rmac_vld_frms"},
	{"rmac_data_octets"},
	{"rmac_fcs_err_frms"},
	{"rmac_drop_frms"},
	{"rmac_vld_mcst_frms"},
	{"rmac_vld_bcst_frms"},
	{"rmac_in_rng_len_err_frms"},
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	{"rmac_out_rng_len_err_frms"},
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	{"rmac_long_frms"},
	{"rmac_pause_ctrl_frms"},
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	{"rmac_unsup_ctrl_frms"},
	{"rmac_ttl_octets"},
	{"rmac_accepted_ucst_frms"},
	{"rmac_accepted_nucst_frms"},
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	{"rmac_discarded_frms"},
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	{"rmac_drop_events"},
	{"rmac_ttl_less_fb_octets"},
	{"rmac_ttl_frms"},
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	{"rmac_usized_frms"},
	{"rmac_osized_frms"},
	{"rmac_frag_frms"},
	{"rmac_jabber_frms"},
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	{"rmac_ttl_64_frms"},
	{"rmac_ttl_65_127_frms"},
	{"rmac_ttl_128_255_frms"},
	{"rmac_ttl_256_511_frms"},
	{"rmac_ttl_512_1023_frms"},
	{"rmac_ttl_1024_1518_frms"},
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	{"rmac_ip"},
	{"rmac_ip_octets"},
	{"rmac_hdr_err_ip"},
	{"rmac_drop_ip"},
	{"rmac_icmp"},
	{"rmac_tcp"},
	{"rmac_udp"},
	{"rmac_err_drp_udp"},
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	{"rmac_xgmii_err_sym"},
	{"rmac_frms_q0"},
	{"rmac_frms_q1"},
	{"rmac_frms_q2"},
	{"rmac_frms_q3"},
	{"rmac_frms_q4"},
	{"rmac_frms_q5"},
	{"rmac_frms_q6"},
	{"rmac_frms_q7"},
	{"rmac_full_q0"},
	{"rmac_full_q1"},
	{"rmac_full_q2"},
	{"rmac_full_q3"},
	{"rmac_full_q4"},
	{"rmac_full_q5"},
	{"rmac_full_q6"},
	{"rmac_full_q7"},
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	{"rmac_pause_cnt"},
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	{"rmac_xgmii_data_err_cnt"},
	{"rmac_xgmii_ctrl_err_cnt"},
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	{"rmac_accepted_ip"},
	{"rmac_err_tcp"},
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	{"rd_req_cnt"},
	{"new_rd_req_cnt"},
	{"new_rd_req_rtry_cnt"},
	{"rd_rtry_cnt"},
	{"wr_rtry_rd_ack_cnt"},
	{"wr_req_cnt"},
	{"new_wr_req_cnt"},
	{"new_wr_req_rtry_cnt"},
	{"wr_rtry_cnt"},
	{"wr_disc_cnt"},
	{"rd_rtry_wr_ack_cnt"},
	{"txp_wr_cnt"},
	{"txd_rd_cnt"},
	{"txd_wr_cnt"},
	{"rxd_rd_cnt"},
	{"rxd_wr_cnt"},
	{"txf_rd_cnt"},
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	{"rxf_wr_cnt"}
};

static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
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	{"rmac_ttl_1519_4095_frms"},
	{"rmac_ttl_4096_8191_frms"},
	{"rmac_ttl_8192_max_frms"},
	{"rmac_ttl_gt_max_frms"},
	{"rmac_osized_alt_frms"},
	{"rmac_jabber_alt_frms"},
	{"rmac_gt_max_alt_frms"},
	{"rmac_vlan_frms"},
	{"rmac_len_discard"},
	{"rmac_fcs_discard"},
	{"rmac_pf_discard"},
	{"rmac_da_discard"},
	{"rmac_red_discard"},
	{"rmac_rts_discard"},
	{"rmac_ingm_full_discard"},
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	{"link_fault_cnt"}
};

static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
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	{"\n DRIVER STATISTICS"},
	{"single_bit_ecc_errs"},
	{"double_bit_ecc_errs"},
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	{"parity_err_cnt"},
	{"serious_err_cnt"},
	{"soft_reset_cnt"},
	{"fifo_full_cnt"},
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	{"ring_0_full_cnt"},
	{"ring_1_full_cnt"},
	{"ring_2_full_cnt"},
	{"ring_3_full_cnt"},
	{"ring_4_full_cnt"},
	{"ring_5_full_cnt"},
	{"ring_6_full_cnt"},
	{"ring_7_full_cnt"},
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	{"alarm_transceiver_temp_high"},
	{"alarm_transceiver_temp_low"},
	{"alarm_laser_bias_current_high"},
	{"alarm_laser_bias_current_low"},
	{"alarm_laser_output_power_high"},
	{"alarm_laser_output_power_low"},
	{"warn_transceiver_temp_high"},
	{"warn_transceiver_temp_low"},
	{"warn_laser_bias_current_high"},
	{"warn_laser_bias_current_low"},
	{"warn_laser_output_power_high"},
	{"warn_laser_output_power_low"},
	{"lro_aggregated_pkts"},
	{"lro_flush_both_count"},
	{"lro_out_of_sequence_pkts"},
	{"lro_flush_due_to_max_pkts"},
	{"lro_avg_aggr_pkts"},
	{"mem_alloc_fail_cnt"},
	{"pci_map_fail_cnt"},
	{"watchdog_timer_cnt"},
	{"mem_allocated"},
	{"mem_freed"},
	{"link_up_cnt"},
	{"link_down_cnt"},
	{"link_up_time"},
	{"link_down_time"},
	{"tx_tcode_buf_abort_cnt"},
	{"tx_tcode_desc_abort_cnt"},
	{"tx_tcode_parity_err_cnt"},
	{"tx_tcode_link_loss_cnt"},
	{"tx_tcode_list_proc_err_cnt"},
	{"rx_tcode_parity_err_cnt"},
	{"rx_tcode_abort_cnt"},
	{"rx_tcode_parity_abort_cnt"},
	{"rx_tcode_rda_fail_cnt"},
	{"rx_tcode_unkn_prot_cnt"},
	{"rx_tcode_fcs_err_cnt"},
	{"rx_tcode_buf_size_err_cnt"},
	{"rx_tcode_rxd_corrupt_cnt"},
	{"rx_tcode_unkn_err_cnt"},
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	{"tda_err_cnt"},
	{"pfc_err_cnt"},
	{"pcc_err_cnt"},
	{"tti_err_cnt"},
	{"tpa_err_cnt"},
	{"sm_err_cnt"},
	{"lso_err_cnt"},
	{"mac_tmac_err_cnt"},
	{"mac_rmac_err_cnt"},
	{"xgxs_txgxs_err_cnt"},
	{"xgxs_rxgxs_err_cnt"},
	{"rc_err_cnt"},
	{"prc_pcix_err_cnt"},
	{"rpa_err_cnt"},
	{"rda_err_cnt"},
	{"rti_err_cnt"},
	{"mc_err_cnt"}
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};

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#define S2IO_XENA_STAT_LEN	ARRAY_SIZE(ethtool_xena_stats_keys)
#define S2IO_ENHANCED_STAT_LEN	ARRAY_SIZE(ethtool_enhanced_stats_keys)
#define S2IO_DRIVER_STAT_LEN	ARRAY_SIZE(ethtool_driver_stats_keys)
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#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )

#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
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#define S2IO_TEST_LEN	ARRAY_SIZE(s2io_gstrings)
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#define S2IO_STRINGS_LEN	S2IO_TEST_LEN * ETH_GSTRING_LEN

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#define S2IO_TIMER_CONF(timer, handle, arg, exp)		\
			init_timer(&timer);			\
			timer.function = handle;		\
			timer.data = (unsigned long) arg;	\
			mod_timer(&timer, (jiffies + exp))	\

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/* copy mac addr to def_mac_addr array */
static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
{
	sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
	sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
	sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
	sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
	sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
	sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
}
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/* Add the vlan */
static void s2io_vlan_rx_register(struct net_device *dev,
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				  struct vlan_group *grp)
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{
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	int i;
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	struct s2io_nic *nic = netdev_priv(dev);
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	unsigned long flags[MAX_TX_FIFOS];
	struct mac_info *mac_control = &nic->mac_control;
	struct config_param *config = &nic->config;

	for (i = 0; i < config->tx_fifo_num; i++)
		spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
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	nic->vlgrp = grp;
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	for (i = config->tx_fifo_num - 1; i >= 0; i--)
		spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
				flags[i]);
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}

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/* Unregister the vlan */
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static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
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{
	int i;
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	struct s2io_nic *nic = netdev_priv(dev);
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	unsigned long flags[MAX_TX_FIFOS];
	struct mac_info *mac_control = &nic->mac_control;
	struct config_param *config = &nic->config;

	for (i = 0; i < config->tx_fifo_num; i++)
		spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);

	if (nic->vlgrp)
		vlan_group_set_device(nic->vlgrp, vid, NULL);

	for (i = config->tx_fifo_num - 1; i >= 0; i--)
		spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
			flags[i]);
}

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/*
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 * Constants to be programmed into the Xena's registers, to configure
 * the XAUI.
 */

#define	END_SIGN	0x0
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static const u64 herc_act_dtx_cfg[] = {
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	/* Set address */
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	0x8000051536750000ULL, 0x80000515367500E0ULL,
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	/* Write data */
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	0x8000051536750004ULL, 0x80000515367500E4ULL,
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	/* Set address */
	0x80010515003F0000ULL, 0x80010515003F00E0ULL,
	/* Write data */
	0x80010515003F0004ULL, 0x80010515003F00E4ULL,
	/* Set address */
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	0x801205150D440000ULL, 0x801205150D4400E0ULL,
	/* Write data */
	0x801205150D440004ULL, 0x801205150D4400E4ULL,
	/* Set address */
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	0x80020515F2100000ULL, 0x80020515F21000E0ULL,
	/* Write data */
	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
	/* Done */
	END_SIGN
};

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static const u64 xena_dtx_cfg[] = {
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	/* Set address */
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	0x8000051500000000ULL, 0x80000515000000E0ULL,
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	/* Write data */
	0x80000515D9350004ULL, 0x80000515D93500E4ULL,
	/* Set address */
	0x8001051500000000ULL, 0x80010515000000E0ULL,
	/* Write data */
	0x80010515001E0004ULL, 0x80010515001E00E4ULL,
	/* Set address */
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	0x8002051500000000ULL, 0x80020515000000E0ULL,
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	/* Write data */
	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
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	END_SIGN
};

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/*
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 * Constants for Fixing the MacAddress problem seen mostly on
 * Alpha machines.
 */
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static const u64 fix_mac[] = {
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	0x0060000000000000ULL, 0x0060600000000000ULL,
	0x0040600000000000ULL, 0x0000600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0060600000000000ULL,
	0x0020600000000000ULL, 0x0000600000000000ULL,
	0x0040600000000000ULL, 0x0060600000000000ULL,
	END_SIGN
};

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MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);


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/* Module Loadable parameters. */
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S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
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S2IO_PARM_INT(rx_ring_num, 1);
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S2IO_PARM_INT(multiq, 0);
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S2IO_PARM_INT(rx_ring_mode, 1);
S2IO_PARM_INT(use_continuous_tx_intrs, 1);
S2IO_PARM_INT(rmac_pause_time, 0x100);
S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
S2IO_PARM_INT(shared_splits, 0);
S2IO_PARM_INT(tmac_util_period, 5);
S2IO_PARM_INT(rmac_util_period, 5);
S2IO_PARM_INT(l3l4hdr_size, 128);
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/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
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/* Frequency of Rx desc syncs expressed as power of 2 */
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S2IO_PARM_INT(rxsync_frequency, 3);
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/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
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S2IO_PARM_INT(intr_type, 2);
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/* Large receive offload feature */
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static unsigned int lro_enable;
module_param_named(lro, lro_enable, uint, 0);

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/* Max pkts to be aggregated by LRO at one time. If not specified,
 * aggregation happens until we hit max IP pkt size(64K)
 */
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S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
S2IO_PARM_INT(indicate_max_pkts, 0);
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S2IO_PARM_INT(napi, 1);
S2IO_PARM_INT(ufo, 0);
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S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
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static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
    {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
static unsigned int rx_ring_sz[MAX_RX_RINGS] =
    {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
static unsigned int rts_frm_len[MAX_RX_RINGS] =
    {[0 ...(MAX_RX_RINGS - 1)] = 0 };

module_param_array(tx_fifo_len, uint, NULL, 0);
module_param_array(rx_ring_sz, uint, NULL, 0);
module_param_array(rts_frm_len, uint, NULL, 0);
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/*
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 * S2IO device table.
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 * This table lists all the devices that this driver supports.
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 */
static struct pci_device_id s2io_tbl[] __devinitdata = {
	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
	 PCI_ANY_ID, PCI_ANY_ID},
	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
	 PCI_ANY_ID, PCI_ANY_ID},
	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
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         PCI_ANY_ID, PCI_ANY_ID},
        {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
         PCI_ANY_ID, PCI_ANY_ID},
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	{0,}
};

MODULE_DEVICE_TABLE(pci, s2io_tbl);

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static struct pci_error_handlers s2io_err_handler = {
	.error_detected = s2io_io_error_detected,
	.slot_reset = s2io_io_slot_reset,
	.resume = s2io_io_resume,
};

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static struct pci_driver s2io_driver = {
      .name = "S2IO",
      .id_table = s2io_tbl,
      .probe = s2io_init_nic,
      .remove = __devexit_p(s2io_rem_nic),
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      .err_handler = &s2io_err_handler,
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};

/* A simplifier macro used both by init and free shared_mem Fns(). */
#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)

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/* netqueue manipulation helper functions */
static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
{
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	if (!sp->config.multiq) {
		int i;

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		for (i = 0; i < sp->config.tx_fifo_num; i++)
			sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
	}
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	netif_tx_stop_all_queues(sp->dev);
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}

static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
{
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	if (!sp->config.multiq)
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		sp->mac_control.fifos[fifo_no].queue_state =
			FIFO_QUEUE_STOP;
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	netif_tx_stop_all_queues(sp->dev);
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}

static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
{
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	if (!sp->config.multiq) {
		int i;

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		for (i = 0; i < sp->config.tx_fifo_num; i++)
			sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
	}
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	netif_tx_start_all_queues(sp->dev);
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}

static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
{
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	if (!sp->config.multiq)
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		sp->mac_control.fifos[fifo_no].queue_state =
			FIFO_QUEUE_START;
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	netif_tx_start_all_queues(sp->dev);
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}

static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
{
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	if (!sp->config.multiq) {
		int i;

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		for (i = 0; i < sp->config.tx_fifo_num; i++)
			sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
	}
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	netif_tx_wake_all_queues(sp->dev);
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}

static inline void s2io_wake_tx_queue(
	struct fifo_info *fifo, int cnt, u8 multiq)
{

	if (multiq) {
		if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
			netif_wake_subqueue(fifo->dev, fifo->fifo_no);
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	} else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
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		if (netif_queue_stopped(fifo->dev)) {
			fifo->queue_state = FIFO_QUEUE_START;
			netif_wake_queue(fifo->dev);
		}
	}
}

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/**
 * init_shared_mem - Allocation and Initialization of Memory
 * @nic: Device private variable.
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 * Description: The function allocates all the memory areas shared
 * between the NIC and the driver. This includes Tx descriptors,
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 * Rx descriptors and the statistics block.
 */

static int init_shared_mem(struct s2io_nic *nic)
{
	u32 size;
	void *tmp_v_addr, *tmp_v_addr_next;
	dma_addr_t tmp_p_addr, tmp_p_addr_next;
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	struct RxD_block *pre_rxd_blk = NULL;
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	int i, j, blk_cnt;
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	int lst_size, lst_per_page;
	struct net_device *dev = nic->dev;
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	unsigned long tmp;
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	struct buffAdd *ba;
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	struct mac_info *mac_control;
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	struct config_param *config;
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	unsigned long long mem_allocated = 0;
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	mac_control = &nic->mac_control;
	config = &nic->config;


	/* Allocation and initialization of TXDLs in FIOFs */
	size = 0;
	for (i = 0; i < config->tx_fifo_num; i++) {
		size += config->tx_cfg[i].fifo_len;
	}
	if (size > MAX_AVAILABLE_TXDS) {
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		DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
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		DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
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		return -EINVAL;
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	}

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	size = 0;
	for (i = 0; i < config->tx_fifo_num; i++) {
		size = config->tx_cfg[i].fifo_len;
		/*
		 * Legal values are from 2 to 8192
		 */
		if (size < 2) {
			DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
			DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
			DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
				"are 2 to 8192\n");
			return -EINVAL;
		}
	}

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	lst_size = (sizeof(struct TxD) * config->max_txds);
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	lst_per_page = PAGE_SIZE / lst_size;

	for (i = 0; i < config->tx_fifo_num; i++) {
		int fifo_len = config->tx_cfg[i].fifo_len;
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		int list_holder_size = fifo_len * sizeof(struct list_info_hold);
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		mac_control->fifos[i].list_info = kzalloc(list_holder_size,
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							  GFP_KERNEL);
		if (!mac_control->fifos[i].list_info) {
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			DBG_PRINT(INFO_DBG,
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				  "Malloc failed for list_info\n");
			return -ENOMEM;
		}
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		mem_allocated += list_holder_size;
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	}
	for (i = 0; i < config->tx_fifo_num; i++) {
		int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
						lst_per_page);
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		mac_control->fifos[i].tx_curr_put_info.offset = 0;
		mac_control->fifos[i].tx_curr_put_info.fifo_len =
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		    config->tx_cfg[i].fifo_len - 1;
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		mac_control->fifos[i].tx_curr_get_info.offset = 0;
		mac_control->fifos[i].tx_curr_get_info.fifo_len =
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		    config->tx_cfg[i].fifo_len - 1;
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		mac_control->fifos[i].fifo_no = i;
		mac_control->fifos[i].nic = nic;
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		mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
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		mac_control->fifos[i].dev = dev;
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		for (j = 0; j < page_num; j++) {
			int k = 0;
			dma_addr_t tmp_p;
			void *tmp_v;
			tmp_v = pci_alloc_consistent(nic->pdev,
						     PAGE_SIZE, &tmp_p);
			if (!tmp_v) {
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				DBG_PRINT(INFO_DBG,
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					  "pci_alloc_consistent ");
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				DBG_PRINT(INFO_DBG, "failed for TxDL\n");
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				return -ENOMEM;
			}
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			/* If we got a zero DMA address(can happen on
			 * certain platforms like PPC), reallocate.
			 * Store virtual address of page we don't want,
			 * to be freed later.
			 */
			if (!tmp_p) {
				mac_control->zerodma_virt_addr = tmp_v;
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				DBG_PRINT(INIT_DBG,
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				"%s: Zero DMA address for TxDL. ", dev->name);
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				DBG_PRINT(INIT_DBG,
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				"Virtual address %p\n", tmp_v);
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				tmp_v = pci_alloc_consistent(nic->pdev,
						     PAGE_SIZE, &tmp_p);
				if (!tmp_v) {
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					DBG_PRINT(INFO_DBG,
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					  "pci_alloc_consistent ");
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					DBG_PRINT(INFO_DBG, "failed for TxDL\n");
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					return -ENOMEM;
				}
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				mem_allocated += PAGE_SIZE;
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			}
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			while (k < lst_per_page) {
				int l = (j * lst_per_page) + k;
				if (l == config->tx_cfg[i].fifo_len)
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					break;
				mac_control->fifos[i].list_info[l].list_virt_addr =
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				    tmp_v + (k * lst_size);
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				mac_control->fifos[i].list_info[l].list_phy_addr =
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				    tmp_p + (k * lst_size);
				k++;
			}
		}
	}

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	for (i = 0; i < config->tx_fifo_num; i++) {
		size = config->tx_cfg[i].fifo_len;
		mac_control->fifos[i].ufo_in_band_v
			= kcalloc(size, sizeof(u64), GFP_KERNEL);
		if (!mac_control->fifos[i].ufo_in_band_v)
			return -ENOMEM;
		mem_allocated += (size * sizeof(u64));
	}
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	/* Allocation and initialization of RXDs in Rings */
	size = 0;
	for (i = 0; i < config->rx_ring_num; i++) {
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		if (config->rx_cfg[i].num_rxd %
		    (rxd_count[nic->rxd_mode] + 1)) {
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			DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
			DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
				  i);
			DBG_PRINT(ERR_DBG, "RxDs per Block");
			return FAILURE;
		}
		size += config->rx_cfg[i].num_rxd;
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		mac_control->rings[i].block_count =
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			config->rx_cfg[i].num_rxd /
			(rxd_count[nic->rxd_mode] + 1 );
		mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
			mac_control->rings[i].block_count;
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	}
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	if (nic->rxd_mode == RXD_MODE_1)
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		size = (size * (sizeof(struct RxD1)));
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	else
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		size = (size * (sizeof(struct RxD3)));
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	for (i = 0; i < config->rx_ring_num; i++) {
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		mac_control->rings[i].rx_curr_get_info.block_index = 0;
		mac_control->rings[i].rx_curr_get_info.offset = 0;
		mac_control->rings[i].rx_curr_get_info.ring_len =
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		    config->rx_cfg[i].num_rxd - 1;
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		mac_control->rings[i].rx_curr_put_info.block_index = 0;
		mac_control->rings[i].rx_curr_put_info.offset = 0;
		mac_control->rings[i].rx_curr_put_info.ring_len =
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		    config->rx_cfg[i].num_rxd - 1;
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		mac_control->rings[i].nic = nic;
		mac_control->rings[i].ring_no = i;
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		mac_control->rings[i].lro = lro_enable;
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		blk_cnt = config->rx_cfg[i].num_rxd /
				(rxd_count[nic->rxd_mode] + 1);
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		/*  Allocating all the Rx blocks */
		for (j = 0; j < blk_cnt; j++) {
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			struct rx_block_info *rx_blocks;
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			int l;

			rx_blocks = &mac_control->rings[i].rx_blocks[j];
			size = SIZE_OF_BLOCK; //size is always page size
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			tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
							  &tmp_p_addr);
			if (tmp_v_addr == NULL) {
				/*
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				 * In case of failure, free_shared_mem()
				 * is called, which should free any
				 * memory that was alloced till the
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				 * failure happened.
				 */
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				rx_blocks->block_virt_addr = tmp_v_addr;
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				return -ENOMEM;
			}
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			mem_allocated += size;
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			memset(tmp_v_addr, 0, size);
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			rx_blocks->block_virt_addr = tmp_v_addr;
			rx_blocks->block_dma_addr = tmp_p_addr;
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			rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
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						  rxd_count[nic->rxd_mode],
						  GFP_KERNEL);
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			if (!rx_blocks->rxds)
				return -ENOMEM;
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			mem_allocated +=
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			(sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
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			for (l=0; l<rxd_count[nic->rxd_mode];l++) {
				rx_blocks->rxds[l].virt_addr =
					rx_blocks->block_virt_addr +
					(rxd_size[nic->rxd_mode] * l);
				rx_blocks->rxds[l].dma_addr =
					rx_blocks->block_dma_addr +
					(rxd_size[nic->rxd_mode] * l);
			}
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		}
		/* Interlinking all Rx Blocks */
		for (j = 0; j < blk_cnt; j++) {
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			tmp_v_addr =
				mac_control->rings[i].rx_blocks[j].block_virt_addr;
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			tmp_v_addr_next =
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				mac_control->rings[i].rx_blocks[(j + 1) %
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					      blk_cnt].block_virt_addr;
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			tmp_p_addr =
				mac_control->rings[i].rx_blocks[j].block_dma_addr;
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			tmp_p_addr_next =
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				mac_control->rings[i].rx_blocks[(j + 1) %
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					      blk_cnt].block_dma_addr;

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			pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
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			pre_rxd_blk->reserved_2_pNext_RxD_block =
			    (unsigned long) tmp_v_addr_next;
			pre_rxd_blk->pNext_RxD_Blk_physical =
			    (u64) tmp_p_addr_next;
		}
	}
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	if (nic->rxd_mode == RXD_MODE_3B) {
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		/*
		 * Allocation of Storages for buffer addresses in 2BUFF mode
		 * and the buffers as well.
		 */
		for (i = 0; i < config->rx_ring_num; i++) {
			blk_cnt = config->rx_cfg[i].num_rxd /
			   (rxd_count[nic->rxd_mode]+ 1);
			mac_control->rings[i].ba =
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				kmalloc((sizeof(struct buffAdd *) * blk_cnt),
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				     GFP_KERNEL);
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			if (!mac_control->rings[i].ba)
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				return -ENOMEM;
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			mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
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			for (j = 0; j < blk_cnt; j++) {
				int k = 0;
				mac_control->rings[i].ba[j] =
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					kmalloc((sizeof(struct buffAdd) *
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						(rxd_count[nic->rxd_mode] + 1)),
						GFP_KERNEL);
				if (!mac_control->rings[i].ba[j])
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					return -ENOMEM;
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				mem_allocated += (sizeof(struct buffAdd) *  \
					(rxd_count[nic->rxd_mode] + 1));
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				while (k != rxd_count[nic->rxd_mode]) {
					ba = &mac_control->rings[i].ba[j][k];

					ba->ba_0_org = (void *) kmalloc
					    (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
					if (!ba->ba_0_org)
						return -ENOMEM;
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					mem_allocated +=
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						(BUF0_LEN + ALIGN_SIZE);
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					tmp = (unsigned long)ba->ba_0_org;
					tmp += ALIGN_SIZE;
					tmp &= ~((unsigned long) ALIGN_SIZE);
					ba->ba_0 = (void *) tmp;

					ba->ba_1_org = (void *) kmalloc
					    (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
					if (!ba->ba_1_org)
						return -ENOMEM;
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					mem_allocated
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						+= (BUF1_LEN + ALIGN_SIZE);
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					tmp = (unsigned long) ba->ba_1_org;
					tmp += ALIGN_SIZE;
					tmp &= ~((unsigned long) ALIGN_SIZE);
					ba->ba_1 = (void *) tmp;
					k++;
				}
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			}
		}
	}

	/* Allocation and initialization of Statistics block */
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	size = sizeof(struct stat_block);
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	mac_control->stats_mem = pci_alloc_consistent
	    (nic->pdev, size, &mac_control->stats_mem_phy);

	if (!mac_control->stats_mem) {
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		/*
		 * In case of failure, free_shared_mem() is called, which
		 * should free any memory that was alloced till the
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		 * failure happened.
		 */
		return -ENOMEM;
	}
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	mem_allocated += size;
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	mac_control->stats_mem_sz = size;

	tmp_v_addr = mac_control->stats_mem;
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	mac_control->stats_info = (struct stat_block *) tmp_v_addr;
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	memset(tmp_v_addr, 0, size);
	DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
		  (unsigned long long) tmp_p_addr);
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	mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
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	return SUCCESS;
}

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/**
 * free_shared_mem - Free the allocated Memory
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 * @nic:  Device private variable.
 * Description: This function is to free all memory locations allocated by
 * the init_shared_mem() function and return it to the kernel.
 */

static void free_shared_mem(struct s2io_nic *nic)
{
	int i, j, blk_cnt, size;
	void *tmp_v_addr;
	dma_addr_t tmp_p_addr;
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	struct mac_info *mac_control;
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	struct config_param *config;
	int lst_size, lst_per_page;
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	struct net_device *dev;
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	int page_num = 0;
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	if (!nic)
		return;

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	dev = nic->dev;

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	mac_control = &nic->mac_control;
	config = &nic->config;

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	lst_size = (sizeof(struct TxD) * config->max_txds);
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	lst_per_page = PAGE_SIZE / lst_size;

	for (i = 0; i < config->tx_fifo_num; i++) {
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		page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
							lst_per_page);
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		for (j = 0; j < page_num; j++) {
			int mem_blks = (j * lst_per_page);
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			if (!mac_control->fifos[i].list_info)
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				return;
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			if (!mac_control->fifos[i].list_info[mem_blks].
				 list_virt_addr)
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				break;
			pci_free_consistent(nic->pdev, PAGE_SIZE,
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					    mac_control->fifos[i].
					    list_info[mem_blks].
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					    list_virt_addr,
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					    mac_control->fifos[i].
					    list_info[mem_blks].
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					    list_phy_addr);
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			nic->mac_control.stats_info->sw_stat.mem_freed
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						+= PAGE_SIZE;
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		}
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		/* If we got a zero DMA address during allocation,
		 * free the page now
		 */
		if (mac_control->zerodma_virt_addr) {
			pci_free_consistent(nic->pdev, PAGE_SIZE,
					    mac_control->zerodma_virt_addr,
					    (dma_addr_t)0);
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			DBG_PRINT(INIT_DBG,
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			  	"%s: Freeing TxDL with zero DMA addr. ",
				dev->name);
			DBG_PRINT(INIT_DBG, "Virtual address %p\n",
				mac_control->zerodma_virt_addr);
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			nic->mac_control.stats_info->sw_stat.mem_freed
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						+= PAGE_SIZE;
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		}
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		kfree(mac_control->fifos[i].list_info);
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		nic->mac_control.stats_info->sw_stat.mem_freed +=
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		(nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
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	}

	size = SIZE_OF_BLOCK;
	for (i = 0; i < config->rx_ring_num; i++) {
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		blk_cnt = mac_control->rings[i].block_count;
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		for (j = 0; j < blk_cnt; j++) {
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			tmp_v_addr = mac_control->rings[i].rx_blocks[j].
				block_virt_addr;
			tmp_p_addr = mac_control->rings[i].rx_blocks[j].
				block_dma_addr;
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			if (tmp_v_addr == NULL)
				break;
			pci_free_consistent(nic->pdev, size,
					    tmp_v_addr, tmp_p_addr);
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			nic->mac_control.stats_info->sw_stat.mem_freed += size;
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			kfree(mac_control->rings[i].rx_blocks[j].rxds);
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			nic->mac_control.stats_info->sw_stat.mem_freed +=
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			( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
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		}
	}

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	if (nic->rxd_mode == RXD_MODE_3B) {
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		/* Freeing buffer storage addresses in 2BUFF mode. */
		for (i = 0; i < config->rx_ring_num; i++) {
			blk_cnt = config->rx_cfg[i].num_rxd /
			    (rxd_count[nic->rxd_mode] + 1);
			for (j = 0; j < blk_cnt; j++) {
				int k = 0;
				if (!mac_control->rings[i].ba[j])
					continue;
				while (k != rxd_count[nic->rxd_mode]) {
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					struct buffAdd *ba =
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						&mac_control->rings[i].ba[j][k];
					kfree(ba->ba_0_org);
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					nic->mac_control.stats_info->sw_stat.\
					mem_freed += (BUF0_LEN + ALIGN_SIZE);
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					kfree(ba->ba_1_org);
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					nic->mac_control.stats_info->sw_stat.\
					mem_freed += (BUF1_LEN + ALIGN_SIZE);
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					k++;
				}
				kfree(mac_control->rings[i].ba[j]);
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				nic->mac_control.stats_info->sw_stat.mem_freed +=
					(sizeof(struct buffAdd) *
					(rxd_count[nic->rxd_mode] + 1));
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			}
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			kfree(mac_control->rings[i].ba);
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			nic->mac_control.stats_info->sw_stat.mem_freed +=
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			(sizeof(struct buffAdd *) * blk_cnt);
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		}
	}

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	for (i = 0; i < nic->config.tx_fifo_num; i++) {
		if (mac_control->fifos[i].ufo_in_band_v) {
			nic->mac_control.stats_info->sw_stat.mem_freed
				+= (config->tx_cfg[i].fifo_len * sizeof(u64));
			kfree(mac_control->fifos[i].ufo_in_band_v);
		}
	}

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	if (mac_control->stats_mem) {
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		nic->mac_control.stats_info->sw_stat.mem_freed +=
			mac_control->stats_mem_sz;
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		pci_free_consistent(nic->pdev,
				    mac_control->stats_mem_sz,
				    mac_control->stats_mem,
				    mac_control->stats_mem_phy);
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	}
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}

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/**
 * s2io_verify_pci_mode -
 */

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static int s2io_verify_pci_mode(struct s2io_nic *nic)
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{
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	struct XENA_dev_config __iomem *bar0 = nic->bar0;
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	register u64 val64 = 0;
	int     mode;

	val64 = readq(&bar0->pci_mode);
	mode = (u8)GET_PCI_MODE(val64);

	if ( val64 & PCI_MODE_UNKNOWN_MODE)
		return -1;      /* Unknown PCI mode */
	return mode;
}

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#define NEC_VENID   0x1033
#define NEC_DEVID   0x0125
static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
{
	struct pci_dev *tdev = NULL;
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	while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
		if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
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			if (tdev->bus == s2io_pdev->bus->parent) {
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				pci_dev_put(tdev);
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				return 1;
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			}
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		}
	}
	return 0;
}
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static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
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/**
 * s2io_print_pci_mode -
 */
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static int s2io_print_pci_mode(struct s2io_nic *nic)
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{
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	struct XENA_dev_config __iomem *bar0 = nic->bar0;
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	register u64 val64 = 0;
	int	mode;
	struct config_param *config = &nic->config;

	val64 = readq(&bar0->pci_mode);
	mode = (u8)GET_PCI_MODE(val64);

	if ( val64 & PCI_MODE_UNKNOWN_MODE)
		return -1;	/* Unknown PCI mode */

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	config->bus_speed = bus_speed[mode];

	if (s2io_on_nec_bridge(nic->pdev)) {
		DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
							nic->dev->name);
		return mode;
	}

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	if (val64 & PCI_MODE_32_BITS) {
		DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
	} else {
		DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
	}

	switch(mode) {
		case PCI_MODE_PCI_33:
			DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
			break;
		case PCI_MODE_PCI_66:
			DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
			break;
		case PCI_MODE_PCIX_M1_66:
			DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
			break;
		case PCI_MODE_PCIX_M1_100:
			DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
			break;
		case PCI_MODE_PCIX_M1_133:
			DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
			break;
		case PCI_MODE_PCIX_M2_66:
			DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
			break;
		case PCI_MODE_PCIX_M2_100:
			DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
			break;
		case PCI_MODE_PCIX_M2_133:
			DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
			break;
		default:
			return -1;	/* Unsupported bus speed */
	}

	return mode;
}

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/**
 *  init_tti - Initialization transmit traffic interrupt scheme
 *  @nic: device private variable
 *  @link: link status (UP/DOWN) used to enable/disable continuous
 *  transmit interrupts
 *  Description: The function configures transmit traffic interrupts
 *  Return Value:  SUCCESS on success and
 *  '-1' on failure
 */

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static int init_tti(struct s2io_nic *nic, int link)
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{
	struct XENA_dev_config __iomem *bar0 = nic->bar0;
	register u64 val64 = 0;
	int i;
	struct config_param *config;

	config = &nic->config;

	for (i = 0; i < config->tx_fifo_num; i++) {
		/*
		 * TTI Initialization. Default Tx timer gets us about
		 * 250 interrupts per sec. Continuous interrupts are enabled
		 * by default.
		 */
		if (nic->device_type == XFRAME_II_DEVICE) {
			int count = (nic->config.bus_speed * 125)/2;
			val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
		} else
			val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);

		val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
				TTI_DATA1_MEM_TX_URNG_B(0x10) |
				TTI_DATA1_MEM_TX_URNG_C(0x30) |
				TTI_DATA1_MEM_TX_TIMER_AC_EN;