clock.c 29.5 KB
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/* linux/arch/arm/mach-exynos4/clock.c
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 *
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 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
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 *
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 * EXYNOS4 - Clock support
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>

#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>

#include <mach/map.h>
#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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static struct clk clk_sclk_hdmi27m = {
	.name		= "sclk_hdmi27m",
	.rate		= 27000000,
};

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static struct clk clk_sclk_hdmiphy = {
	.name		= "sclk_hdmiphy",
};

static struct clk clk_sclk_usbphy0 = {
	.name		= "sclk_usbphy0",
	.rate		= 27000000,
};

static struct clk clk_sclk_usbphy1 = {
	.name		= "sclk_usbphy1",
};

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static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
}

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static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
}

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static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
}

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static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
}

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static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
}

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static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}

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static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
}

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static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
}

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static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
}

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static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
}

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static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
}

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static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
}

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static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
}

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static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
}

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static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}

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static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
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{
	return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
}

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/* Core list of CMU_CPU side */

static struct clksrc_clk clk_mout_apll = {
	.clk	= {
		.name		= "mout_apll",
	},
	.sources	= &clk_src_apll,
	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
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};

static struct clksrc_clk clk_sclk_apll = {
	.clk	= {
		.name		= "sclk_apll",
		.parent		= &clk_mout_apll.clk,
	},
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	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
};

static struct clksrc_clk clk_mout_epll = {
	.clk	= {
		.name		= "mout_epll",
	},
	.sources	= &clk_src_epll,
	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
};

static struct clksrc_clk clk_mout_mpll = {
	.clk = {
		.name		= "mout_mpll",
	},
	.sources	= &clk_src_mpll,
	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
};

static struct clk *clkset_moutcore_list[] = {
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	[0] = &clk_mout_apll.clk,
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	[1] = &clk_mout_mpll.clk,
};

static struct clksrc_sources clkset_moutcore = {
	.sources	= clkset_moutcore_list,
	.nr_sources	= ARRAY_SIZE(clkset_moutcore_list),
};

static struct clksrc_clk clk_moutcore = {
	.clk	= {
		.name		= "moutcore",
	},
	.sources	= &clkset_moutcore,
	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
};

static struct clksrc_clk clk_coreclk = {
	.clk	= {
		.name		= "core_clk",
		.parent		= &clk_moutcore.clk,
	},
	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
};

static struct clksrc_clk clk_armclk = {
	.clk	= {
		.name		= "armclk",
		.parent		= &clk_coreclk.clk,
	},
};

static struct clksrc_clk clk_aclk_corem0 = {
	.clk	= {
		.name		= "aclk_corem0",
		.parent		= &clk_coreclk.clk,
	},
	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
};

static struct clksrc_clk clk_aclk_cores = {
	.clk	= {
		.name		= "aclk_cores",
		.parent		= &clk_coreclk.clk,
	},
	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
};

static struct clksrc_clk clk_aclk_corem1 = {
	.clk	= {
		.name		= "aclk_corem1",
		.parent		= &clk_coreclk.clk,
	},
	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
};

static struct clksrc_clk clk_periphclk = {
	.clk	= {
		.name		= "periphclk",
		.parent		= &clk_coreclk.clk,
	},
	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
};

/* Core list of CMU_CORE side */

static struct clk *clkset_corebus_list[] = {
	[0] = &clk_mout_mpll.clk,
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	[1] = &clk_sclk_apll.clk,
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};

static struct clksrc_sources clkset_mout_corebus = {
	.sources	= clkset_corebus_list,
	.nr_sources	= ARRAY_SIZE(clkset_corebus_list),
};

static struct clksrc_clk clk_mout_corebus = {
	.clk	= {
		.name		= "mout_corebus",
	},
	.sources	= &clkset_mout_corebus,
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	.reg_src	= { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
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};

static struct clksrc_clk clk_sclk_dmc = {
	.clk	= {
		.name		= "sclk_dmc",
		.parent		= &clk_mout_corebus.clk,
	},
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	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
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};

static struct clksrc_clk clk_aclk_cored = {
	.clk	= {
		.name		= "aclk_cored",
		.parent		= &clk_sclk_dmc.clk,
	},
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	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
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};

static struct clksrc_clk clk_aclk_corep = {
	.clk	= {
		.name		= "aclk_corep",
		.parent		= &clk_aclk_cored.clk,
	},
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	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
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};

static struct clksrc_clk clk_aclk_acp = {
	.clk	= {
		.name		= "aclk_acp",
		.parent		= &clk_mout_corebus.clk,
	},
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	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
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};

static struct clksrc_clk clk_pclk_acp = {
	.clk	= {
		.name		= "pclk_acp",
		.parent		= &clk_aclk_acp.clk,
	},
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	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
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};

/* Core list of CMU_TOP side */

static struct clk *clkset_aclk_top_list[] = {
	[0] = &clk_mout_mpll.clk,
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	[1] = &clk_sclk_apll.clk,
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};

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static struct clksrc_sources clkset_aclk = {
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	.sources	= clkset_aclk_top_list,
	.nr_sources	= ARRAY_SIZE(clkset_aclk_top_list),
};

static struct clksrc_clk clk_aclk_200 = {
	.clk	= {
		.name		= "aclk_200",
	},
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	.sources	= &clkset_aclk,
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	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
};

static struct clksrc_clk clk_aclk_100 = {
	.clk	= {
		.name		= "aclk_100",
	},
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	.sources	= &clkset_aclk,
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	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
};

static struct clksrc_clk clk_aclk_160 = {
	.clk	= {
		.name		= "aclk_160",
	},
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	.sources	= &clkset_aclk,
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	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
};

static struct clksrc_clk clk_aclk_133 = {
	.clk	= {
		.name		= "aclk_133",
	},
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	.sources	= &clkset_aclk,
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	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
};

static struct clk *clkset_vpllsrc_list[] = {
	[0] = &clk_fin_vpll,
	[1] = &clk_sclk_hdmi27m,
};

static struct clksrc_sources clkset_vpllsrc = {
	.sources	= clkset_vpllsrc_list,
	.nr_sources	= ARRAY_SIZE(clkset_vpllsrc_list),
};

static struct clksrc_clk clk_vpllsrc = {
	.clk	= {
		.name		= "vpll_src",
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		.enable		= exynos4_clksrc_mask_top_ctrl,
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		.ctrlbit	= (1 << 0),
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	},
	.sources	= &clkset_vpllsrc,
	.reg_src	= { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
};

static struct clk *clkset_sclk_vpll_list[] = {
	[0] = &clk_vpllsrc.clk,
	[1] = &clk_fout_vpll,
};

static struct clksrc_sources clkset_sclk_vpll = {
	.sources	= clkset_sclk_vpll_list,
	.nr_sources	= ARRAY_SIZE(clkset_sclk_vpll_list),
};

static struct clksrc_clk clk_sclk_vpll = {
	.clk	= {
		.name		= "sclk_vpll",
	},
	.sources	= &clkset_sclk_vpll,
	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
};

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static struct clk init_clocks_off[] = {
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	{
		.name		= "timers",
		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1<<24),
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	}, {
		.name		= "csis",
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		.devname	= "s5p-mipi-csis.0",
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		.enable		= exynos4_clk_ip_cam_ctrl,
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		.ctrlbit	= (1 << 4),
	}, {
		.name		= "csis",
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		.devname	= "s5p-mipi-csis.1",
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		.enable		= exynos4_clk_ip_cam_ctrl,
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		.ctrlbit	= (1 << 5),
	}, {
		.name		= "fimc",
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		.devname	= "exynos4-fimc.0",
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		.enable		= exynos4_clk_ip_cam_ctrl,
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		.ctrlbit	= (1 << 0),
	}, {
		.name		= "fimc",
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		.devname	= "exynos4-fimc.1",
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		.enable		= exynos4_clk_ip_cam_ctrl,
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		.ctrlbit	= (1 << 1),
	}, {
		.name		= "fimc",
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		.devname	= "exynos4-fimc.2",
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		.enable		= exynos4_clk_ip_cam_ctrl,
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		.ctrlbit	= (1 << 2),
	}, {
		.name		= "fimc",
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		.devname	= "exynos4-fimc.3",
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		.enable		= exynos4_clk_ip_cam_ctrl,
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		.ctrlbit	= (1 << 3),
	}, {
		.name		= "fimd",
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		.devname	= "exynos4-fb.0",
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		.enable		= exynos4_clk_ip_lcd0_ctrl,
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		.ctrlbit	= (1 << 0),
	}, {
		.name		= "fimd",
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		.devname	= "exynos4-fb.1",
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		.enable		= exynos4_clk_ip_lcd1_ctrl,
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		.ctrlbit	= (1 << 0),
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	}, {
		.name		= "sataphy",
		.parent		= &clk_aclk_133.clk,
		.enable		= exynos4_clk_ip_fsys_ctrl,
		.ctrlbit	= (1 << 3),
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	}, {
		.name		= "hsmmc",
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		.devname	= "s3c-sdhci.0",
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		.parent		= &clk_aclk_133.clk,
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 5),
	}, {
		.name		= "hsmmc",
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		.devname	= "s3c-sdhci.1",
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		.parent		= &clk_aclk_133.clk,
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 6),
	}, {
		.name		= "hsmmc",
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		.devname	= "s3c-sdhci.2",
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		.parent		= &clk_aclk_133.clk,
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 7),
	}, {
		.name		= "hsmmc",
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		.devname	= "s3c-sdhci.3",
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		.parent		= &clk_aclk_133.clk,
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 8),
	}, {
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		.name		= "dwmmc",
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		.parent		= &clk_aclk_133.clk,
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 9),
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	}, {
		.name		= "sata",
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		.parent		= &clk_aclk_133.clk,
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 10),
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	}, {
		.name		= "pdma",
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		.devname	= "s3c-pl330.0",
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 0),
	}, {
		.name		= "pdma",
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		.devname	= "s3c-pl330.1",
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 1),
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	}, {
		.name		= "adc",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 15),
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	}, {
		.name		= "keypad",
		.enable		= exynos4_clk_ip_perir_ctrl,
		.ctrlbit	= (1 << 16),
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	}, {
		.name		= "rtc",
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		.enable		= exynos4_clk_ip_perir_ctrl,
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		.ctrlbit	= (1 << 15),
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	}, {
		.name		= "watchdog",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_perir_ctrl,
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		.ctrlbit	= (1 << 14),
	}, {
		.name		= "usbhost",
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		.enable		= exynos4_clk_ip_fsys_ctrl ,
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		.ctrlbit	= (1 << 12),
	}, {
		.name		= "otg",
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		.enable		= exynos4_clk_ip_fsys_ctrl,
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		.ctrlbit	= (1 << 13),
	}, {
		.name		= "spi",
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		.devname	= "s3c64xx-spi.0",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 16),
	}, {
		.name		= "spi",
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		.devname	= "s3c64xx-spi.1",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 17),
	}, {
		.name		= "spi",
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		.devname	= "s3c64xx-spi.2",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 18),
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	}, {
		.name		= "iis",
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		.devname	= "samsung-i2s.0",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 19),
	}, {
		.name		= "iis",
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		.devname	= "samsung-i2s.1",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 20),
	}, {
		.name		= "iis",
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		.devname	= "samsung-i2s.2",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 21),
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	}, {
		.name		= "ac97",
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		.devname	= "samsung-ac97",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 27),
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	}, {
		.name		= "fimg2d",
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		.enable		= exynos4_clk_ip_image_ctrl,
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		.ctrlbit	= (1 << 0),
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	}, {
		.name		= "mfc",
		.devname	= "s5p-mfc",
		.enable		= exynos4_clk_ip_mfc_ctrl,
		.ctrlbit	= (1 << 0),
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	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.0",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 6),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.1",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 7),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.2",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 8),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.3",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 9),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.4",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 10),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.5",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 11),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.6",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 12),
	}, {
		.name		= "i2c",
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		.devname	= "s3c2440-i2c.7",
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		.parent		= &clk_aclk_100.clk,
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 13),
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	}, {
		.name		= "SYSMMU_MDMA",
		.enable		= exynos4_clk_ip_image_ctrl,
		.ctrlbit	= (1 << 5),
	}, {
		.name		= "SYSMMU_FIMC0",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 7),
	}, {
		.name		= "SYSMMU_FIMC1",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 8),
	}, {
		.name		= "SYSMMU_FIMC2",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 9),
	}, {
		.name		= "SYSMMU_FIMC3",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 10),
	}, {
		.name		= "SYSMMU_JPEG",
		.enable		= exynos4_clk_ip_cam_ctrl,
		.ctrlbit	= (1 << 11),
	}, {
		.name		= "SYSMMU_FIMD0",
		.enable		= exynos4_clk_ip_lcd0_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_FIMD1",
		.enable		= exynos4_clk_ip_lcd1_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_PCIe",
		.enable		= exynos4_clk_ip_fsys_ctrl,
		.ctrlbit	= (1 << 18),
	}, {
		.name		= "SYSMMU_G2D",
		.enable		= exynos4_clk_ip_image_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "SYSMMU_ROTATOR",
		.enable		= exynos4_clk_ip_image_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_TV",
		.enable		= exynos4_clk_ip_tv_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "SYSMMU_MFC_L",
		.enable		= exynos4_clk_ip_mfc_ctrl,
		.ctrlbit	= (1 << 1),
	}, {
		.name		= "SYSMMU_MFC_R",
		.enable		= exynos4_clk_ip_mfc_ctrl,
		.ctrlbit	= (1 << 2),
	}
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};

static struct clk init_clocks[] = {
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	{
		.name		= "uart",
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		.devname	= "s5pv210-uart.0",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 0),
	}, {
		.name		= "uart",
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		.devname	= "s5pv210-uart.1",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 1),
	}, {
		.name		= "uart",
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		.devname	= "s5pv210-uart.2",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 2),
	}, {
		.name		= "uart",
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		.devname	= "s5pv210-uart.3",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 3),
	}, {
		.name		= "uart",
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		.devname	= "s5pv210-uart.4",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 4),
	}, {
		.name		= "uart",
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		.devname	= "s5pv210-uart.5",
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		.enable		= exynos4_clk_ip_peril_ctrl,
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		.ctrlbit	= (1 << 5),
	}
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};

static struct clk *clkset_group_list[] = {
	[0] = &clk_ext_xtal_mux,
	[1] = &clk_xusbxti,
	[2] = &clk_sclk_hdmi27m,
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	[3] = &clk_sclk_usbphy0,
	[4] = &clk_sclk_usbphy1,
	[5] = &clk_sclk_hdmiphy,
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	[6] = &clk_mout_mpll.clk,
	[7] = &clk_mout_epll.clk,
	[8] = &clk_sclk_vpll.clk,
};

static struct clksrc_sources clkset_group = {
	.sources	= clkset_group_list,
	.nr_sources	= ARRAY_SIZE(clkset_group_list),
};

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static struct clk *clkset_mout_g2d0_list[] = {
	[0] = &clk_mout_mpll.clk,
	[1] = &clk_sclk_apll.clk,
};

static struct clksrc_sources clkset_mout_g2d0 = {
	.sources	= clkset_mout_g2d0_list,
	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d0_list),
};

static struct clksrc_clk clk_mout_g2d0 = {
	.clk	= {
		.name		= "mout_g2d0",
	},
	.sources	= &clkset_mout_g2d0,
	.reg_src	= { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
};

static struct clk *clkset_mout_g2d1_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_sclk_vpll.clk,
};

static struct clksrc_sources clkset_mout_g2d1 = {
	.sources	= clkset_mout_g2d1_list,
	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d1_list),
};

static struct clksrc_clk clk_mout_g2d1 = {
	.clk	= {
		.name		= "mout_g2d1",
	},
	.sources	= &clkset_mout_g2d1,
	.reg_src	= { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
};

static struct clk *clkset_mout_g2d_list[] = {
	[0] = &clk_mout_g2d0.clk,
	[1] = &clk_mout_g2d1.clk,
};

static struct clksrc_sources clkset_mout_g2d = {
	.sources	= clkset_mout_g2d_list,
	.nr_sources	= ARRAY_SIZE(clkset_mout_g2d_list),
};

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static struct clk *clkset_mout_mfc0_list[] = {
	[0] = &clk_mout_mpll.clk,
	[1] = &clk_sclk_apll.clk,
};

static struct clksrc_sources clkset_mout_mfc0 = {
	.sources	= clkset_mout_mfc0_list,
	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc0_list),
};

static struct clksrc_clk clk_mout_mfc0 = {
	.clk	= {
		.name		= "mout_mfc0",
	},
	.sources	= &clkset_mout_mfc0,
	.reg_src	= { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
};

static struct clk *clkset_mout_mfc1_list[] = {
	[0] = &clk_mout_epll.clk,
	[1] = &clk_sclk_vpll.clk,
};

static struct clksrc_sources clkset_mout_mfc1 = {
	.sources	= clkset_mout_mfc1_list,
	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc1_list),
};

static struct clksrc_clk clk_mout_mfc1 = {
	.clk	= {
		.name		= "mout_mfc1",
	},
	.sources	= &clkset_mout_mfc1,
	.reg_src	= { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
};

static struct clk *clkset_mout_mfc_list[] = {
	[0] = &clk_mout_mfc0.clk,
	[1] = &clk_mout_mfc1.clk,
};

static struct clksrc_sources clkset_mout_mfc = {
	.sources	= clkset_mout_mfc_list,
	.nr_sources	= ARRAY_SIZE(clkset_mout_mfc_list),
};

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static struct clksrc_clk clk_dout_mmc0 = {
	.clk		= {
		.name		= "dout_mmc0",
	},
	.sources = &clkset_group,
	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
};

static struct clksrc_clk clk_dout_mmc1 = {
	.clk		= {
		.name		= "dout_mmc1",
	},
	.sources = &clkset_group,
	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
	.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
};

static struct clksrc_clk clk_dout_mmc2 = {
	.clk		= {
		.name		= "dout_mmc2",
	},
	.sources = &clkset_group,
	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
};

static struct clksrc_clk clk_dout_mmc3 = {
	.clk		= {
		.name		= "dout_mmc3",
	},
	.sources = &clkset_group,
	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
	.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
};

static struct clksrc_clk clk_dout_mmc4 = {
	.clk		= {
		.name		= "dout_mmc4",
	},
	.sources = &clkset_group,
	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
	.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
};

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static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "uclk1",
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			.devname	= "s5pv210-uart.0",
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			.enable		= exynos4_clksrc_mask_peril0_ctrl,
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			.ctrlbit	= (1 << 0),
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		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
	}, {
		.clk		= {
			.name		= "uclk1",
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			.devname	= "s5pv210-uart.1",
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			.enable		= exynos4_clksrc_mask_peril0_ctrl,
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			.ctrlbit	= (1 << 4),
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		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
	}, {
		.clk		= {
			.name		= "uclk1",
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			.devname	= "s5pv210-uart.2",
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			.enable		= exynos4_clksrc_mask_peril0_ctrl,
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			.ctrlbit	= (1 << 8),
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		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
	}, {
		.clk		= {
			.name		= "uclk1",
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			.devname	= "s5pv210-uart.3",
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			.enable		= exynos4_clksrc_mask_peril0_ctrl,
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			.ctrlbit	= (1 << 12),
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		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_pwm",
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			.enable		= exynos4_clksrc_mask_peril0_ctrl,
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			.ctrlbit	= (1 << 24),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
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	}, {
		.clk		= {
			.name		= "sclk_csis",
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			.devname	= "s5p-mipi-csis.0",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 24),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_csis",
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			.devname	= "s5p-mipi-csis.1",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 28),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
	}, {
		.clk		= {
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			.name		= "sclk_cam0",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 16),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
	}, {
		.clk		= {
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			.name		= "sclk_cam1",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 20),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_fimc",
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			.devname	= "exynos4-fimc.0",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 0),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_fimc",
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			.devname	= "exynos4-fimc.1",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 4),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_fimc",
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			.devname	= "exynos4-fimc.2",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 8),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_fimc",
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			.devname	= "exynos4-fimc.3",
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			.enable		= exynos4_clksrc_mask_cam_ctrl,
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			.ctrlbit	= (1 << 12),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_fimd",
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			.devname	= "exynos4-fb.0",
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			.enable		= exynos4_clksrc_mask_lcd0_ctrl,
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			.ctrlbit	= (1 << 0),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_fimd",
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			.devname	= "exynos4-fb.1",
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			.enable		= exynos4_clksrc_mask_lcd1_ctrl,
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			.ctrlbit	= (1 << 0),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_sata",
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			.enable		= exynos4_clksrc_mask_fsys_ctrl,
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			.ctrlbit	= (1 << 24),
		},
		.sources = &clkset_mout_corebus,
		.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
		.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_spi",
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			.devname	= "s3c64xx-spi.0",
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			.enable		= exynos4_clksrc_mask_peril1_ctrl,
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			.ctrlbit	= (1 << 16),
		},
		.sources = &clkset_group,
		.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
		.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
	}, {
		.clk		= {
			.name		= "sclk_spi",
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			.devname	= "s3c64xx-spi.1",
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