Commit 26f60603 authored by David Johnson's avatar David Johnson

Add lame aarch64 userspace support.

We don't (can't) have runtime L1 cache size detection on aarch64 without
help.  Of course, line size is always 64 bytes (and that can be found at
runtime); but the total L1 dcache size is not discoverable unless the
kernel (or something else at EL0) has flipped the ECT bit in the system
control register.  This could well be why getconf LEVEL1_DCACHE_SIZE
fails.  In any case, I can't see how it would work.

So, abuse the fact that no aarch64 impl has L1 dcache < 32KB and be happy.
parent 41cd2114
Pipeline #1867 passed with stage
in 16 seconds
......@@ -178,6 +178,13 @@ static inline void __cap_clear_bit(int nr, volatile unsigned long *addr)
_min1 < _min2 ? _min1 : _min2; })
#ifdef __aarch64__
static __always_inline unsigned long __ffs(unsigned long word)
return __builtin_ctzl(word);
#define ffz(x) __ffs(~(x))
static inline unsigned long ffz(unsigned long word)
asm("rep; bsf %1,%0"
......@@ -185,6 +192,7 @@ static inline unsigned long ffz(unsigned long word)
: "r"(~word));
return word;
static unsigned long find_first_zero_bit(const unsigned long *addr,
unsigned long size)
......@@ -7,6 +7,15 @@ int __cache_lines;
int __cache_line_size;
int __l1_cache_size;
#ifdef __aarch64__
static __always_inline int __get_l1_cache_size(int *size, int *line) {
if (size)
*size = 32078;
if (line)
*line = 64;
return 0;
#define cpuid(func,ax,bx,cx,dx) \
__asm__ __volatile__ ("cpuid": \
"=a" (ax), "=b" (bx), "=c" (cx), "=d" (dx) : "a" (func), "b" (bx), "c" (cx), "d" (dx));
......@@ -40,6 +49,7 @@ static int __get_l1_cache_size(int *size, int *line)
return 0;
int __cptr_init(void)
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment