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Keir Fraser authored
No need to wbinvd before HLT (entering C1) as the processor continues to participate in the full cache coherency protocol in this sleep state. Signed-off-by: Keir Fraser <keir@xen.org>
a5629197
No need to wbinvd before HLT (entering C1) as the processor continues
to participate in the full cache coherency protocol in this sleep
state.
Signed-off-by: Keir Fraser <keir@xen.org>