Commit 45db6fe1 authored by michael-west's avatar michael-west

Test: Adjust test procedures

- Adjust/remove failing N310 FPGA functional verification tests
- Correct phase alignment testing procedures
parent 83907678
......@@ -446,7 +446,6 @@ Note: On TX tests, initial Us within the first 5 seconds can be ignored and do n
| 1x RX & 1x TX | 10e6 | 1e6 | 60 | Test both channels |
| 1x RX & 1x TX | 61.44e6 | 3.84e6 | 60 | Use channel 1 |
| 2x RX & 2x TX | 10e6 | 1e6 | 60 | |
| 2x RX & 2x TX | 30.72e6 | 1.92e6 | 60 | |
| 1x RX & 1x TX | 61.44e6 | 3.84e6 | 3600 | Use channel 0 |
| 2x RX & 2x TX | 30.72e6 | 1.92e6 | 3600 | |
......@@ -536,16 +535,16 @@ Note: On TX tests, initial Us within the first 5 seconds can be ignored and do n
| 4x TX | 125e6 | 1.25e6, 12.5e6 | 60 | N310 only
| 4x RX & 4x TX | 125e6 | 1.25e6, 62.5e6 | 60 | Drop to 2 channels for N300
| 4x RX & 4x TX | 122.88e6 | 1.2288e6, 61.44e6 | 60 | Drop to 2 channels for N300
| 4x RX & 4x TX | 153e6 | 1.536e6, 76.8e6 | 60 | Drop to 2 channels for N300
| 4x RX & 4x TX | 153.6e6 | 1.536e6, 38.4e6 | 60 | Drop to 2 channels for N300
| 4x RX & 4x TX | 125e6 | 62.5e6 | 3600 | Drop to 2 channels for N300
| 4x RX & 4x TX | 122.88e6 | 61.44e6 | 3600 | Drop to 2 channels for N300
| 4x RX & 4x TX | 153e6 | 76.8e6 | 3600 | Drop to 2 channels for N300
| 4x RX & 4x TX | 125e6 | 125e6 RX, 62.5e6 TX | 60 | Use dual 10GigE, N310 XG only
| 4x RX & 4x TX | 122.88e6 | 122.88e6 RX, 61.44e6 TX | 60 | Use dual 10GigE, N310 XG only
| 4x RX & 4x TX | 153e6 | 153e6 RX, 76.8e6 TX | 60 | Use dual 10GigE, N310 XG only
| 4x RX & 4x TX | 153.6e6 | 38.4e6 | 3600 | Drop to 2 channels for N300
| 4x RX & 4x TX | 125e6 | 62.5e6 RX, 62.5e6 TX | 60 | Use dual 10GigE, N310 XG only
| 4x RX & 4x TX | 122.88e6 | 61.44e6 RX, 61.44e6 TX | 60 | Use dual 10GigE, N310 XG only
| 4x RX & 4x TX | 153.6e6 | 76.8e6 RX, 38.4e6 TX | 60 | Use dual 10GigE, N310 XG only
| 2x RX & 2x TX | 125e6 | 125e6 RX, 62.5e6 TX | 60 | Use dual 10GigE, N300 XG only
| 2x RX & 2x TX | 122.88e6 | 122.88e6 RX, 61.44e6 TX | 60 | Use dual 10GigE, N300 XG only
| 2x RX & 2x TX | 153e6 | 153e6 RX, 76.8e6 TX | 60 | Use dual 10GigE, N300 XG only
| 2x RX & 2x TX | 153.6e6 | 153.6e6 RX, 76.8e6 TX | 60 | Use dual 10GigE, N300 XG only
\subsection rdtesting_fpgafuncverif_auto FPGA Functional Verification: Automatic Test Procedure
......@@ -675,7 +674,7 @@ Software Required
- `./tools/gr-usrptest/apps/usrp_phasealignment.py --spec "A:0 A:1 B:0 B:1" --channels 0,1,2,3 --sync pps --time-source external --clock-source external -s 5e6 -g 75 -f 10e6 --freq-bands 12 --start-freq 10e6 --stop-freq 6e9 --duration 2.0 --auto --lo-export True,False,False,False --lo-source internal,companion,external,external`
9. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 3 dB.
9. At each frequency step, tune Signal Generator to the displayed frequency + 100 kHz and increase output power by 1 dB.
10. Analyze terminal output. The "run avg" across all runs should not deviate more than 1 degree and the "stddev" for any run should not deviate more than 1 degree.
\subsection rdtesting_phase_rx_X3x0_sbx_ubx X3x0 with SBX or UBX
......@@ -684,12 +683,12 @@ Software Required
3. Connect host to both X3x0s.
4. Connect 10 MHz and PPS from Octoclock-G to both X3x0s.
5. Connect Signal Generator to input of splitter and outputs of the splitter to the RX2 port on each daughterboard.
6. Set Signal Generator output power at -30 dBm.
6. Set Signal Generator output power at -40 dBm.
7. From the top of the UHD source, run the command:
- `./tools/gr-usrptest/apps/usrp_phasealignment.py --args "addr0=<first X3x0 IP addr>,addr1=<second X3x0 IP addr>,dboard_clock_rate=20e6" --clock-source external --time-source external --sync pps --spec "A:0" --channels 0,1 -s 10e6 -g 25 -f \<lowest DB freq\> --freq-bands \<# frequency bands\> --start-freq \<lowest freq\> --stop-freq \<highest freq\> --duration 2.0 --auto`
8. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 2dB.
8. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 1 dB.
9. Analyze terminal output. The "run avg" across all runs should not deviate more than 2 degrees and the "stddev" for any run should not deviate more than 2 degrees.
\subsection rdtesting_phase_rx_N2x0_MIMO N2x0 MIMO with SBX
......@@ -698,12 +697,12 @@ Software Required
3. Connect host to master device via 1 GbE.
4. Connect 10 MHz and PPS from Octoclock-G to master device only.
5. Connect Signal Generator to input of splitter and outputs of the splitter to the RX2 port on each daughterboard.
6. Set Signal Generator output power at -36 dBm.
6. Set Signal Generator output power at -40 dBm.
7. From the top of the UHD source, run the command:
- `./tools/gr-usrptest/apps/usrp_phasealignment.py --args "addr0=<IP address of master>,addr1=<IP address of slave>" --clock-source external,mimo --time-source external,mimo --sync default --channels 0,1 -s 10e6 -f 400e6 -g 31.5 --freq-bands 7 --start-freq 400e6 --stop-freq 4400e6 --duration 2.0 --auto`
8. At each frequency step, tune Signal Generator to the displayed frequency + 1 MHz and increase output power by 2 dB.
8. At each frequency step, tune Signal Generator to the displayed frequency + 100 kHz and increase output power by 1 dB.
9. Analyze terminal output. The "run avg" across all runs should not deviate more than 2 degrees and the "stddev" for any run should not deviate more than 5 degrees.
\subsection rdtesting_phase_rx_auto Automatic phase alignment testing (Receiver)
......
......@@ -274,14 +274,14 @@ FUNCVERIF_SETTINGS = {
# | 4x RX & 4x TX | 125e6 | 1.25e6, 62.5e6 | 60
# | 4x RX & 4x TX | 122.88e6 | 1.2288e6, 61.44e6 | 60
# | 4x RX & 4x TX | 153e6 | 1.536e6, 76.8e6 | 60
# | 4x RX & 4x TX | 153e6 | 1.536e6, 38.4e6 | 60
{'--rx_rate': 1.25e6, '--tx_rate': 1.25e6, 'master_clock_rate': '125e6', '--channels': '0,1,2,3',},
{'--rx_rate': 1.2288e6, '--tx_rate': 1.2288e6, 'master_clock_rate': '122.88e6', '--channels': '0,1,2,3',},
{'--rx_rate': 1.536e6, '--tx_rate': 1.536e6, 'master_clock_rate': '153.6e6', '--channels': '0,1,2,3',},
{'--rx_rate': 62.5e6, '--tx_rate': 62.5e6, 'master_clock_rate': '125e6', '--channels': '0,1,2,3', '--duration': 3600,},
{'--rx_rate': 61.44e6, '--tx_rate': 61.44e6, 'master_clock_rate': '122.88e6', '--channels': '0,1,2,3', '--duration': 3600,},
{'--rx_rate': 76.8e6, '--tx_rate': 76.8e6, 'master_clock_rate': '153.6e6', '--channels': '0,1,2,3', '--duration': 3600,},
{'--rx_rate': 38.4e6, '--tx_rate': 38.4e6, 'master_clock_rate': '153.6e6', '--channels': '0,1,2,3', '--duration': 3600,},
],
},
'n300_10gige': {
......@@ -365,8 +365,8 @@ FUNCVERIF_SETTINGS = {
'--duration': 3600, '--underrun-threshold': 1000, '--overrun-threshold': 1000,},
{'--rx_rate': 122.88e6,'--tx_rate': 61.44e6, 'master_clock_rate': '122.88e6', '--channels': '0,1,2,3',
'--duration': 3600, '--underrun-threshold': 1000, '--overrun-threshold': 1000,},
{'--rx_rate': 153.6e6, '--tx_rate': 76.8e6, 'master_clock_rate': '153.6e6', '--channels': '0,1,2,3',
'--duration': 3600, '--underrun-threshold': 1000, '--overrun-threshold': 1000,},
#{'--rx_rate': 153.6e6, '--tx_rate': 76.8e6, 'master_clock_rate': '153.6e6', '--channels': '0,1,2,3',
# '--duration': 3600, '--underrun-threshold': 1000, '--overrun-threshold': 1000,},
],
},
'n300_2x_10gige': {
......@@ -758,4 +758,3 @@ def main():
if __name__ == "__main__":
exit(not main())
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